| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 711202000 |
Address mapping (e.g., conversion, translation)
| 909 |
| 711216000 |
Hashing
| 71 |
| 711217000 |
Generating a particular pattern/sequence of addresses
| 27 |
| 711213000 |
Generating prefetch, look-ahead, jump, or predictive address
| 19 |
| 711211000 |
Address multiplexing or address bus manipulation
| 18 |
| 711221000 |
Using table
| 11 |
| 711214000 |
Operand address generation
| 9 |
| 711219000 |
Incrementing, decrementing, or shifting circuitry
| 8 |
| 711201000 |
Slip control, misaligning, boundary alignment
| 8 |
| 711220000 |
Combining two or more values to create address
| 8 |
| 711212000 |
Varying address bit-length or size | 5 |
| 20090198954 | Method and system for generating location codes - The present disclosure provides a method for generating a standardized location code is provided that comprises extracting an address component from an input location data record, parsing the address component into one or more address words, and processing the address words by validating the address words one by one using one or more validation rules specific to the input location data record. The method also includes constructing the standardized location code by assembling the processed address words and producing an updated location data file to be shared with a plurality of subscribing applications. | 08-06-2009 |
| 20120297162 | Method for Detecting Address Match in a Deeply Pipelined Processor Design - A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution. | 11-22-2012 |
| 20120324205 | MEMORY MANAGEMENT TABLE PROCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A memory management table processing method for storing a plurality of entries belonging to a plurality of memory management tables into a buffer memory of a memory storage apparatus is provided, wherein each of the entries has at least one invalid bit. The present method includes following steps. An area corresponding to each of the memory management tables is configured in the buffer memory. Invalid bit information corresponding to each of the memory management tables is recorded. The invalid bit in each of the entries is removed according to the invalid bit information corresponding to each of the memory management tables, so as to generate a valid data stream corresponding to each of the entries. Each of the valid data streams is written into the corresponding area in the buffer memory. Accordingly, the storage space of the buffer memory can be efficiently utilized. | 12-20-2012 |
| 20140089632 | DIVISION OF NUMERICAL VALUES BASED ON SUMMATIONS AND MEMORY MAPPING IN COMPUTING SYSTEMS - Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (⅓) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers. | 03-27-2014 |
| 20150095613 | ASSET MANAGEMENT DEVICE AND METHOD IN A HARDWARE PLATFORM - An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address. | 04-02-2015 |
| 711215000 |
In response to microinstruction | 2 |
| 20140195774 | APPARATUS AND METHOD FOR SLIDING WINDOW DATA ACCESS - An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers. | 07-10-2014 |
| 20140351555 | DIGITAL SIGNAL PROCESSOR AND METHOD FOR ADDRESSING A MEMORY IN A DIGITAL SIGNAL PROCESSOR - In a digital signal processor comprising at least one vector execution unit and at least a first memory unit a third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit said third unit being connectable to the first memory unit through the on-chip network, in such a way that data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit. This enables fast reading from and writing to a memory unit of data in any desired order. | 11-27-2014 |
| Entries |
| Document | Title | Date |
|---|
| 20080222382 | PERFORMANCE MONITORING DEVICE AND METHOD THEREOF - A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events. | 09-11-2008 |
| 20080229050 | DYNAMIC PAGE ON DEMAND BUFFER SIZE FOR POWER SAVINGS - A portable electronic device includes a processing device, a memory operatively coupled to said processing device, said memory comprising a plurality of blocks, wherein at least one block of the plurality of blocks may be powered independent of other blocks of the plurality of blocks, and a logic circuit operative to dynamically adjust a demand page buffer size within the memory and utilized by the processor, thereby permitting a corresponding adjustment of a number of powered memory blocks within the memory. | 09-18-2008 |
| 20080229051 | Broadcasting Instructions/Data to a Plurality of Processors in a Multiprocessor Device Via Aliasing - A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data. | 09-18-2008 |
| 20080250221 | Contention detection with data consolidation - A multiple computer system is disclosed in which n computers (M | 10-09-2008 |
| 20080288740 | Method and Device for Generating an Identification Data Block for a Data Carrier - The invention relates to a method for generating an identification data block (ID) for a data carrier ( | 11-20-2008 |
| 20080288741 | Data Access Tracing - A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address. | 11-20-2008 |
| 20090019252 | System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination - A system, method, and program product are provided that identifies a cache set using Translation LookAside Buffer (TLB) attributes. When a virtual address is requested, the method, system, and program product identifies a cache set using buffer attributes. When a virtual address is received, an attempt is made to load the received virtual address from a cache. When the attempt results in a cache miss, a page is identified within a Translation LookAside Buffer that includes the virtual address. A class identifier is then retrieved from the identified page, with the class identifier identifying a cache set that is selected from the cache. | 01-15-2009 |
| 20090024822 | CIRCUIT FOR TRANSFOMING ADDRESS - A circuit for transforming memory address is disclosed. A first memory address is transformed into a second memory address with more bits than the first memory address for providing a memory. The memory space is an even multiple of the maximum of the first memory address. Therefore a large memory can be used as a small memory. | 01-22-2009 |
| 20090031101 | DATA PROCESSING SYSTEM - Before arbitration is performed in an arbitration section, an access from a master is kept in a waiting state until update of a conversion table buffer is performed, and an address conversion section is provided in a subsequent stage of the arbitration section. Without waiting for the completion of buffer update, an access is issued in advance at a time when it is assured that update is completed at the completion of address conversion. Thus, influences of waiting buffer update on another master can be eliminated and access latency can be reduced. | 01-29-2009 |
| 20090055619 | DISK FORMATTER AND METHODS FOR USE THEREWITH - A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data. | 02-26-2009 |
| 20090063808 | Microprocessor and method of processing data - A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part. | 03-05-2009 |
| 20090089536 | METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES - A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations. | 04-02-2009 |
| 20090292898 | PROCESSOR WITH ADDRESS GENERATOR - A processor for processing data is provided. The processor comprises an address generator, which is operative to generate an address based on a base address and a fractional step (Δ). | 11-26-2009 |
| 20090319753 | HYBRID LINEAR VALIDATION ALGORITHM FOR SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEMS - A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation. | 12-24-2009 |
| 20100030996 | System and Method for Forensic Identification of Elements Within a Computer System - A system and method for employing memory forensic techniques to determine operating system type, memory management configuration, and virtual machine status on a running computer system. The techniques apply advanced techniques in a fashion to make them usable and accessible by Information Technology professionals that may not necessarily be versed in the specifics of memory forensic methodologies and theory. | 02-04-2010 |
| 20100058022 | ADAPTIVE BUFFER DEVICE AND METHOD THEREOF - An adaptive buffer device includes a plurality of entries each including an address field and a record block, and a control unit for selectively setting each entry to one of a normal status and a transformed status. When the control unit sets a first one of the entries to the normal status, the address field thereof records a first address, and the record block thereof records data corresponding to the first address and data corresponding to addresses adjacent to the first address. When the control unit sets a second one of the entries to the transformed status, the control unit reconfigures the address field and the record block thereof into a plurality of units, each of which includes a second address, data corresponding to the second address, and data corresponding to addresses adjacent to the second address. In addition, an adaptive buffer method is also disclosed. | 03-04-2010 |
| 20100146238 | System and Method for Generating Real Addresses in Data Processing Architectures - A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to a data memory. A connection ID may be received in association with the access request. This connection ID may include a buffer ID designating a buffer in data memory to which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into a real address of the data memory, and accessing the data in the data memory at a location corresponding to the real address. | 06-10-2010 |
| 20100153681 | Block Driven Computation With An Address Generation Accelerator - A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation. | 06-17-2010 |
| 20100268910 | FLEXRAY SYSTEM USING EFFICIENT STORAGE OF INSTRUCTIONS - A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space. | 10-21-2010 |
| 20100306496 | APPARATUS AND METHOD FOR ADDRESS GENERATION FOR ARRAY PROCESSOR AND ARRAY PROCESSOR - In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers. | 12-02-2010 |
| 20110107055 | Diagonally accessed memory array circuit - A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether. | 05-05-2011 |
| 20110125982 | MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF CONTROLLING THE MEMORY DEVICE - A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal. | 05-26-2011 |
| 20120017063 | MECHANISM TO HANDLE PERIPHERAL PAGE FAULTS - A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memory. The processor is notified that the page request is present in the queue. The processor may be notified with an interrupt of a new queue entry. The processor processes the page service request and the peripheral device is notified of the completion of the processing of the request. | 01-19-2012 |
| 20120102293 | TRANSMISSION DEVICE, TRANSMISSION METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - A transmission device includes a plurality of memory units storing requests for processing information stored in a memory. Moreover, when a request from a first device is received, the transmission device analyzes the received request to specify an address range including a memory address storing data to be subjected to the requested processing. The transmission device stores requests in different memory units for each address range. Moreover, the transmission device determines for each memory unit whether the stored requests are being executed by a second device. The transmission device transmits a request which is stored in a memory unit and which is determined to be not being executed, to the second device. | 04-26-2012 |
| 20120117354 | STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD - According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller. | 05-10-2012 |
| 20120239902 | AREA EFFICIENT COUNTERS ARRAY SYSTEM AND METHOD FOR UPDATING COUNTERS - A counters array system comprises a memory device having a plurality of addressable memory locations for storing counter-values; a plurality of delta-counter devices. Each delta-counter device is operable to hold a maximum delta-value corresponding to a maximum number of occurrences of an event during a time duration between two counter scans controlled by a scan control unit. Each delta-counter device has an input connected to receive a signal from an event source corresponding to an occurrence of the event, and an output connected to provide a delta-value representing an accumulated number of occurrences of the event to a delta-count update circuit. The delta-count update circuit is connected to the memory device and the counter scan control unit, and being arranged to receive the delta-value and an address of a corresponding counter-value, read the counter-value from the memory device, and provide an updated counter-value incremented by the delta-value to the memory device. | 09-20-2012 |
| 20120317391 | RELEASING BLOCKS OF STORAGE CLASS MEMORY - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 12-13-2012 |
| 20120317392 | CHAINING MOVE SPECIFICATION BLOCKS - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 12-13-2012 |
| 20120317393 | DATA RETURNED RESPONSIVE TO EXECUTING A START SUBCHANNEL INSTRUCTION - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 12-13-2012 |
| 20120324204 | Memory Having information Refinement Detection Function, Information Detection Method Using Memory, Device Including Memory, Information Detection Method, Method For Using Memory, And Memory Address Comparison Circuit - There is provided an externally readable memory for storing information in each memory address, and this memory is provided with an information refinement detection function; this memory comprises: an input means for entering first input data for comparing data items stored in the memory and second input data for comparing addresses in the memory, wherein the first and second comparison data are externally; means for determining matches/mismatches of both data items stored in the memory and addresses of the memory according to both of the input data provided by the input means, and further performing logic operations on both of the match/mismatch determination results; and means for outputting addresses with positive results of the logic operations. This memory may be applicable in a broad range of fields including intelligent information search as well as artificial intelligence. | 12-20-2012 |
| 20130124819 | OBJECT TRANSFORMATION OF ARRAYS OF FORMULAS AND VALUES - Embodiments of the invention relate to reducing memory required to store an array of formulas and values corresponding to a formula-array. A set of formula-array representations is provided and arranged in a successive order. Each formula-array representation is evaluated for an associated memory requirement to support use thereof, followed by conversion to a structure of the formula-array representation at a successive level. Selection of the formula-array representation is determined based upon a minimal memory requirement from the formula-array representations in the order. | 05-16-2013 |
| 20160132269 | METHOD AND APPARATUS FOR SETTING HIGH ADDRESS BITS IN A MEMORY MODULE - Provided are a method and apparatus for setting high address bits in a memory module. A memory module controller in the memory module, having pins to communicate on a bus, determines whether high address bits are available for the memory module, uses a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module, and uses values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space. | 05-12-2016 |
