| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438710000 |
By creating electric field (e.g., plasma, glow discharge, etc.)
| 739 |
| 438708000 |
Photo-induced etching
| 18 |
| 438733000 |
Using or orientation dependent etchant (i.e., anisotropic etchant) | 4 |
| 20080305644 | Method of manufacturing semiconductor device including trench-forming process - In a manufacturing method of a semiconductor device, a trench is formed in a semiconductor substrate by an anisotropic dry etching so as to have an aspect ratio greater than or equal to 10, and a damaged layer that is generated in a wall and a bottom of the trench due to the anisotropic dry etching is removed by an isotropic dry etching. The isotropic dry etching is performed with a first gas including carbon and fluorine and a second gas including oxygen. A temperature of the semiconductor substrate is controlled so that the damaged layer is removed from a whole surface of the wall and the bottom in the isotropic dry etching. | 12-11-2008 |
| 20090130857 | METHOD OF MANUFACTURING A STRUCTURE BASED ON ANISOTROPIC ETCHING, AND SILICON SUBSTRATE WITH ETCHING MASK - A method of manufacturing a structure includes a first step of forming, on a monocrystal silicon substrate having a (100) surface as a principal surface, a basic etching mask corresponding to a target shape and having at least a first structure with a projecting corner and a second structure adjoining the first structure with an opening intervening therebetween, and a correction etching mask extending from the projecting corner of an etching mask of the first structure and connected to an etching mask of the second structure, and a second step of performing anisotropic etching of the monocrystal silicon substrate having the basic etching mask and the correction etching mask to form the target shape. | 05-21-2009 |
| 20100203738 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which includes a gate electrode formed in the shape substantially vertical to a semiconductor substrate is disclosed. A gate electrode is formed by anisotropically etching a gate electrode film having a metal-containing film formed on the semiconductor substrate via a gate insulating film to expose a portion of the gate insulating film. A modified film is formed on a side wall of the metal-containing film by modifying the side wall of the metal-containing film. The exposed portion of the gate insulating film is removed and a portion of the gate insulating film sandwiched between the semiconductor substrate and the metal-containing film is recessed so as to recede from the modified side wall of the metal-containing film by isotropically etching. A side portion of the metal-containing film protruding from the receded gate insulating film is removed by isotropically etching. | 08-12-2010 |
| 20140273495 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate. | 09-18-2014 |
| Entries |
| Document | Title | Date |
|---|
| 20090023293 | IMPLEMENTING STATE-OF-THE-ART GATE TRANSISTOR, SIDEWALL PROFILE/ANGLE CONTROL BY TUNING GATE ETCH PROCESS RECIPE PARAMETERS - In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle. | 01-22-2009 |
| 20090137127 | PLASMA ETCHING METHOD AND STORAGE MEDIUM - A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas. | 05-28-2009 |
| 20100203735 | SOLUTION FOR REMOVING RESIDUE AFTER SEMICONDUCTOR DRY PROCESS AND METHOD OF REMOVING THE RESIDUE USING THE SAME - A residue-removing solution for removing residues present on semiconductor substrates after dry etching and/or ashing, the residue-removing solution comprising a Cu surface protective agent including: at least one compound selected from compounds (1), (2) and (3) each having as a basic skeleton a five-membered or six-membered heteratomic structure as defined herein; a compound capable of forming a complex or chelate with Cu (copper); and water. Further, the residue-removing solution has a pH of 4 to 9. | 08-12-2010 |
| 20120058644 | RESIST STRIPPING COMPOSITIONS AND METHODS FOR MANUFACTURING ELECTRICAL DEVICES - A liquid composition free from N-alkylpyrrolidones and hydroxyl amine and its derivatives, having a dynamic shear viscosity at 50° C. of from 1 to 10 mPas as measured by rotational viscometry and comprising based on the complete weight of the composition, (A) of from 40 to 99.95% by weight of a polar organic solvent exhibiting in the presence of dissolved tetramethylammonium hydroxide (B) a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) of from 0.05 to <0.5% of a quaternary ammonium hydroxide, and (C) <5% by weight of water; method for its preparation, a method for manufacturing electrical devices and its use for removing negative-tone and positive-tone photoresists and post etch residues in the manufacture of 3D Stacked Integrated Circuits and 3D Wafer Level Packagings by way of patterning Through Silicon Vias and/or by plating and bumping. | 03-08-2012 |
| 20120244716 | SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM - There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer | 09-27-2012 |
| 20130059445 | GAS CLUSTER ION BEAM ETCHING PROCESS FOR Si-CONTAINING and Ge-CONTAINING MATERIALS - A method and system for performing gas cluster ion beam (GCIB) etch processing of Si-containing material and/or Ge-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element. | 03-07-2013 |
| 20130252433 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential. | 09-26-2013 |
| 20150079796 | Charged-Particle-Beam Processing Using a Cluster Source - A cluster source is used to assist charged particle beam processing. For example, a protective layer is applied using a cluster source and a precursor gas. The large mass of the cluster and the low energy per atom or molecule in the cluster restricts damage to within a few nanometers of the surface. Fullerenes or clusters of fullerenes, bismuth, gold or Xe can be used with a precursor gas to deposit material onto a surface, or can be used with an etchant gas to etch the surface. Clusters can also be used to deposit material directly onto the surface to form a protective layer for charged particle beam processing or to provide energy to activate an etchant gas. | 03-19-2015 |
