| Entries |
| Document | Title | Date |
|---|
| 20080200035 | METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact hole having a pitch with exposure equipment resolution or less can be formed. | 08-21-2008 |
| 20080220612 | PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION - A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process. | 09-11-2008 |
| 20080220613 | PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION - A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process. | 09-11-2008 |
| 20080227300 | Method for manufacturing semiconductor device - A method of manufacturing a semiconductor device prevents a pattern bridge phenomenon generated by a proximity effect between patterns and a thickness lowering phenomenon of the pattern. As a result, a length of the major axis required in characteristics of the device is secured to improve an electric characteristic and an overlapping margin. A photoresist pattern is formed to have a line/space type, thereby securing a DOF margin in comparison with a photoresist pattern of an island type. | 09-18-2008 |
| 20080242097 | Selective deposition method - The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants. | 10-02-2008 |
| 20080242098 | Method for forming pattern in semiconductor device - A method for forming a pattern in a semiconductor device includes forming an etch target layer over a substrate, forming a hard mask pattern over the etch target layer, and etching the etch target layer using the hard mask pattern as an etch mask and a gas mixture including a fluorine (F)-based gas and a bromine (Br)-based gas as an etch gas to form a target pattern. | 10-02-2008 |
| 20080248651 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A first oxide film and a second oxide film 16 are formed in a first region | 10-09-2008 |
| 20080254633 | MULTIPLE EXPOSURE LITHOGRAPHY METHOD INCORPORATING INTERMEDIATE LAYER PATTERNING - A method of patterning a semiconductor substrate includes creating a first set of patterned features in a first inorganic layer; creating a second set of patterned features in one of the first inorganic layer and a second inorganic layer; and transferring, into an organic underlayer, both the first and second sets of patterned features, wherein the first and second sets of patterned features are combined into a composite set of patterned features that are transferable into the substrate by using the organic underlayer as a mask. | 10-16-2008 |
| 20080254634 | Photoresist composition and method of manufacturing a thin-film transistor substrate using the same - In one example, a photoresist composition includes about 1 to about 70 parts by weight of a first binder resin including a repeat unit represented by the following Chemical Formula 1, about 1 to about 70 parts by weight of a second binder resin including a repeat unit represented by the following Chemical Formula 2, about 0.5 to about 10 parts by weight of a photo-acid generator, about 1 to about 20 parts by weight of a cross-linker and about 10 to about 200 parts by weight of a solvent. The photoresist composition may improve the heat resistance and adhesion ability of a photoresist pattern. | 10-16-2008 |
| 20080280449 | SELF-ALIGNED DIELECTRIC CAP - A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate. | 11-13-2008 |
| 20080293249 | In-situ photoresist strip during plasma etching of active hard mask - A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber. | 11-27-2008 |
| 20080299775 | GAPFILL EXTENSION OF HDP-CVD INTEGRATED PROCESS MODULATION SIO2 PROCESS - Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas. A first portion of the silicon oxide film is deposited using the high-density plasma at a deposition rate between 900 and 6000 Å/min and with a deposition/sputter ratio greater than 30. The deposition/sputter ratio is defined as a ratio of a net deposition rate and a blanket sputtering rate to the blanket sputtering rate. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched. A second portion of the silicon oxide film is deposited over the etched portion of the silicon oxide film. | 12-04-2008 |
| 20080299776 | FREQUENCY DOUBLING USING SPACER MASK - A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask. | 12-04-2008 |
| 20080305641 | REVERSE MASKING PROFILE IMPROVEMENTS IN HIGH ASPECT RATIO ETCH - A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array. | 12-11-2008 |
| 20080305642 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer. | 12-11-2008 |
| 20080318430 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING POROUS LOW DIELECTRIC CONSTANT LAYER FORMED FOR INSULATION BETWEEN METAL LINES - The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers. | 12-25-2008 |
| 20090011603 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO | 01-08-2009 |
| 20090017631 | SELF-ALIGNED PILLAR PATTERNING USING MULTIPLE SPACER MASKS - A method for fabricating a semiconductor mask is described. The image of a series of lines from a first spacer mask is first provided to a mask layer to form a patterned mask layer. The image of a series of lines from a second spacer mask is then provided to the patterned mask layer to form a pillar mask comprised of a series of pillars. The image of the series of lines from the second spacer mask is non-parallel with the series of lines from the first spacer mask. | 01-15-2009 |
| 20090023292 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refractive index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refractive index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements. | 01-22-2009 |
| 20090029554 | Method of Batch Integration of Low Dielectric Substrates with MMICs - A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling. | 01-29-2009 |
| 20090029555 | Multi-Step selective etching for cross-point memory - Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum. | 01-29-2009 |
| 20090029556 | METHOD FOR FORMING A SHALLOW TRENCH ISOLATION - A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of the first liner layer to expose the substrate, performing a second wet etching to remove part of the second liner layer so that the second liner layer is lower than surface of the substrate, performing a third wet etching to remove part of the first oxide and part of the first liner layer, and filling the trench with a second oxide to form a shallow trench isolation. | 01-29-2009 |
| 20090035944 | METHODS OF FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE - Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension. | 02-05-2009 |
| 20090047790 | Selective Wet Etching of Hafnium Aluminum Oxide Films - Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO | 02-19-2009 |
| 20090053899 | METHOD OF PATTERN FORMATION IN SEMICONDUCTOR FABRICATION - Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element. | 02-26-2009 |
| 20090061636 | Etching method for nitride semiconductor - The invention discloses etching method for the nitride semiconductor. Firstly dielectric layer is formed on gallium nitride. The line pattern or dot pattern is formed on the dielectric layer by using the exposure, development, and etching processes. The dielectric layer is used as the mask for the epitaxial lateral overgrowth of follow-up gallium nitride layer. The thick gallium nitride film is grown on the dielectric layer. Then the wet etching process is used to remove the dielectric layer, and the thick gallium nitride film on the dielectric layer is etched to form the specific shape as required. | 03-05-2009 |
| 20090061637 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: forming a first material film, a second material film, each having a function of preventing metal diffusion, and a third material film of which the etching rate for a first etchant is sufficiently lower than that of the first material film and the etching rate for a second etchant is sufficiently lower than that of the second material film, in this order on the outer peripheral surface of the semiconductor substrate; forming a trench structure; forming a buried insulating film and flattening it; removing the second material film through a wet etching process using the second etchant until the first material film formed on the main surface side is exposed; and removing the first material film on the main surface side through a wet etching process using the first etchant until the semiconductor substrate is exposed on the main surface side. | 03-05-2009 |
| 20090087993 | METHODS AND APPARATUS FOR COST-EFFECTIVELY INCREASING FEATURE DENSITY USING A MASK SHRINKING PROCESS WITH DOUBLE PATTERNING - Methods and apparatus are provided for forming an array of devices. The invention includes forming a stack of material layers, forming a first hardmask over the plurality of material layers, exposing the first hardmask to ozone mixed with a halogenated additive, forming a protective layer over the first hardmask, forming a second mask on the protective layer shifted relative to the first mask, exposing the second hardmask to ozone mixed with the halogenated additive, and etching the plurality of material layers to remove material not covered by the hardmasks. Numerous other aspects are disclosed. | 04-02-2009 |
| 20090098735 | METHOD OF FORMING ISOLATION LAYER IN SEMICONDCUTOR DEVICE - A method of forming an isolation layer in a semiconductor device which prevents formation of voids in the isolation layer by sequentially forming an insulating layer and an anti-reflective layer on and/or over a semiconductor substrate, and then forming a photoresist pattern on and/or over the anti-reflective layer, and then forming an insulating layer pattern on and/or over and corresponding to an isolation area of the substrate by performing an etch process using the photoresist pattern as an etch mask, and then forming a polysilicon layer around the insulating layer pattern such that the insulating layer patterns protrudes from the uppermost surface of the polysilicon layer. | 04-16-2009 |
| 20090104780 | METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE - A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used. This results in improved manufacturing efficiency and reduced manufacturing costs of a SONOS semiconductor device. | 04-23-2009 |
| 20090111272 | METHOD OF FORMING STRAIN-CAUSING LAYER FOR MOS TRANSISTORS AND PROCESS FOR FABRICATING STRAINED MOS TRANSISTORS - A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures. | 04-30-2009 |
| 20090111273 | Method for Manufacturing Semiconductor Device - The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved. | 04-30-2009 |
| 20090124086 | METHOD OF FABRICATING A FLASH MEMORY DEVICE - A method of fabricating a flash memory device, in which a pre-metal dielectric layer, a hard mask layer, and a first etch mask pattern are sequentially formed over a semiconductor substrate; an auxiliary layer is formed along a surface of the first etch mask pattern and the hard mask layer; and an etch mask layer is formed on the auxiliary layer to gap-fill between adjacent first etch mask pattern elements. The etch mask layer is etched to form a second etch mask pattern between adjacent first etch mask pattern elements. The auxiliary layer between the first and second etch mask patterns is removed; and a hard mask pattern is formed by etching the hard mask layer between the first etch mask pattern and the second etch mask pattern. The pre-metal dielectric layer is etched process using the hard mask pattern as a mask to form contact holes. | 05-14-2009 |
| 20090130854 | PATTERNING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICES - Methods for forming a pattern layer over a target layer are disclosed. The methods use a novel low temperature spacer structure which results in a pattern layer having a decreased pattern pitch versus conventional patterning using photolithography. The decreased pattern pitch allows the target layer to be divided into multiple regions separated by a small distance, which in turn allows for greater density and device miniaturization. The structure and methods may be applied to patterning a word line layer in a memory device. | 05-21-2009 |
| 20090137126 | METHOD OF FORMING A SPACER - A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask. | 05-28-2009 |
| 20090142926 | Line edge roughness reduction and double patterning - Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures. | 06-04-2009 |
| 20090142927 | Fabricating sub-lithographic contacts - A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements. | 06-04-2009 |
| 20090142928 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device simplifies a process for forming an oxide film of a high-voltage device, thereby reducing the manufacturing costs and manufacturing time of the high-voltage device. The manufacturing method includes applying a gate oxide material over a semiconductor wafer, applying a photoresist material over the gate oxide material, performing an exposure process and a primary development process on the photoresist material to form a photoresist pattern, performing an etching process using the photoresist pattern to form a gate oxide film, and performing a secondary development process to remove the photoresist pattern. | 06-04-2009 |
| 20090149026 | METHOD FOR FORMING HIGH DENSITY PATTERNS - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 06-11-2009 |
| 20090149027 | Method of Fabricating an Integrated Circuit - Embodiments of the invention relate to a method of fabricating an integrated circuit, including etching of a layer that includes a high k material in the form of a metal oxide composition, wherein an etchant is used that includes a silicon halogen composition. | 06-11-2009 |
| 20090163028 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an organic bottom anti-reflective coating over an etch target layer, forming a photoresist pattern over the organic bottom anti-reflective coating, and etching the organic bottom anti-reflective coating using a sulfur-containing gas. | 06-25-2009 |
| 20090163029 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride layer, forming a opening in the photoresist layer, etching the second nitride layer using the photoresist layer as a mask such that the opening is reached to the first oxide layer, etching the first oxide layer using the second nitride layer as a mask such that the opening is reached to the first nitride layer, etching the first oxide layer such that bottom zone of the opening is increased in diameter, and etching the first nitride layer using the first oxide layer as a mask such that the opening is reached to the substrate thereby to form contact hole reaching to the substrate. | 06-25-2009 |
| 20090163030 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed. | 06-25-2009 |
| 20090170330 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. Second etch mask patterns are formed between the auxiliary films formed on sidewalls of the first etch mask patterns. The first etch mask patterns and the second etch mask patterns are formed using the same material. The auxiliary films between the first and second etch mask patterns are removed. Accordingly, more micro patterns can be formed than allowed by the resolution limit of an exposure apparatus while preventing misalignment. | 07-02-2009 |
| 20090181543 | METHOD OF FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming patterns of a semiconductor device, a to-be-etched layer is formed on a semiconductor substrate. First etch mask patterns are formed over the to-be-etched layer. An auxiliary layer is formed on the first etch mask patterns and the to-be-etched layer. The auxiliary layer is thicker on upper sidewalls of the first etch mask patterns than on lower sidewalls thereof. Second etch mask patterns are formed in concave portions of the auxiliary layer. The auxiliary layer between the first and second etch mask patterns is removed. The to-be-etched layer is patterned using the first and second etch mask patterns as an etch mask. | 07-16-2009 |
| 20090191712 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part. | 07-30-2009 |
| 20090191713 | METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER - Provided is a method of forming a fine pattern using a block copolymer. The method comprises forming a coating layer including a block copolymer having a plurality of repeating units on a substrate. A mold is provided having a first pattern comprising a plurality of ridges and valleys. The first pattern is transferred from the mold into the coating layer. Then, a self-assembly structure is formed comprising a plurality of polymer blocks aligned in a direction guided by the ridges and valleys of the mold thereby rearranging the repeating units of the block copolymer within the coating layer by phase separation while the coating layer is located within the valleys of the mold. A portion of the polymer blocks are removed from among the plurality of polymer blocks and a self-assembly fine pattern of remaining polymer blocks is formed. | 07-30-2009 |
| 20090197417 | METHOD FOR FORMING SPACERS OF DIFFERENT SIZES - A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall. | 08-06-2009 |
| 20090215272 | DOUBLE MASK SELF-ALIGNED DOUBLE PATTERNING TECHNOLOGY (SADPT) PROCESS - A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer. | 08-27-2009 |
| 20090246960 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned. | 10-01-2009 |
| 20090253267 | REVERSE MASKING PROFILE IMPROVEMENTS IN HIGH ASPECT RATIO ETCH - A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array. | 10-08-2009 |
| 20090258499 | METHOD OF FORMING AT LEAST AN OPENING USING A TRI-LAYER STRUCTURE - A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate. | 10-15-2009 |
| 20090258500 | METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR - A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes. | 10-15-2009 |
| 20090258501 | Double patterning method - A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, and etching the underlying layer using both the first and the second photoresist patterns as a mask. | 10-15-2009 |
| 20090263973 | FIN MASK AND METHOD FOR FABRICATING SADDLE TYPE FIN USING THE SAME - A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis. | 10-22-2009 |
| 20090269932 | Method for fabricating self-aligned complimentary pillar structures and wiring - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask. | 10-29-2009 |
| 20090275203 | METHOD FOR PROCESSING A THIN FILM MICRO DEVICE ON A SUBSTRATE - A method for processing a thin film micro device on a substrate includes: 1) depositing a carbon film on the substrate as a sacrificial layer; 2) photolithographically defining a first predetermined pattern in the carbon film; 3) etching an unwanted portion of the carbon film outside the first predetermined pattern; 4) depositing a structural film including a single or multiple layers of solid state materials; 5) photolithographically defining a second predetermined pattern in the structural film; 6) etching the discarded portion of the structural film outside the second predetermined pattern; 7) selectively removing the remaining portion of the sacrificial carbon film by using a selective etch process gas in a reactor chamber, so that the overlapped portion of the remaining structural element with the first predetermined pattern is suspended above an underneath cavity above the substrate. | 11-05-2009 |
| 20090286402 | METHOD FOR CRITICAL DIMENSION SHRINK USING CONFORMAL PECVD FILMS - A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant. | 11-19-2009 |
| 20090286403 | METHOD OF FORMING THIN FILM PATTERN FOR SEMICONDUCTOR DEVICE AND APPARATUS FOR THE SAME - A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern. | 11-19-2009 |
| 20090286404 | Method of forming minute patterns in semiconductor device using double patterning - A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns. | 11-19-2009 |
| 20090291560 | FORMING METHOD OF ETCHING MASK, CONTROL PROGRAM AND PROGRAM STORAGE MEDIUM - A feedforward control is performed so that a line width of a mask constituted by an Si | 11-26-2009 |
| 20090291561 | METHOD OF FORMING PATTERN - Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern. | 11-26-2009 |
| 20090298293 | Etching with Improved Control of Critical Feature Dimensions at the Bottom of Thick Layers - The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material. | 12-03-2009 |
| 20090317976 | ETCHING SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An etching system includes: a vacuum chamber; a stage for mounting a workpiece, the stage being disposed within the vacuum chamber; a first electrode located within the vacuum chamber and above the stage; a second located between the first electrode and a ceiling of the vacuum chamber; a gas supply for introducing a process gas into the vacuum chamber; a variable capacitance element connected to the second electrode; and a radio frequency power supply connected to the first electrode and connected through the variable capacitance element to the second electrode. The radio frequency power supply supplies radio frequency power to the first and second electrodes to produce an inductively coupled plasma in the process gas within the vacuum chamber. | 12-24-2009 |
| 20090317977 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: forming a first deposition film on a surface of a member in a chamber configured to perform plasma etching of a wafer, by introducing a first seasoning gas into the chamber; forming a second deposition film on the first deposition film to coat the first deposition film by introducing a second seasoning gas into the chamber; loading the wafer into the chamber; and performing plasma etching of the wafer. | 12-24-2009 |
| 20090317978 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing semiconductor device may include forming a second core on a member to be processed, and a first core on the second core, the second core located below the first core and having a width larger than that of the first core, forming a coating film on a top surface and side surfaces of the first core, and a top surface and side surfaces of the second core, processing the coating film into sidewall masks by partially removing the coating film in a manner that portions of the coating film, which are located on the side surfaces of the first and second cores, are left remaining, etching the first and second cores by using the sidewall masks as a mask so as to remove the first core and portions of the second core which are not covered with the sidewall masks from above, so that an etching mask including the sidewall masks and portions of the second core which remain directly below the sidewall masks is formed, and etching the member by using the etching mask as a mask, so that the member is patterned. | 12-24-2009 |
| 20100015808 | Impact sensor and method for manufacturing the impact sensor - An impact sensor comprises a silicon substrate; an insulating layer formed over the silicon substrate; a plurality of beams having flexibility that are formed of conductive silicon material; a fixing portion to fix a fixed end of each of the beams, the fixing portion being formed of conductive silicon material; a fixed end line at whose one end is formed the fixing portion, the fixed end line being formed of conductive silicon material on the insulating layer; and a free end line having a pressing portion that faces a free end of each of the beams via a space, the free end line being formed of conductive silicon material on the insulating layer. Respective beam widths, each measured in a direction orthogonal to a length direction joining the fixed end and the free end, of the plurality of beams are set different from each other, thus reducing the space occupied by the sensor. | 01-21-2010 |
| 20100022089 | Method for manufacturing semiconductor device using quadruple-layer laminate - There is provided a laminate used as an underlayer layer for a photoresist in a lithography process of a semiconductor device and a method for manufacturing a semiconductor device by using the laminate. The method comprising: laminating each layer of an organic underlayer film (layer A), a silicon-containing hard mask (layer B), an organic antireflective film (layer C) and a photoresist film (layer D) in this order on a semiconductor substrate. The method also comprises: forming a resist pattern in the photoresist film (layer D); etching the organic antireflective film (layer C) with the resist pattern; etching the silicon-containing hard mask (layer B) with the patterned organic antireflective film (layer C); etching the organic underlayer film (layer A) with the patterned silicon-containing hard mask (layer B); and processing the semiconductor substrate with the patterned organic underlayer film (layer A). | 01-28-2010 |
| 20100022090 | RESIST UNDERLAYER FILM FORMING COMPOSITION FOR LITHOGRAPHY, CONTAINING AROMATIC FUSED RING-CONTAINING RESIN - There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern. | 01-28-2010 |
| 20100041235 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICES - A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x−890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5≦x≦22.1). | 02-18-2010 |
| 20100048025 | NANOSTRUCTURES AND NANOSTRUCTURE FABRICATION - Nanostructure and techniques for fabricating nanostructures are provided. In one embodiment, nanostructures may be formed by providing a Silicon-on-Insulator (SOI) substrate, forming a pattern on the SOI substrate, disposing a conformal layer over the pattern, etching the conformal layer, except for a sidewall portion, removing the pattern, transferring the sidewall pattern to the silicon layer of the SOI substrate to form the nanostructure, and releasing the nanostructure. | 02-25-2010 |
| 20100062605 | METHOD OF FORMING A CONTACT HOLE FOR A SEMICONDUCTOR DEVICE - Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable of being chemically bonded to the reaction pattern. A coating layer is then formed on substantially all of the structure that includes the self-assembled monolayer. Afterwards, the contact holes are formed on the semiconductor substrate by performing an etching process. | 03-11-2010 |
| 20100068885 | SIDEWALL FORMING PROCESSES - An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask. | 03-18-2010 |
| 20100068886 | METHOD OF FABRICATING A DIFFERENTIAL DOPED SOLAR CELL - A method of fabricating a differential doped solar cell is described. The method includes the following steps. First, a substrate is provided. A doping process is conducted thereon to form a doped layer. A heavy doping portion of the doped layer is partially or fully removed. Subsequently, an anti-reflection coating layer is formed thereon. A metal conducting paste is printed on the anti-reflection coating layer and is fired to form the metal electrodes for the solar cell. | 03-18-2010 |
| 20100075503 | INTEGRAL PATTERNING OF LARGE FEATURES ALONG WITH ARRAY USING SPACER MASK PATTERNING PROCESS FLOW - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit. | 03-25-2010 |
| 20100081283 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: sequentially forming a first film and a second film on a base film; processing the second film, thereby forming a second pattern; processing the first film with the second pattern as a mask, thereby forming a first pattern; removing the second pattern; depositing a third film on the base film and on the first pattern; processing the third film, thereby forming a third side wall pattern on a side wall of the first pattern; removing the first pattern; and processing the base film with the third side wall pattern as a mask, thereby forming a target pattern so that, in the target pattern, a space dimension is larger than a pattern dimension. | 04-01-2010 |
| 20100099262 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY CELL USING SELF-ALIGNED METAL SILICIDE - In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided. | 04-22-2010 |
| 20100099263 | NF3/H2 REMOTE PLASMA PROCESS WITH HIGH ETCH SELECTIVITY OF PSG/BPSG OVER THERMAL OXIDE AND LOW DENSITY SURFACE DEFECTS - A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface. | 04-22-2010 |
| 20100130015 | PATTERNING METHOD - Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask. | 05-27-2010 |
| 20100130016 | METHODS OF FORMING A MASKING PATTERN FOR INTEGRATED CIRCUITS - In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes. | 05-27-2010 |
| 20100136791 | Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer. | 06-03-2010 |
| 20100136792 | SELF-ALIGNED MULTI-PATTERNING FOR ADVANCED CRITICAL DIMENSION CONTACTS - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density. | 06-03-2010 |
| 20100151685 | METHODS OF REMOVING MULTI-LAYERED STRUCTURE AND OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of removing a multi-layered structure includes the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a multi-layered structure including a first film over the semiconductor substrate, a second film on the first film, and a mask pattern film on the second film. Then, the mask pattern film is removed. Then, the second film is removed by etching the second film with a first etching selectivity of the second film to the first film. The first etching selectivity is greater than a second etching selectivity of the second film to the first film with which the second film is patterned by etching using the mask pattern film. Then, the third film is removed. | 06-17-2010 |
| 20100173497 | Method of fabricating semiconductor integrated circuit device - A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern. | 07-08-2010 |
| 20100178772 | METHOD OF FABRICATING HIGH-K METAL GATE DEVICES - The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts. | 07-15-2010 |
| 20100178773 | METHOD OF FORMING SEMICONDUCTOR DEVICES EMPLOYING DOUBLE PATTERNING - A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between the spacer patterns. The exposed portions of the first material film are removed to form first material film patterns. Third material film patterns are formed in trenches defined by the first material film patterns. Adjacent first portions of the second material film patterns proximate ends of the second material film patterns are separated by a distance less than twice a width of the individual spacer patterns. In some embodiments, the distance separating the adjacent first portions of the second material film patterns is greater than a minimum feature size, and a width of the individual spacer patterns is approximately equal to the minimum feature size. | 07-15-2010 |
| 20100190347 | REMOVAL CHEMISTRY FOR SELECTIVELY ETCHING METAL HARD MASK - Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H | 07-29-2010 |
| 20100190348 | Manufacturing method of semiconductor substrate and substrate processing apparatus - A first processing gas containing a first element and a second processing gas containing a second element are alternately supplied to a surface of a substrate placed in a processing chamber, to thereby form a first thin film, and a second processing gas and a third processing containing the first element and different from the first processing gas are alternately supplied, to thereby form a second thin film on the first thin film, having the same element component as that of the first thin film. | 07-29-2010 |
| 20100261353 | WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS - A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present. | 10-14-2010 |
| 20100279508 | METHOD FOR REDUCING AMINE BASED CONTAMINANTS - Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing. | 11-04-2010 |
| 20100285668 | TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. | 11-11-2010 |
| 20100297848 | ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE - The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF | 11-25-2010 |
| 20100311244 | DOUBLE-EXPOSURE METHOD - The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology. | 12-09-2010 |
| 20100330810 | METHOD FOR REMOVING THRESHOLD VOLTAGE ADJUSTING LAYER WITH EXTERNAL ACID DIFFUSION PROCESS - The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid. | 12-30-2010 |
| 20110008968 | METHOD AND MATERIAL FOR FORMING A DOUBLE EXPOSURE LITHOGRAPHY PATTERN - A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers. | 01-13-2011 |
| 20110008969 | FREQUENCY DOUBLING USING SPACER MASK - A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask. | 01-13-2011 |
| 20110059613 | MASK PATTERN FOR SEMICONDUCTOR DEVICE FABRICATION, METHOD OF FORMING THE SAME, AND METHOD OF FABRICATING FINELY PATTERNED SEMICONDUCTOR DEVICE - Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern. | 03-10-2011 |
| 20110065278 | METHOD FOR FABRICATING PELLICLE OF EUV MASK - A method for fabricating a pellicle of an EUV mask is provided. An insulation layer is formed over a silicon substrate, and a mesh is formed over the insulation layer. A frame exposing a rear surface of the insulation layer is formed by selectively removing a center portion of a rear surface of the silicon substrate. A membrane layer is deposited over the mesh and an exposed top surface of the insulation layer which is adjacent to the mesh. A rear surface of the membrane layer is exposed by selectively removing the portion of the insulation layer which is exposed by the frame. | 03-17-2011 |
| 20110076850 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one embodiment, a method of fabricating a semiconductor device is disclosed. The method can selectively form a core material made of carbon-containing material above a workpiece member. Additionally, the method can form a protective film made of material containing no oxygen so as to cover an upper surface and side faces of the core material. Furthermore, the method can form an oxide film so as to cover the core material and the workpiece member via the protective film. Moreover, the method can shape at least the oxide film into a sidewall in a position lateral to the core material. In addition, the method can etch the workpiece member by using the sidewall as a mask after removal of at least the core material, thereby transferring a pattern of the sidewall to the workpiece member. | 03-31-2011 |
| 20110076851 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 03-31-2011 |
| 20110086512 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A resist pattern ( | 04-14-2011 |
| 20110104901 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes a process of forming a first organic film pattern on a to-be-etched layer on a substrate, a process of forming a silicon oxide film coating the first organic film pattern in an isotropic manner, a process of etching the silicon oxide film to form a first mask pattern in such a manner to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect to a thickness of the silicon oxide film that coats a surface of the line part in the isotropic manner, a process of forming a second organic film pattern coating the silicon oxide film, a process of forming a second mask pattern that includes the silicon oxide film on a side face part in an area that is coated by the second organic film pattern, and a process of, in an area other than the area that is coated by the second organic film pattern, forming a third mask pattern in which an even number of the silicon oxide films are arranged. | 05-05-2011 |
| 20110111599 | METHOD FOR PATTERNED ETCHING OF SELECTED MATERIAL - Surface processing in which the area to be processed is restricted to a predetermined pattern, can be achieved by: (a) providing a layer of a first reagent over a region of the surface to be processed which at least covers an area of the predetermined pattern; (b) providing one or more further reagents which are further reagents required for the processing of the surface; and (c) applying at least one of the further reagents over the region to be processed according to the predetermined pattern; such that the first reagent acts with the one or more of the further reagents to process the surface only in the area of the predetermined pattern. The process is particularly applicable to etching where an etchant having two or more components is used. In that case at least a first etchant component is applied over the surface and at least one further etchant component is applied in the predetermined pattern. | 05-12-2011 |
| 20110117745 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment includes processing a second film | 05-19-2011 |
| 20110117746 | COATING COMPOSITION AND PATTERN FORMING METHOD - It is an object to provide a coating composition applicable to “reversal patterning” and suitable for forming a film covering a resist pattern. The object is accomplished by a coating composition for lithography comprising an organopolysiloxane, a solvent containing the prescribed organic solvent as a main component, and a quaternary ammonium salt or a quaternary phosphonium salt; or a coating composition for lithography comprising a polysilane, a solvent containing the prescribed organic solvent as a main component, and at least one additive selected from a group consisting of a crosslinking agent, a quaternary ammonium salt, a quaternary phosphonium salt, and a sulfonic acid compound, wherein the polysilane has, at a terminal thereof, a silanol group or a silanol group together with a hydrogen atom. | 05-19-2011 |
| 20110124197 | METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES - A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. | 05-26-2011 |
| 20110130006 | MASK MATERIAL CONVERSION - The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation. | 06-02-2011 |
| 20110143544 | METHOD OF FORMING MICROPATTERN, DIE FORMED BY THIS METHOD OF FORMING MICROPATTERN, TRANSFER METHOD AND MICROPATTERN FORMING METHOD USING THIS DIE - A micropattern is joined to a substrate (W | 06-16-2011 |
| 20110151672 | Method of Etching Oxide Layer and Nitride Layer - An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device. | 06-23-2011 |
| 20110159693 | METHOD FOR FABRICATING HOLE PATTERN - A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns. | 06-30-2011 |
| 20110159694 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: providing a substrate, forming an insulation layer, an adhesive layer, and a photoresist pattern, etching the adhesive layer using the photoresist pattern as an etch barrier, and wet etching the insulation layer using the etched adhesive layer and the photoresist pattern as etch barriers. | 06-30-2011 |
| 20110159695 | METHOD FOR MANUFACTURING MASK - Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity. | 06-30-2011 |
| 20110159696 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices comprises forming an etch target layer and auxiliary patterns over a semiconductor substrate, forming spacers on sidewalls of the auxiliary patterns, removing the auxiliary patterns, performing an etch process to change both corners of upper portions of the spacers to be symmetrical to one another, and patterning the etch target layer by using the spacers. | 06-30-2011 |
| 20110159697 | ETCHING METHOD AND ETCHING APPARATUS - There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF | 06-30-2011 |
| 20110189859 | Method of Etching Oxide Layer and Nitride Layer - An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching. | 08-04-2011 |
| 20110201206 | METHOD FOR FORMING AMORPHOUS CARBON NITRIDE FILM, AMORPHOUS CARBON NITRIDE FILM, MULTILAYER RESIST FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND STORAGE MEDIUM IN WHICH CONTROL PROGRAM IS STORED - An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N | 08-18-2011 |
| 20110201207 | BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES - There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel openings on the electrode structures. The bank structure has a height adjacent to the pixel opening, h | 08-18-2011 |
| 20110207330 | Method of manufacturing semiconductor device - A sidewall core that is slimmed is formed in a memory cell array area by patterning a polysilicon layer formed over a silicon nitride layer. A silicon oxide layer that at least covers side surfaces of the sidewall core and the polysilicon layer are sequentially formed and an embedded hard mask is formed by etching back the polysilicon layer. Thereafter, the silicon nitride layer within the memory cell array area that does not overlap with the sidewall core or the embedded hard mask and the silicon nitride layer within a peripheral circuit area that overlaps with a positioning monitor mark are exposed by etching the silicon oxide layer, and then the silicon nitride layer that is to be etched is patterned. | 08-25-2011 |
| 20110207331 | Resist underlayer film forming composition for lithography, containing aromatic fused ring-containing resin - There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern. | 08-25-2011 |
| 20110217846 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To prevent the occurrence of short circuit or abnormality of wiring resistance values, a semiconductor wafer is subjected to nitrogen plasma treatment after one of the following steps is over; a step of providing a resist pattern on an inter-layer insulation film and then dry-etching the inter-layer insulation film, and a step of dry-etching a stressor SiN film after the resist pattern is removed. | 09-08-2011 |
| 20110223769 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device, including, selectively forming a first film as a core member on a film to be processed, forming a second film on a side surface and an upper surface of the core member, and on an upper surface of the film to be processed to cover the film, the second film which is constituted with same material as the first film and is doped with impurities being different in amount from impurities in the first film, removing the second film on the core member and on the film to be processed to form a sidewall mask constituted with the second film on the side surface of the core member, selectively removing the core member, and etching the film to be processed using the sidewall mask film as a mask. | 09-15-2011 |
| 20110237082 | MICRO PATTERN FORMING METHOD - There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film. | 09-29-2011 |
| 20110244690 | COMBINATORIAL PLASMA ENHANCED DEPOSITION AND ETCH TECHNIQUES - According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes. | 10-06-2011 |
| 20110250757 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A coating film is formed on a member to be etched, which includes an amorphous carbon film and a silicon oxynitride film, by a spin coating method; a sidewall core is formed by pattering the coating film; a silicon oxide film is formed to cover at least the side surface of the sidewall core; and an organic anti-reflection film is formed on the silicon oxide film by a spin coating method. Thereafter, an embedded mask is formed to cover concave portions of the silicon oxide film by etching the organic anti-reflection film; exposed is a portion of the member to be etched which does not overlap the sidewall core or the embedded mask by etching the silicon oxide film; and the member to be etched is etched. Thus, it is possible to obtain a pattern with a size less than the photolithography resolution limit. | 10-13-2011 |
| 20110256727 | METHOD OF FORMING SEMICONDUCTOR PATTERNS - Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure. | 10-20-2011 |
| 20110281435 | FAST GAS SWITCHING PLASMA PROCESSING APPARATUS - A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas within a period of less than 1 s. A first frequency tuned RF power source for providing power to the electrode in a first frequency range is electrically connected to the at least one electrode wherein the first frequency tuned RF power source is able to minimize a reflected RF power. A second frequency tuned RF power source for providing power to the plasma chamber in a second frequency range outside of the first frequency range wherein the second frequency tuned RF power source is able to minimize a reflected RF power. | 11-17-2011 |
| 20110294297 | Method of manufacturing semiconductor device - In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer. The hole pattern formed thereby has a high precision, with a density thereof being double or triple that of a pattern formed by a lithography technique. | 12-01-2011 |
| 20110294298 | TEXTURED SINGLE CRYSTAL - A method for fabricating a textured single crystal including depositing pads made of metal on a surface of a single crystal. A protective layer is deposited on the pads and on the single crystal between the pads; and etching the surface with a first compound that etches the metal more rapidly than the protective layer is carried out. Processing continues with etching the surface with a second compound that etches the single crystal more rapidly than the protective layer; and etching the surface with a third compound that etches the protective layer more rapidly than the single crystal. The textured substrate may be used for the epitaxial growth of GaN, AlN or III-N compounds (i.e. a nitride of a metal the positive ion of which carries a +3 positive charge) in the context of the fabrication of LEDs, electronic components or solar cells. | 12-01-2011 |
| 20110300712 | Methods of Forming a Photoresist Pattern Using Plasma Treatment of Photoresist Patterns - Methods of forming a photoresist pattern include forming a first photoresist pattern on a substrate and treating the first photoresist pattern with plasma that modifies etching characteristics of the first photoresist pattern. This modification may include making the first photoresist pattern more susceptible to removal during subsequent processing. The plasma-treated first photoresist pattern is covered with a second photoresist layer, which is patterned into a second photoresist pattern that contacts sidewalls of the plasma-treated first photoresist pattern. The plasma-treated first photoresist pattern is selectively removed from the substrate to reveal the remaining second photoresist pattern. The second photoresist pattern is used as an etching mask during the selective etching of a portion of the substrate (e.g., target layer). The use of the second photoresist pattern as an etching mask may yield narrower linewidths in the etched portion of the substrate than are achievable using the first photoresist pattern alone. | 12-08-2011 |
| 20110300713 | OVERLAY VERNIER KEY AND METHOD FOR FABRICATING THE SAME - Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape. | 12-08-2011 |
| 20110312185 | PATTERN FORMATION METHOD AND PATTERN FORMATION DEVICE - According to one embodiment, a pattern formation method includes: forming a first pattern in a first region on a substrate to be treated; coating a plurality of types of block copolymers which are different in composition ratio on a second region which is different from the first region; and forming in the second region, by a heat treatment, a second pattern including a plurality of types of structures based on the coated plurality of types of block copolymers. | 12-22-2011 |
| 20120009795 | CHEMICALLY AMPLIFIED RESIST MATERIAL AND PATTERN FORMATION METHOD USING THE SAME - A resist film ( | 01-12-2012 |
| 20120015521 | AMORPHOUS CARBON DEPOSITION METHOD FOR IMPROVED STACK DEFECTIVITY - Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer. | 01-19-2012 |
| 20120015522 | SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer | 01-19-2012 |
| 20120021607 | METHOD OF PITCH DIMENSION SHRINKAGE - An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch. | 01-26-2012 |
| 20120021608 | SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer | 01-26-2012 |
| 20120028473 | Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer. | 02-02-2012 |
| 20120045900 | COMPOSITION FOR RESIST UNDERLAYER FILM, PROCESS FOR FORMING RESIST UNDERLAYER FILM, PATTERNING PROCESS, AND FULLERENE DERIVATIVE - The invention provides a composition for a resist underlayer film, the composition for a resist underlayer film to form a resist underlayer film of a multilayer resist film used in lithography, wherein the composition comprises at least (A) a fullerene derivative that is a reaction product of a substance having a fullerene skeleton with a 1,3-diene compound derivative having an electron-withdrawing group and (B) an organic solvent. There can be a composition for a resist underlayer film for a multilayer resist film used in lithography, the composition giving a resist underlayer film having excellent high dry etching resistance, capable of suppressing wiggling during substrate etching with high effectiveness, and capable of avoiding a poisoning problem in upperlayer patterning that uses a chemical amplification resist; a process for forming a resist underlayer film; a patterning process; and a fullerene derivative. | 02-23-2012 |
| 20120045901 | METHOD OF FORMING A PATTERN STRUCTURE FOR A SEMICONDUCTOR DEVICE - In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line. | 02-23-2012 |
| 20120064724 | Methods of Forming a Pattern of Semiconductor Devices - Methods of forming a pattern of a semiconductor device including performing a double patterning process without using an atomic layer deposition (ALD) oxide film are provided. The methods may include forming a mask pattern on a substrate; forming a chemical attach process (CAP) material layer covering at least a portion of the mask pattern; forming a CAP adhesive layer by adhering at least a portion of the CAP material layer to the mask pattern by using a first baking process and a first development process; forming an interlayer covering at least a portion of the mask pattern and the CAP adhesive layer; and removing the mask pattern and the interlayer while allowing the CAP adhesive layer to remain by using a second baking process and a second development process. | 03-15-2012 |
| 20120064725 | NAPHTHALENE DERIVATIVE, RESIST BOTTOM LAYER MATERIAL, AND PATTERNING PROCESS - A naphthalene derivative having formula (1) is provided wherein An and Art denote a benzene or naphthalene ring, and n is such a natural number as to provide a weight average molecular weight of up to 100,000. A material comprising the naphthalene derivative or a polymer comprising the naphthalene derivative is spin coated to form a resist bottom layer having improved properties. A pattern forming process in which a resist bottom layer formed by spin coating is combined with an inorganic hard mask formed by CVD is available. | 03-15-2012 |
| 20120070993 | PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS - A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region. | 03-22-2012 |
| 20120070994 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING SULFIDE BOND - There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hard mask; and a forming method of a resist pattern using the underlayer film forming composition for lithography. A resist underlayer film forming composition for lithography comprising: as a silicon atom-containing compound, a hydrolyzable organosilane containing a sulfur atom-containing group, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein in the whole silicon atom-containing compound, the ratio of a sulfur atom to a silicon atom is less than 5% by mole. The hydrolyzable organosilane is preferably a compound of Formula (1): [R | 03-22-2012 |
| 20120077345 | CARBAZOLE NOVOLAK RESIN - There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula ( | 03-29-2012 |
| 20120083127 | METHOD FOR FORMING A PATTERN AND A SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for forming a fine pattern on a substrate includes providing a substrate including a material with an initial pattern formed thereon and having a first line width, performing a self-limiting oxidation and/or nitridation process on a surface of the material and thereby forming an oxide, a nitride, or an oxynitride film on a surface of the initial pattern, and removing the oxide, nitride, or oxynitride film. The method further includes repeating the formation and removal of the oxide, nitride, or oxynitride film to form a second pattern having a second line width that is smaller than the first line width of the initial pattern. The patterned material can contain silicon, a silicon-containing material, a metal, or a metal-nitride, and the self-limiting oxidation process can include exposure to vapor phase ozone, atomic oxygen generated by non-ionizing electromagnetic (EM) radiation, atomic nitrogen generated by ionizing or non-ionizing EM radiation, or a combination thereof. | 04-05-2012 |
| 20120088369 | Atomic Layer Deposition Of Photoresist Materials And Hard Mask Precursors - Methods for forming photoresists sensitive to radiation on substrate are provided. Atomic layer deposition methods of forming films (e.g., silicon-containing films) photoresists are described. The process can be repeated multiple times to deposit a plurality of silicon photoresist layers. Process of depositing photoresist and forming patterns in photoresist are also disclosed which utilize carbon containing underlayers such as amorphous carbon layers. | 04-12-2012 |
| 20120108070 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first hard mask layer over a semiconductor substrate including a cell region and a peripheral circuit region, forming a spacer pattern over the first hard mask layer of the cell region, forming a cell-open mask pattern over the peripheral circuit region, forming a first hard mask pattern by etching the first hard mask layer using the spacer pattern of the cell region as an etch mask, forming a second hard mask layer over the first hard mask pattern of the cell region and a first hard mask layer of the peripheral circuit region, forming a cutting mask pattern over the second hard mask layer; and forming an active region in the cell region and a device isolation region in the peripheral circuit region by etching the second hard mask layer, the first hard mask pattern of the cell region, the first hard mask layer of the peripheral circuit region, and the semiconductor substrate using the cutting mask pattern as an etch mask. | 05-03-2012 |
| 20120108071 | RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, namely, an underlayer film having optimum n-value and k-value, excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same. | 05-03-2012 |
| 20120129351 | COMPOSITE REMOVABLE HARDMASK - A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels. | 05-24-2012 |
| 20120129352 | SILICON-CONTAINING FILM, RESIN COMPOSITION, AND PATTERN FORMATION METHOD - A pattern-forming method includes forming a silicon-containing film on a substrate, the silicon-containing film having a mass ratio of silicon atoms to carbon atoms of 2 to 12. A shape transfer target layer is formed on the silicon-containing film. A fine pattern is transferred to the shape transfer target layer using a stamper that has a fine pattern to form a resist pattern. The silicon-containing film and the substrate are dry-etched using the resist pattern as a mask to form a pattern on the substrate in nanoimprint lithography. According to another aspect of the invention, a silicon-containing film includes silicon atoms and carbon atoms. A mass ratio of silicon atoms to carbon atoms is 2 to 12. The silicon-containing film is used for a pattern-forming method employed in nanoimprint lithography. | 05-24-2012 |
| 20120129353 | METHOD FOR PATTERN FORMATION, METHOD AND COMPOSITION FOR RESIST UNDERLAYER FILM FORMATION, AND RESIST UNDERLAYER FILM - Provided by the present invention is a method including: (1) forming a resist underlayer film on the upper face side of a substrate to be processed using a composition for forming a resist underlayer film, the composition containing (A) a compound having a group represented by the following formula (1); (2) forming a resist coating film by applying a resist composition on the resist underlayer film; (3) exposing the resist coating film by selectively irradiating the resist coating film with a radiation; (4) forming a resist pattern by developing the exposed resist coating film; and (5) forming a predetermined pattern on the substrate to be processed by sequentially dry etching the resist underlayer film and the substrate using the resist pattern as a mask. | 05-24-2012 |
| 20120142193 | RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or general formula (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same. | 06-07-2012 |
| 20120142194 | METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE - A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions. | 06-07-2012 |
| 20120142195 | COMPOSITION FOR FORMING RESIST UNDERLAYER FILM FOR LITHOGRAPHY INCLUDING RESIN CONTAINING ALICYCLIC RING AND AROMATIC RING - There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): | 06-07-2012 |
| 20120156881 | METHOD FOR DEFINING A SEPARATING STRUCTURE WITHIN A SEMICONDUCTOR DEVICE - A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features. | 06-21-2012 |
| 20120156882 | METHOD FOR FABRICATING LARGE-AREA NANOSCALE PATTERN - A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area. | 06-21-2012 |
| 20120156883 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device includes forming partition patterns on a hard mask layer; forming a first auxiliary layer on the entire structure including a surface of the partition patterns; forming auxiliary patterns to cover a portion of the first auxiliary layer formed over sidewalls of the partition pattern formed in second region, where each of the auxiliary patterns in the second region has a width greater than a thickness of the first auxiliary layer; forming spacers on sidewalls of the partition patterns, so that a portion of the partition patterns and a portion of the hard mask layer are exposed; removing the auxiliary patterns; etching the partition patterns exposed between the spacers; and removing remaining regions of the partition patterns and the hard mask layer exposed between the spacers. | 06-21-2012 |
| 20120156884 | FILM FORMING METHOD OF AMORPHOUS CARBON FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate. | 06-21-2012 |
| 20120164837 | FEATURE SIZE REDUCTION - Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited. | 06-28-2012 |
| 20120171868 | RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed A resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), one or more kinds of a compound represented by the following general formula (2), and one or more kinds of a compound, represented by the following general formula (3), and/or an equivalent body thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same. | 07-05-2012 |
| 20120171869 | ETCHING METHOD - There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order. | 07-05-2012 |
| 20120178261 | SILICON-CONTAINING COMPOSITION HAVING SULFONAMIDE GROUP FOR FORMING RESIST UNDERLAYER FILM - There is provided a lithographic resist underlayer film-forming composition for forming a resist underlayer film which can be used as a hard mask. A lithographic resist underlayer film-forming composition including a silane compound having sulfonamide group, wherein the silane compound having sulfonamide group is a hydrolyzable organosilane having a sulfonamide group in the molecule, a hydrolyzate thereof, or a hydrolytic condensation product thereof. The composition including a silane compound having sulfonamide group and a silane compound lacking a sulfonamide group, wherein the silane compound having sulfonamide group is present within the silane compounds overall in a proportion of less than 1 mol %, for example 0.1 to 0.95 mol %. | 07-12-2012 |
| 20120184103 | RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), and one or more kinds of compounds, represented by the following general formulae (2-1) and/or (2-2), and/or equivalent bodies thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same. | 07-19-2012 |
| 20120184104 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 07-19-2012 |
| 20120184105 | METHOD OF FORMING OPENINGS - A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask. | 07-19-2012 |
| 20120184106 | METHOD AND ALGORITHM FOR RANDOM HALF PITCHED INTERCONNECT LAYOUT WITH CONSTANT SPACING - An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces. | 07-19-2012 |
| 20120184107 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O( | 07-19-2012 |
| 20120190205 | METHODS FOR SELF-ALIGNED SELF-ASSEMBLED PATTERNING ENHANCEMENT - Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature. | 07-26-2012 |
| 20120190206 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first organic film pattern on a to-be-etched layer on a substrate, forming a silicon oxide film coating the first organic film pattern-etching the silicon oxide film to form a first mask pattern to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect forming a second organic film pattern coating the silicon oxide film, forming a second mask pattern including the silicon oxide film on a side face part in an area coated by the second organic film pattern, and forming, in an area other than the area coated by the second organic film pattern, a third mask pattern in which an even number of the silicon oxide films are arranged. | 07-26-2012 |
| 20120196444 | METHOD FOR THE SELECTIVE DELIVERY OF MATERIAL TO A SUBSTRATE - A method of selective delivery of material to locations on a substrate using a continuous stream deposition device to deposit the material at selected locations on the substrate. This is achieved by creating a mask with an opening, locating the mask over the substrate and depositing the material through the opening onto the substrate. When locating the mask, over the substrate, a portion of the substrate is exposed through the opening and when the continuous stream deposition device is moved relative to the substrate and the mask, the continuous stream deposition device follows a path relative to the mask which intersects the opening. While the continuous stream deposition device moves, it discharges a continuous stream comprising the material to be delivered, to deposit the material through the mask at a discrete location on the substrate, at the intersection of the opening and the path of the continuous stream deposition device. Alternatively the mask may be dispensed with and two materials deposited on two intersecting paths whereby at the intersections the two materials react. | 08-02-2012 |
| 20120202350 | METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 08-09-2012 |
| 20120208367 | METHOD FOR FABRICATING CARBON HARD MASK AND METHOD FOR FABRICATING PATTERNS OF SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using C | 08-16-2012 |
| 20120208368 | METHOD AND APPARATUS FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere. | 08-16-2012 |
| 20120220132 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a core layer, an anti-reflection film and a photoresist layer on a layer to be etched of a substrate; trimming first line patterns of the photoresist layer; forming a first film on the first line patterns; removing the first film such that the first film is left in sidewall portions of the first line patterns of the photoresist layer; removing the photoresist layer; producing the core layer into second line patterns by etching the anti-reflection film and the core layer; forming a second film on the core layer produced into the second line patterns; removing the second film such that the second film is left in sidewall portions of the second line patterns of the core layer; and producing the layer to be etched into third line patterns by etching the layer to be etched. | 08-30-2012 |
| 20120220133 | Integrated Circuit Having Interleaved Gridded Features, Mask Set, and Method for Printing - A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer. | 08-30-2012 |
| 20120225560 | MANUFACTURING METHOD OF INTEGRATED CIRCUITS BASED ON FORMATION OF LINES AND TRENCHES - The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask. | 09-06-2012 |
| 20120238099 | METHOD OF MANUFACTURING ELECTRONIC PART - According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed. | 09-20-2012 |
| 20120244711 | SIDEWALL IMAGE TRANSFER PROCESS - An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer. | 09-27-2012 |
| 20120244712 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film. | 09-27-2012 |
| 20120244713 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier. | 09-27-2012 |
| 20120244714 | EXPOSURE MASK AND METHOD FOR MANUFACTURING SAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An exposure mask includes: an insulative substrate; a light reflecting film provided on the substrate; a light absorbing film provided on the light reflecting film and forming a pattern in a center region on the substrate; and an interconnect provided on the substrate, the light reflecting film and the light absorbing film not being provided in a frame-shaped region surrounding the center region, and the interconnect being placed so that a portion of a laminated film composed of the light reflecting film and the light absorbing film located inside the frame-shaped region is electrically connected to a portion of the laminated film located outside the frame-shaped region. | 09-27-2012 |
| 20120252216 | Low-Temperature in-situ Removal of Oxide from a Silicon Surface During CMOS Epitaxial Processing - Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof. | 10-04-2012 |
| 20120252217 | COMPOSITION FOR FORMING RESIST UNDERLAYER FILM AND METHOD FOR FORMING PATTERN - A resist underlayer film-forming composition includes (A) a polymer that includes a repeating unit shown by a formula (1), and has a polystyrene-reduced weight average molecular weight of 3000 to 10,000, and (B) a solvent, | 10-04-2012 |
| 20120252218 | BIPHENYL DERIVATIVE, RESIST BOTTOM LAYER MATERIAL, BOTTOM LAYER FORMING METHOD, AND PATTERNING PROCESS - A biphenyl derivative having formula (1) is provided wherein Ar1 and Ar2 denote a benzene or naphthalene ring, and x and z each are 0 or 1. A material comprising the biphenyl derivative or a polymer comprising recurring units of the biphenyl derivative is spin coated and heat treated to form a resist bottom layer having improved properties, optimum values of n and k, step coverage, etch resistance, heat resistance, solvent resistance, and minimized outgassing. | 10-04-2012 |
| 20120276745 | METHOD FOR FABRICATING HOLE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern. | 11-01-2012 |
| 20120282778 | Methods Of Forming A Pattern On A Substrate - A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated. | 11-08-2012 |
| 20120282779 | SIDEWALL IMAGE TRANSFER PROCESS EMPLOYING A CAP MATERIAL LAYER FOR A METAL NITRIDE LAYER - A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer. | 11-08-2012 |
| 20120295445 | Methods of Fabricating Substrates - A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed. | 11-22-2012 |
| 20120302069 | METHOD OF PATTERNED IMAGE REVERSAL - A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern. | 11-29-2012 |
| 20120309202 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device, includes forming a mask film on a base material. The base material includes a first portion made of a first material and a second portion made of a second material. The mask film includes a third portion located immediately above the first portion and made of a third material and a fourth portion located immediately above the second portion and made of a fourth material. The mask film has an opening formed in both the third portion and the fourth portion. | 12-06-2012 |
| 20120322268 | METHOD OF FORMING A PATTERN - A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern. | 12-20-2012 |
| 20120322269 | Methods of Fabricating Substrates - A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed. | 12-20-2012 |
| 20120329282 | METHOD AND MATERIAL FOR FORMING A DOUBLE EXPOSURE LITHOGRAPHY PATTERN - Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension. | 12-27-2012 |
| 20130017685 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUSAANM Akae; NaonoriAACI Imizu-shiAACO JPAAGP Akae; Naonori Imizu-shi JPAANM Murakami; KotaroAACI Toyama-shiAACO JPAAGP Murakami; Kotaro Toyama-shi JPAANM Hirose; YoshiroAACI Toyama-shiAACO JPAAGP Hirose; Yoshiro Toyama-shi JPAANM Kameda; KenjiAACI Toyama-shiAACO JPAAGP Kameda; Kenji Toyama-shi JP - To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit. | 01-17-2013 |
| 20130023124 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer. | 01-24-2013 |
| 20130034965 | METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES - In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask. | 02-07-2013 |
| 20130045603 | SEMICONDUCTOR PROCESS - A semiconductor process is described as follows. A material layer is provided on a substrate. A low-temperature oxidation treatment is performed to the material layer. A photoresist layer is formed on the material layer after the low-temperature oxidation treatment. The photoresist layer is patterned. | 02-21-2013 |
| 20130052832 | PRODUCING TRANSISTOR INCLUDING SINGLE LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer. | 02-28-2013 |
| 20130065397 | Methods to increase pattern density and release overlay requirement by combining a mask design with special fabrication processes - A novel process technique and mask design based on the optimized self-aligned triple patterning are invented for the semiconductor manufacturing. This invention pertains to methods of forming one and/or two dimensional features on a substrate having the feature density increased to three times of what is possible using optical lithography, and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. | 03-14-2013 |
| 20130072023 | METHOD OF CONTROLLED LATERAL ETCHING - A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure. | 03-21-2013 |
| 20130078814 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING ANION GROUP - There is provided a method of making a semiconductor device utilizing a resist underlayer film forming composition comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): R | 03-28-2013 |
| 20130084704 | METHOD FOR MANUFACTURING MICROSTRUCTURE - According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film. | 04-04-2013 |
| 20130089985 | Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach - When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material. | 04-11-2013 |
| 20130089986 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer. | 04-11-2013 |
| 20130095664 | ATOMIC LAYER DEPOSITION OF ANTIMONY OXIDE FILMS - Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl | 04-18-2013 |
| 20130109186 | METHOD OF FORMING SEMICONDUCTOR DEVICES USING SMT | 05-02-2013 |
| 20130115776 | PRESSURE CONTROL VALVE ASSEMBLY OF PLASMA PROCESSING CHAMBER AND RAPID ALTERNATING PROCESS - A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber. | 05-09-2013 |
| 20130115777 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURES - A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate. | 05-09-2013 |
| 20130115778 | Dry Etch Processes - Provided methods of etching and/or patterning films. Certain methods comprise exposing at least part of a film on a substrate, the film comprising one or more of HfO | 05-09-2013 |
| 20130122710 | CARBAZOLE NOVOLAK RESIN - There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): | 05-16-2013 |
| 20130130503 | METHOD FOR FABRICATING ULTRA-FINE NANOWIRE - Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented. | 05-23-2013 |
| 20130130504 | METHOD OF MANUFACTURING NON-PHOTOSENSITIVE POLYIMIDE PASSIVATION LAYER - A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues. | 05-23-2013 |
| 20130157468 | ETCHING METHOD, SUBSTRATE PROCESSING METHOD, PATTERN FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT - A fluorocarbon layer is formed on a silicon substrate that is a to-be-processed substrate (step A). A resist layer is formed on the thus-formed fluorocarbon layer (step B). Then, the resist layer is patterned into a predetermined shape by exposing the resist layer to light by means of a photoresist layer (step C). The fluorocarbon layer is etched using the resist layer, which has been patterned into a predetermined shape, as a mask (step D). Next, the resist layer served as a mask is removed (step E). After that, the silicon substrate is etched using the remained fluorocarbon layer as a mask (step F). Since the fluorocarbon layer by itself functions as an antireflective film and a harm mask, the reliability of processing can be improved, while reducing the cost. | 06-20-2013 |
| 20130183829 | METHODS FOR INCREASED ARRAY FEATURE DENSITY - A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided. | 07-18-2013 |
| 20130183830 | SILICON-CONTAINING COMPOSITION FOR FORMATION OF RESIST UNDERLAYER FILM, WHICH CONTAINS ORGANIC GROUP CONTAINING PROTECTED ALIPHATIC ALCOHOL - Described herein are compositions for forming an underlayer film for a solvent-developable resist. These compositions can include a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof and a solvent. The composition can form a resist underlayer film including, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof, the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms. Also described is a method for applying the composition onto a semiconductor substrate and baking the composition to form a resist underlayer film. | 07-18-2013 |
| 20130203257 | PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer, forming a plurality of elongated protrusions in a third layer above the first and second layers, and forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. The method also includes forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner. | 08-08-2013 |
| 20130210233 | Methods for Particle Reduction in Semiconductor Processing - Methods for removing particles from a wafer for photolithography. A method is provided including providing a semiconductor wafer; attaching a polyimide layer to a backside of the semiconductor wafer; and performing an etch on an active surface of the semiconductor wafer; wherein particles that impinge on the backside during the etch are captured by the polyimide layer. In another method, includes attaching a layer of polyimide film to a backside of a semiconductor wafer; dry etching a material on an active surface of the semiconductor wafer; depositing of an additional layer of material on the active surface of the semiconductor wafer; removing the layer of polyimide film from the backside of the semiconductor wafer; patterning the layer of material using an immersion photolithography process to expose a photoresist on the active surface of the wafer; and repeating the attaching, dry etching, depositing, removing and patterning steps. | 08-15-2013 |
| 20130210234 | LITHOGRAPHY PROCESSES UTILIZING EXTREME ULTRAVIOLET RAYS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Lithography processes are provided. The lithography process includes installing a reticle masking (REMA) part having a REMA open region in a lithography apparatus, loading a reticle including at least one reticle chip region in which circuit patterns are disposed into the lithography apparatus, and sequentially exposing a first wafer field, which includes a first chip region corresponding to the reticle chip region, and a second wafer field, which includes a second chip region corresponding to the reticle chip region, of a wafer to rays using the reticle and the REMA part to transfer images of the circuit patterns onto the wafer. An edge boundary of the REMA open region transferred on the first wafer field is located on a scribe lane region between the first and second chip regions while the first wafer field is exposed. Methods of manufacturing a semiconductor device using the lithography process are also provided. | 08-15-2013 |
| 20130224957 | SILICON-CONTAINING RESIST UNDERLAYER FILM FORMING COMPOSITION HAVING FLUORINE-BASED ADDITIVE - A resist underlayer film forming composition for lithography includes: as a component (I), a fluorine-containing highly branched polymer obtained by polymerizing a monomer A having two or more radical polymerizable double bonds in the molecule thereof, a monomer B having a fluoroalkyl group and at least one radical polymerizable double bond in the molecule thereof, and a monomer D having a silicon atom-containing organic group and at least one radical polymerizable double bond in the molecule thereof, in the presence of a polymerization initiator C in a content of 5% by mole or more and 200% by mole or less, based on the total mole of the monomer A, the monomer B, and the monomer D; and as a component (II), a hydrolyzable silane compound, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a silicon-containing compound that is a combination of these compounds. | 08-29-2013 |
| 20130230988 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask. | 09-05-2013 |
| 20130244437 | METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE - One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers. | 09-19-2013 |
| 20130244438 | PHOTOLITHOGRAPHIC METHODS - Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices. | 09-19-2013 |
| 20130244439 | REMOVABLE TEMPLATES FOR DIRECTED SELF ASSEMBLY - A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate. | 09-19-2013 |
| 20130260563 | Mask Treatment for Double Patterning Design - A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask. | 10-03-2013 |
| 20130260564 | INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION - Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF. | 10-03-2013 |
| 20130260565 | METHOD TO FORM CONVEX STRUCTURE ON SURFACE OF SEMICONDUCTOR MATERIAL - A process to form a lens on a semiconductor material is disclosed. The process includes steps of: forming double layers of an intermediate layer on the semiconductor material and a mask layer made of hard-baked photoresist on the semiconductor substrate; the first transcribing the convex shape of the mask layer on the intermediate layer; and the second scribing the convex shape of the intermediate layer on the semiconductor material. | 10-03-2013 |
| 20130267095 | METHOD OF FABRICATING AND CORRECTING NANOIMPRINT LITHOGRAPHY TEMPLATES - A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence. | 10-10-2013 |
| 20130288482 | METHODS OF FORMING A PATTERN - In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern. | 10-31-2013 |
| 20130302990 | ORGANIC FILM COMPOSITION, METHOD FOR FORMING ORGANIC FILM AND PATTERNING PROCESS USING THIS, AND HEAT-DECOMPOSABLE POLYMER - The invention provides an organic film composition comprises (A) a heat-decomposable polymer, (B) an organic solvent, and (C) an aromatic ring containing resin, with the weight reduction rate of (A) the heat-decomposable polymer from 30° C. to 250° C. being 40% or more by mass. There can be provided an organic film composition having not only a high dry etching resistance but also an excellent filling-up or flattening characteristics. | 11-14-2013 |
| 20130302991 | COMPOSITION FOR FORMING RESIST UNDERLAYER FILM, CONTAINING SILICON THAT BEARS DIKETONE-STRUCTURE-CONTAINING ORGANIC GROUP - A composition for forming a lithographic resist underlayer film, including, as a silane, a hydrolyzable organosilane, a hydrolysate thereof, or a hydrolytic condensate thereof, wherein the silane includes a hydrolyzable organosilane of Formula (1) below: | 11-14-2013 |
| 20130309871 | METHODS OF FORMING A MASKING PATTERN FOR INTEGRATED CIRCUITS - In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes. | 11-21-2013 |
| 20130316539 | METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UNDOPED POLYSILICON GATES AFTER ETCHING - The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively. | 11-28-2013 |
| 20130323930 | Selective Capping of Metal Interconnect Lines during Air Gap Formation - Provided are methods and systems for forming air gaps in an interconnect layer between adjacent conductive lines. Protective layers may be selectively formed on exposed surfaces of the conductive lines, while structures in between the lines may remain unprotected. These structures may be made from a sacrificial material that is later removed to form voids. In certain embodiments, the structures are covered with a permeable non-protective layer that allows etchants and etching products to pass through during removal. When a work piece having a selectively formed protective layer is exposed to gas or liquid etchants, these etchants remove the sacrificial material without etching or otherwise impacting the metal lines. Voids formed in between these lines may be then partially filled with a dielectric material to seal the voids and/or protect sides of the metal lines. Additional interconnect layers may be formed above the processed layer containing air gaps. | 12-05-2013 |
| 20130323931 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 12-05-2013 |
| 20130337652 | MASK PATTERN FOR HOLE PATTERNING AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns. | 12-19-2013 |
| 20140011364 | METHODS OF FORMING A PATTERN ON A SUBSTRATE - A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed. | 01-09-2014 |
| 20140017898 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a plasma process. The method also involves, in the same operation, removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer. | 01-16-2014 |
| 20140017899 | DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES - Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity. | 01-16-2014 |
| 20140024219 | IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER - At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer. | 01-23-2014 |
| 20140030893 | METHOD FOR SHRINK AND TUNE TRENCH/VIA CD - A method for etching with CD reduction, an etch layer disposed below a silicon containing mask layer under a patterned organic mask with features with a first CD. Features are opened in the silicon containing mask layer using the patterned organic mask, comprising providing an opening gas with an etchant component and polymerizing component, forming the opening gas into a plasma, and providing a pulsed bias with a pulse frequency between 10 Hz and 1 kHz, which etches features through the silicon containing mask layer with a second CD, which is less than half the first CD, forming a pattern in the silicon containing mask layer. The pattern of the silicon containing mask layer is transferred to the etch layer. | 01-30-2014 |
| 20140030894 | METHODS OF FABRICATING FINE PATTERNS AND PHOTOMASK SETS USED THEREIN - Photo mask sets and methods of fabricating fine patterns are provided. The method includes forming a first layer having a first main pattern part and a first dummy pattern part on a base layer, forming a second layer on the first layer, etching the first layer using the second layer as an etch mask to form a third main pattern part composed of a remaining portion of the first main pattern part and to remove the first dummy pattern part, and removing the second layer. The second layer is formed to have a second main pattern part exposing portions of the first main pattern part and to have a second dummy pattern part exposing the first dummy pattern part. | 01-30-2014 |
| 20140045336 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device having patterns with different widths. The method includes etching a sacrificial pattern using a protective pattern that has a greater width and remains during an etch process of a spacer layer. Since the sacrificial pattern that has a greater width and remains under the protective pattern having a greater width is used as a pad mask pattern, a separate process of forming a pad mask pattern may not be necessary. Therefore, a method of manufacturing a semiconductor device may be simplified. | 02-13-2014 |
| 20140051252 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 02-20-2014 |
| 20140057441 | METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed. | 02-27-2014 |
| 20140057442 | SEMICONDUCTOR DEVICE WITH SILICON-CONTAINING HARD MASK AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer. | 02-27-2014 |
| 20140057443 | PATTERN FORMING METHOD - According to one embodiment, a pattern forming method includes forming a physical guide including a first predetermined pattern in a first region on a to-be-processed film, and a second predetermined pattern in a second region on the to-be-processed film, forming a block copolymer in the physical guide, forming a self-assembled phase including a first polymer portion and a second polymer portion by causing microphase separation of the block copolymer, removing the second polymer portion, and processing the to-be-processed film, with the physical guide and the first polymer portion serving as a mask. A pattern height of the first predetermined pattern is greater than a pattern height of the second predetermined pattern. | 02-27-2014 |
| 20140057444 | METHOD FOR MANUFACTURING MEMS DEVICE, METHOD FOR MANUFACTURING THERMAL DETECTOR, THERMAL DETECTOR, THERMAL DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A method for manufacturing a MEMS device having an undercut shape formed on a fixed part includes a first step of forming an etching layer having a first cavity on the fixed part; a second step of forming a mask layer on a side wall of the etching layer, the side wall facing the first cavity; and a third step of directing an etchant fed into the first cavity on a surface side of the mask layer to a back surface side of the mask layer, isotropically etching the etching layer, forming a second cavity communicated with the first cavity on the back surface side of the mask layer, and processing the etching layer into an undercut shape. | 02-27-2014 |
| 20140065830 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process. The first and second inorganic thin film dielectric material layers form a patterned inorganic thin film dielectric stack. | 03-06-2014 |
| 20140065831 | PATTERNED THIN FILM DIELECTRIC LAYER FORMATION - A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. | 03-06-2014 |
| 20140065832 | ENHANCED FINFET PROCESS OVERLAY MARK - An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin. | 03-06-2014 |
| 20140065833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns. | 03-06-2014 |
| 20140073137 | METHODS FOR SINGLE EXPOSURE - SELF-ALIGNED DOUBLE, TRIPLE, AND QUADRUPLE PATTERNING - A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern. | 03-13-2014 |
| 20140080306 | METHOD OF FORMING FINE PATTERNS - A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate. | 03-20-2014 |
| 20140080307 | PATTERN-FORMING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A pattern-forming method for forming a predetermined pattern serving as a mask when etching film on a substrate includes the steps of: an organic film pattern-forming step for forming an organic film pattern on a film to be processed; forming a silicon nitride film on the organic film pattern; etching the silicon nitride film so that the silicon nitride film remains only on the lateral wall sections of the organic film pattern; and removing the organic film, thereby forming the predetermined silicon nitride film pattern on the film to be processed on a substrate. With the temperature of the substrate maintained at no more than 100° C., the film-forming step excites a processings gas and generates a plasma, performs plasma processing with the plasma, and forms a silicon nitride film having stress of no more than 100 MPa. | 03-20-2014 |
| 20140094035 | CARBON DEPOSITION-ETCH-ASH GAP FILL PROCESS - Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles. | 04-03-2014 |
| 20140106569 | METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICE FABRICATED USING THE SAME - According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth. | 04-17-2014 |
| 20140106570 | COMPOSITION FOR FORMING ORGANIC HARD MASK LAYER FOR USE IN LITHOGRAPHY CONTAINING POLYMER HAVING ACRYLAMIDE STRUCTURE - Whereas, conventionally, ashing had been used at the time of removal, the present invention provides a material for forming an organic hard mask that can be removed by an alkaline aqueous solution, and thus can be expected to reduce damage to the substrate at the time of the removal. A composition for forming an organic hard mask layer comprising: a polymer (A) including a structural unit of Formula (1) and a structural unit of Formula (2); a crosslinkable compound (B) including at least two of blocked isocyanate groups, methylol groups, or C | 04-17-2014 |
| 20140120729 | METHOD FOR REMOVING A PATTERNED HARD MASK LAYER - The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer. | 05-01-2014 |
| 20140120730 | THIN FILM FORMING COMPOSITION FOR LITHOGRAPHY CONTAINING TITANIUM AND SILICON - A thin film forming composition for forming resist underlayer film useable in the production of a semiconductor device, and a resist upper layer film absorbs undesirable UV light with a thin film as an upper layer of the EUV resist before undesirable UV light reaches the EUV resist layer in EUV lithography, an underlayer film (hardmask) for an EUV resist, a reverse material, and an underlayer film for a resist for solvent development. The thin film forming composition useable together with a resist in a lithography process, comprising a mixture of titanium compound (A) selected from: | 05-01-2014 |
| 20140127910 | PATTERN FORMATION METHOD AND BLOCK COPOLYMER - According to one embodiment, a pattern formation method includes: forming a block copolymer layer containing a polystyrene derivative and an acrylic having 6 or more carbon atoms on a side chain in an opening of a resist layer provided on an underlayer and having the opening; forming a first layer containing the polystyrene derivative and a second layer containing the acrylic in the opening by phase-separating the block copolymer layer; and removing the second layer. | 05-08-2014 |
| 20140134846 | PLASMA ETCHING METHOD - A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S | 05-15-2014 |
| 20140154887 | SEMICONDUCTOR DEVICE PROCESSING TOOLS AND METHODS FOR PATTERNING SUBSTRATES - In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first subset of processes on a substrate having pattern features, the first subsystem including a first conformal deposition chamber and a first etch chamber. The processing tool includes a second subsystem coupled to the first subsystem and configured to carry out a second subset of processes on the substrate, the second subsystem including a second conformal deposition chamber and a second etch chamber. The processing tool is configured to employ the first and second subsystems to perform pitch division on the substrate within the processing tool so as to form a reduced-pitch pattern on the substrate. Numerous other embodiments are provided. | 06-05-2014 |
| 20140162460 | METHOD OF FORMING A PATTERN - A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region. | 06-12-2014 |
| 20140162461 | METHODS FOR FORMING A SEMICONDUCTOR DEVICE INCLUDING FINE PATTERNS - Methods for forming a semiconductor device including fine patterns are provided. The method may include forming a mask layer including first holes spaced apart from each other in a first direction and a second direction. The method may also include forming local mask patterns on the mask layer and forming a sacrificial layer on the mask layer filling the first holes and surrounding the local mask patterns. The local mask patterns may be offset from the first holes in the first direction and the second direction. The method may further include removing the local mask patterns to form openings in the sacrificial layer exposing the mask layer and etching the mask layer through the opening to form second holes in the mask layer. | 06-12-2014 |
| 20140170855 | SILICON-CONTAINING RESIST UNDERLAYER FILM-FORMING COMPOSITION HAVING SULFONE STRUCTURE - A composition for forming a resist underlayer film for lithography, including: as a silane, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, or a hydrolysis-condensation product of the hydrolyzable organosilane, wherein the hydrolyzable organosilane is a compound of Formula (1): | 06-19-2014 |
| 20140187047 | PATTERNING PROCESS METHOD FOR SEMICONDUCTOR DEVICES - A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask. | 07-03-2014 |
| 20140187048 | Plasma Etching Method - An object of the present invention is to provide a plasma etching method capable of forming a tapered recess portion in a wide-gap semiconductor substrate. As a solving means therefor, a high speed etching film E an etching speed of which is higher than that of a wide-gap semiconductor substrate K is formed on the wide-gap semiconductor substrate K, and a mask M having an opening is formed on the high speed etching film E. Thereafter, the wide-gap semiconductor substrate K having the high speed etching film E and the mask M formed thereon is placed on a platen and is heated to a temperature equal to or higher than 200° C., then a plasma is generated form an etching gas supplied into a processing chamber and a bias potential is applied to the platen, and thereby the wide-gap semiconductor substrate K is etched. | 07-03-2014 |
| 20140199847 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask. | 07-17-2014 |
| 20140213060 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O | 07-31-2014 |
| 20140220782 | METHODS OF FORMING HOLE PATTERNS OF SEMICONDUCTOR DEVICES - A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern. | 08-07-2014 |
| 20140220783 | PATTERN-FORMING METHOD AND RESIST UNDERLAYER FILM-FORMING COMPOSITION - A pattern-forming method includes providing a resist underlayer film on a substrate using a resist underlayer film-forming composition. The resist underlayer film-forming composition includes a first polymer having a glass transition temperature of 0 to 180° C. A silicon-based oxide film is provided on a surface of the resist underlayer film. A resist pattern is provided on a surface of the silicon-based oxide film using a resist composition. The silicon-based oxide film and the resist underlayer film are sequentially dry-etched using the resist pattern as a mask. The substrate is dry-etched using the dry-etched resist underlayer film as a mask. | 08-07-2014 |
| 20140235060 | RESIST UNDERLAYER FILM-FORMING COMPOSITION WHICH CONTAINS ALICYCLIC SKELETON-CONTAINING CARBAZOLE RESIN - There is provided a resist underlayer film used in lithography process that has a high n value and a low k value, and can effectively reduce reflection of light having a wavelength of 193 nm from the substrate in a three-layer process in which the resist underlayer film is used in combination with a silicon-containing intermediate layer. A resist underlayer film-forming composition used in lithography process including: a polymer containing a unit structure including a product obtained by reaction of a condensed heterocyclic compound and a bicyclo ring compound. The condensed heterocyclic compound is a carbazole compound or a substituted carbazole compound. The bicyclo ring compound is dicyclopentadiene, substituted dicyclopentadiene, tetracyclo[4.4.0.1 | 08-21-2014 |
| 20140242800 | METHODS OF FORMING LAYER PATTERNS OF A SEMICONDUCTOR DEVICE - A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern. | 08-28-2014 |
| 20140256140 | Methods Of Forming A Pattern On A Substrate - A method of forming a pattern on a substrate includes forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Photoresist is formed elevationally over and laterally inward of the cylinder-like structures. The photoresist is patterned to form interstitial spaces into the photoresist laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by at least three of the cylinder-like structures. The patterned photoresist is used as an etch mask while etching interstitial openings into the base and while the photoresist is laterally inward of the cylinder-like structures. Other aspects are disclosed. | 09-11-2014 |
| 20140256141 | METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS - A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles. | 09-11-2014 |
| 20140256142 | METHOD OF ETCHING AN ETCH LAYER - A method for etching an etch layer is provided. A glue layer having metallizable terminations is formed over the etch layer. The glue layer is exposed to a patterned light, wherein the metallizable terminations of the glue layer illuminated by the patterned light become unmetallizable. A metal deposition layer is formed on the glue layer, wherein the metal deposition layer only deposits on areas of the glue layer with metallizable terminations of the glue layer. The etch layer is etched through portions of the glue layer without the metal deposition layer. | 09-11-2014 |
| 20140256143 | Method for Hard Mask Loop with Defect Reduction - The present disclosure provides one embodiment of a method of fabricating an integrated circuit. The method includes forming a patterned hard mask on a substrate; performing a fabrication process to the substrate through openings of the patterned hard mask; performing a first etch process to remove the patterned hard mask; and applying an NHD solution to the substrate, wherein the NHD solution includes ammonium hydroxide, hydrogen peroxide and deionized water with ratios tuned such that the NHD solution is weak basic. | 09-11-2014 |
| 20140256144 | SEMICONDUCTOR FIN FORMATION METHOD AND MASK SET - A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks. | 09-11-2014 |
| 20140256145 | DSA GRAPHO-EPITAXY PROCESS WITH ETCH STOP MATERIAL - A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials. | 09-11-2014 |
| 20140256146 | Method and Structure to Improve Process Window for Lithography - The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process | 09-11-2014 |
| 20140273473 | METHODS OF FORMING A MASKING LAYER FOR PATTERNING UNDERLYING STRUCTURES - One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure. | 09-18-2014 |
| 20140273474 | INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT) - Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer. | 09-18-2014 |
| 20140273475 | METHODS FOR FABRICATING GUIDE PATTERNS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH GUIDE PATTERNS - Methods for fabricating guide patterns and methods for fabricating integrated circuits using guide patterns are provided. In an embodiment, a method for fabricating a guide pattern includes forming a coating of a material with latent grafting sites and a photosensitive component configured to activate the latent grafting sites upon exposure over a substrate. The method exposes selected latent grafting sites in the coating to convert the selected latent grafting sites to active grafting sites. A grafting agent is bonded to the active grafting sites to form the guide pattern. | 09-18-2014 |
| 20140273476 | METHODS OF REDUCING DEFECTS IN DIRECTED SELF-ASSEMBLED STRUCTURES - Methods are disclosed for reducing the number of defects in a directed self-assembled structure formed on a guiding pre-pattern (e.g., a chemical pre-pattern) on a substrate. A first layer comprising a first self-assembly material is applied onto the guiding pre-pattern, with the first self-assembly material forming domains whose alignment and orientation are directed by the guiding pre-pattern; as a result, a first self-assembled structure is formed. The first self-assembled structure is washed away, and a second layer comprising a second self-assembly material is then applied. The second self-assembly material forms a second self-assembled structure having fewer defects than the first self-assembled structure. | 09-18-2014 |
| 20140273477 | Si PRECURSORS FOR DEPOSITION OF SiN AT LOW TEMPERATURES - Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). | 09-18-2014 |
| 20140273478 | Reducing Defects in Patterning Processes - A method includes forming a mask layer forming a first photo resist over the mask layer, performing a first patterning step on the first photo resist, and performing a first etching step on the mask layer using the first photo resist as an etching mask. The first photo resist is then removed. The method further includes forming a particle-fixing layer on a top surface and sidewalls of the mask layer, forming a second photo resist over the particle-fixing layer and the mask layer, performing a second patterning step on the second photo resist, and performing a second etching step on the particle-fixing layer and the mask layer using the second photo resist as an etching mask. The particle-fixing layer is etched through. A target layer underlying the mask layer is etched using the mask layer as an etching mask. | 09-18-2014 |
| 20140273479 | PLASMA PRE-TREATMENT FOR IMPROVED UNIFORMITY IN SEMICONDUCTOR MANUFACTURING - Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate. | 09-18-2014 |
| 20140273480 | METHOD FOR PRODUCING A SUBSTRATE PROVIDED WITH EDGE PROTECTION - The method for producing a substrate provided with protection of its edges has a first step which is providing a substrate having a semiconductor material base. The substrate has opposite first and second main surfaces connected by a lateral surface. A first layer made from first protective material is then formed so as to coat the substrate. The first protective material is then etched on the lateral surface leaving a pattern of first protective material at least partially covering each of the first and second surfaces, and a second protective layer made from second protective material is then formed on the lateral surface devoid of the first protective material. After formation of the second protective layer, the first protective material is eliminated from the substrate. | 09-18-2014 |
| 20140315389 | CRACK CONTROL FOR SUBSTRATE SEPARATION - A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack. | 10-23-2014 |
| 20140315390 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-23-2014 |
| 20140315391 | Method of Manufacturing a Semiconductor Device Including a Stress Relief Layer - A method of manufacturing a semiconductor device includes providing a layered structure having a hard dielectric layer containing a first dielectric material having a Young's modulus greater than 10 GPa in a central portion of a main surface of a main body comprising a single crystalline semiconductor body, and providing a dielectric stress relief layer containing a second dielectric material having a lower Young's modulus than the first dielectric material, the stress relief layer covering the layered structure and extending beyond an outer edge of the layered structure. | 10-23-2014 |
| 20140322917 | GRAPHO-EPITAXY DSA PROCESS WITH DIMENSION CONTROL OF TEMPLATE PATTERN - A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern. | 10-30-2014 |
| 20140329389 | BULK NANO-RIBBON AND/OR NANO-POROUS STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME - Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 μm. Each of the multiple nano-ribbons corresponds to a cross-sectional area associated with a ribbon thickness, and the ribbon thickness ranges from 5 nm to 500 nm. Each of the multiple nano-ribbons is separated from at least another nano-ribbon selected from the multiple nano-ribbons by a second distance ranging from 5 nm to 500 nm. | 11-06-2014 |
| 20140342564 | Photomask With Three States For Forming Multiple Layer Patterns With A Single Exposure - The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern. | 11-20-2014 |
| 20140342565 | METHOD OF MANUFACTURING DUAL GATE OXIDE DEVICES - The present invention provides method of manufacturing dual gate oxide devices. The method comprises coating photoresist on the substrate which is deposited by an oxide thin film; removing some of the photoresist by exposure and development to divide the oxide thin film into a first area to be etched and a second area coated by the remained photoresist; coating RELACS material on the remained photoresist and heating to form a protective film based on the crosslinking reaction between the RELACS material and the high molecular compounds in the photoresist; performing UV radiation to strengthen and cure the protective film; removing the oxide thin film in the first area by etching and removing the remained photoresist; and depositing again an oxide film to form an oxide layer of different thickness in the first area and the second area so as to form a dual gate oxide structure. | 11-20-2014 |
| 20140342566 | Manufacturing Method of Semiconductor Device - To improve the manufacturing yield of semiconductor devices. Over a semiconductor wafer, a film to be processed is formed; over that film, an antireflection film is formed; and, over the antireflection film, a resist layer is formed. Then, the resist layer is subjected to liquid immersion exposure, and a development and rinsing process to form a resist pattern. After that, the antireflection film and the film to be processed are etched sequentially using the resist pattern as an etching mask. In the development process of the resist layer, the antireflection film is exposed from parts from which the resist layer has been removed by the development process. When performing a rinsing process after the development, the water repellent property of the surface of the antireflection film exposed from the resist layer is not lower than the water repellent property of the surface of the resist layer. | 11-20-2014 |
| 20140342567 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate. | 11-20-2014 |
| 20140370714 | ROLLER APPARATUS, PRINTING METHOD AND METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - Provided are a roller apparatus, a printing method and a method of fabricating an LCD device using the same, which can minimize the number of processes and a printing defect. In the printing method, first patterns are formed on a blanket. The first patterns have different surface energy from that of the blanket, and the blanket is formed around a roller. The roller is rotated and a printing material is dropped to form second patterns on the blanket between the first patterns. The second patterns are transferred from the roller onto a substrate. | 12-18-2014 |
| 20140377956 | PATTERN FORMING METHOD - According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter. | 12-25-2014 |
| 20140377957 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SILICON-CONTAINING RESIST UNDERLAYER FILM FORMING COMPOSITION FOR SOLVENT DEVELOPMENT - A resist underlayer film for a resist pattern formation by developing a resist with organic solvent after exposure of resist. Method for manufacturing a semiconductor includes: applying onto a substrate a resist underlayer film forming composition including hydrolyzable silanes, hydrolysis products of hydrolyzable silanes, hydrolysis-condensation products of hydrolyzable silanes, or a combination thereof. Hydrolyzable silanes being silane of Formulas (1), (2) and (3). Silane of Formulas (1), (2) and (3) in total silanes in a ratio % by mole of 45-90:6-20:0-35; baking the applied resist underlayer film forming composition to form a resist underlayer film; applying a composition to form a resist film; exposing the resist film to light; developing the resist film after exposure, with organic solvent to obtain patterned resist film; and etching the resist underlayer film by using the patterned resist film and processing the substrate using the patterned resist underlayer film; wherein | 12-25-2014 |
| 20150011090 | FIN-SHAPED STRUCTURE FORMING PROCESS - A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively. | 01-08-2015 |
| 20150011091 | SUBSTRATE PROCESSING METHOD AND CONTROL APPARATUS - Provided is a substrate processing method of filling a recess of a predetermined uneven pattern formed on a substrate with a film forming material by performing a first film forming processing, a first etching processing and a second film forming processing on the substrate, using a vertical substrate processing apparatus and a control apparatus controlling operations of the vertical substrate processing apparatus. The method includes calculating a first film forming condition, a first etching condition, and a second film forming condition by the control apparatus such that the film forming material is filled in the recess without any void after the second film forming processing; and performing the first film forming processing, the first etching processing and the second film forming processing on the substrate based on the calculated first film forming condition, first etching condition and second film forming condition. | 01-08-2015 |
| 20150011092 | RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING COPOLYMER RESIN HAVING HETEROCYCLIC RING - A resist underlayer film-forming composition for forming a resist underlayer film having both dry etching resistance and heat resistance. A resist underlayer film-forming composition comprising a polymer containing a unit structure of Formula (1): | 01-08-2015 |
| 20150017808 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space. | 01-15-2015 |
| 20150024602 | METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 01-22-2015 |
| 20150031210 | METHODS OF FABRICATING FINE PATTERNS - Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains. | 01-29-2015 |
| 20150031211 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 01-29-2015 |
| 20150044875 | METHOD OF FORMING PATTERN - A method of forming a pattern is disclosed. First, N kinds of different photomask patterns are provided. Thereafter, the N kinds of different photomask patterns are transferred to a hard mask layer by using at least N−1 kinds of light sources with different wavelengths, so as to form a hard mask pattern, wherein one of the at least N−1 kinds of light sources with different wavelengths is a light source with a wavelength of 193 nm, and N is an integer of three or more. | 02-12-2015 |
| 20150044876 | RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING PHENYLINDOLE-CONTAINING NOVOLAC RESIN - A composition for forming a resist underlayer film having heat resistance, which is used for a lithography process of semiconductor device production. A resist underlayer film forming composition including a polymer having a unit structure of Formula (1): | 02-12-2015 |
| 20150050811 | CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES MANUFACTURED USING DOUBLE PATTERNING TECHNIQUES - An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure. | 02-19-2015 |
| 20150056810 | METHOD FOR SEMICONDUCTOR CROSS PITCH DOUBLED PATTERNING PROCESS - The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns. | 02-26-2015 |
| 20150056811 | STACKED STRUCTURE BODY AND PATTERN FORMATION METHOD - According to one embodiment, a stacked structure body includes: an underlayer; a mask layer provided on the underlayer; a copolymer-containing layer provided on the mask layer, the copolymer-containing layer containing a metal and carbon, and the copolymer-containing layer including a first copolymer region and a second copolymer region provided on the first copolymer region, and the second copolymer region having a lower proportion of a metal concentration to a carbon concentration than the first copolymer region; and a resist pattern provided on the copolymer-containing layer. | 02-26-2015 |
| 20150056812 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench. | 02-26-2015 |
| 20150056813 | SELF-ASSEMBLED MONOLAYER FOR PATTERN FORMATION - The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A first self-assembled monolayer (SAM) layer is formed over the one or more layers, wherein the first SAM layer exhibits a first SAM pattern. At least a first of the one or more layers is patterned using the first SAM layer as a first etch mask to form first pillars in the first of the one or more layers and then removing the first SAM layer. A second self-assembled monolayer (SAM) layer is formed along sidewall portions of the first pillars after the first SAM layer has been removed, wherein the second SAM layer exhibits a second SAM pattern that differs from the first SAM pattern and where the second SAM layer differs in material composition from the first SAM layer. | 02-26-2015 |
| 20150064917 | UV-Assisted Stripping of Hardened Photoresist to Create Chemical Templates for Directed Self-Assembly - A processing method is disclosed that enables an improved directed self-assembly (DSA) processing scheme by allowing the formation of improved guide strips in the DSA template that may enable the formation of sub-30 nm features on a substrate. The improved guide strips may be formed by improving the selectivity of wet chemical processing between different organic layers or films. In one embodiment, treating the organic layers with one or more wavelengths of ultraviolet light may improve selectivity. The first wavelength of UV light may be less than 200 nm and the second wavelength of UV light may be greater than 200 nm. | 03-05-2015 |
| 20150072530 | METHODS FOR ETCHING MATERIALS USING SYNCHRONIZED RF PULSES - Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points. | 03-12-2015 |
| 20150072531 | METHOD FOR FORMING LAYOUT PATTERN - A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate. | 03-12-2015 |
| 20150072532 | PATTERNING METHOD - A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask. | 03-12-2015 |
| 20150079792 | SILICON-CONTAINING EUV RESIST UNDERLAYER FILM-FORMING COMPOSITION INCLUDING ADDITIVE - There is provided a composition for forming an EUV resist underlayer film which shows a good resit form. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (A) containing a hydrolyzed condensate of hydrolyzable silane (a); and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (B) containing a hydrolyzed condensate of hydrolyzable silane (a) and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. The polysiloxane (A) is preferably a co-hydrolyzed condensate of a tetraalkoxysilane, an alkyltrialkoxysilane and an aryltrialkoxysilane. | 03-19-2015 |
| 20150079793 | ADHESION-PROMOTING COMPOSITION USED BETWEEN CURABLE COMPOSITION FOR IMPRINTS AND SUBSTRATE, AND SEMICONDUCTOR DEVICE USING THE SAME - Provided is an adhesion-promoting composition between a curable composition for imprints and a substrate, which excellent in adhesiveness and can control pattern failure. An adhesion-promoting composition used between a curable composition for imprints and a substrate, which comprises a compound having a molecular weight of 500 or larger and having a reactive group, and has a content of a compound, with a molecular weight of 200 or smaller, of more than 1% by mass and not more than 10% by mass of a total solid content. | 03-19-2015 |
| 20150079794 | PATTERN FORMING METHOD - A pattern forming method includes forming a coating film containing a hydrophilic first homopolymer having a first bonding group and a hydrophobic second homopolymer having a second bonding group capable of bonding with the first bonding group, forming a bond between the first and second bonding group to produce a block copolymer of the first and second homopolymners, and heating the coating film to microphase-separating the copolymer into a hydrophilic domain and a hydrophobic domain. The hydrophilic and hydrophobic domains are arranged alternately. The bond is broken, then selectively dissolving-removing either domain by a solvent to provide a polymer pattern of a remainder domain. | 03-19-2015 |
| 20150087154 | HIGH ASPECT RATIO ETCH WITH COMBINATION MASK - A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask. | 03-26-2015 |
| 20150087155 | RESIST UNDERLAYER FILM-FORMING COMPOSITION - A composition forms a resist underlayer film showing improved adhesiveness to a resist pattern. A resist underlayer film-forming composition for lithography, including: a polymer that has a structure of Formula (1a), Formula (1b), or Formula (2) below on an end of the polymer; and an organic solvent: | 03-26-2015 |
| 20150093902 | Self-Aligned Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step. | 04-02-2015 |
| 20150093903 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - According to one embodiment, a method of manufacturing a semiconductor device includes forming a resist and a layer to be etched on a substrate, forming a non-cured layer on the resist by supplying a metal compound containing Ru, forming a cured layer on a surface layer of the resist by using the non-cured layer, and etching the layer to be etched by reactive ion etching using the cured layer and the resist as a mask. | 04-02-2015 |
| 20150093904 | ARRAYS OF LONG NANOSTRUCTURES IN SEMICONDUCTOR MATERIALS AND METHODS THEREOF - An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 μm. All nanowires of the plurality of nanowires are substantially parallel to each other. | 04-02-2015 |
| 20150104944 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - There is provided a method of forming patterns for a semiconductor device. The method sequentially forming a first mask layer and a second mask layer on a substrate. The method also includes forming a second mask pattern layer by patterning the second mask layer. The method further includes forming a first mask pattern layer having a negative slope portion, by etching the first mask layer exposed through the second mask pattern layer. The method also includes forming a thin film layer on the substrate exposed through the first mask pattern layer. | 04-16-2015 |
| 20150104945 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer. | 04-16-2015 |
| 20150104946 | METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES - Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings. | 04-16-2015 |
| 20150104947 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASKS - Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1. | 04-16-2015 |
| 20150111386 | USE OF TOPOGRAPHY TO DIRECT ASSEMBLY OF BLOCK COPOLYMERS IN GRAPHO-EPITAXIAL APPLICATIONS - A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) surrounds the exposed topography. Further to the method, the template is filled with a block copolymer (BCP) to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography. | 04-23-2015 |
| 20150111387 | USE OF TOPOGRAPHY TO DIRECT ASSEMBLY OF BLOCK COPOLYMERS IN GRAPHO-EPITAXIAL APPLICATIONS - A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) is formed surrounding the exposed topography. Further to the method, the exposed template surfaces are chemically treated. In one embodiment, the surfaces are treated with a hydrogen-containing reducing chemistry to alter the surfaces to a less oxidized state. In another embodiment, the surfaces are coated with a first phase of a block copolymer (BCP) to render the surfaces more attractive to the first phase than prior to the coating. The template is then filled with the BCP to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography. | 04-23-2015 |
| 20150118850 | Lithography using Multilayer Spacer for Reduced Spacer Footing - A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer. | 04-30-2015 |
| 20150118851 | METHOD FOR DIRECTED SELF-ASSEMBLY (DSA) OF BLOCK COPOLYMERS - In directed self-assembly (DSA) of a block copolymer (BCP), a patterned sublayer on a substrate serves as a guiding chemical prepattern on which BCPs form more uniform and/or denser patterns. A layer of a blend of a BCP and functional homopolymers, referred to as inks, is deposited on the patterned sublayer and annealed to change the initial chemical prepattern to a 1:1-like chemical pattern that is more favorable to DSA. After annealing, the inks selectively distribute into blocks by DSA, and part of the inks graft on the substrate underneath the blocks. The BCP blend layer is then rinsed away, leaving the grafted inks A second layer of BCP is then deposited and annealed as a second DSA step to form alternating lines of the BCP components. One of the BCP components is removed, leaving lines of the other BCP component as a mask for patterning the substrate. | 04-30-2015 |
| 20150118852 | METHOD OF FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method of forming a pattern of a semiconductor device includes providing a substrate, forming a photoresist layer by coating a resist composition including an acid generator and a first resin, the first resin having an acid-labile group, exposing the photoresist layer, forming a photoresist pattern by negatively developing the photoresist layer using a developing solution including an organic solvent, coating a capping composition including a second resin and the organic solvent on the substrate having the photoresist pattern formed thereon, and attaching a capping layer on upper and side surfaces of the photoresist pattern, by baking the capping composition and developing the capping composition using the developing solution including the organic solvent. | 04-30-2015 |
| 20150118853 | METHOD FOR FORMING STAIR-STEP STRUCTURES - A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times. | 04-30-2015 |
| 20150132962 | FACILITATING MASK PATTERN FORMATION - Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern. | 05-14-2015 |
| 20150132963 | MECHANISM FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Embodiments of mechanisms of forming a semiconductor device structure are provided. The method includes providing a substrate, forming a first material layer on the substrate, forming a second material layer on the first material layer and forming a first PR layer on the second material layer. The method includes exposing a portion of the first PR layer to a first radiation beam and forming a second PR layer on the first PR layer. The method includes exposing a portion of the second PR layer to a second radiation beam and developing the first PR layer and the second PR layer to form a patterned first PR layer and a patterned second PR layer. The method includes etching a portion of the first material layer and the second material layer by using the patterned first PR layer and the patterned second PR layer as a mask. | 05-14-2015 |
| 20150132964 | Method of Patterning - In a patterning method according to the present embodiment, a guide pattern is formed on a processing target film. The guide pattern is configured by concave portions and convex portions extending in a predetermined direction. A block copolymer layer is formed on the guide pattern. The block copolymer layer contains at least two block chains. A layer of microphase-separated structures is formed on the concave portions and the convex portions, respectively, by microphase-separating the block copolymer layer. The processing target film is formed into predetermined patterns by selectively removing the processing target film. At least a part of the block copolymer layer is used as a mask. | 05-14-2015 |
| 20150132965 | Method for Using Post-Processing Methods for Accelerating EUV Lithography - Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development. | 05-14-2015 |
| 20150132966 | METHOD FOR FORMING A FINFET STRUCTURE - A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure. | 05-14-2015 |
| 20150140825 | Method for Chemical Polishing and Planarization - A chemical planarization process described herein can be used for planarizing a substrate without using mechanical abrasion. A developable planarization material can be applied to a substrate having a non-planar topography, such that a planar surface results. The resulting planarization layer can cover existing structures on the substrate. A top portion of the planarization layer can be solubilized using a solubility-changing agent, and then the soluble portion can be removed thereby slimming a height of the planarization material to a target value, which can be a top surface of a tallest underlying structure. With the substrate planarized, additional patterning operations can be executed. | 05-21-2015 |
| 20150140826 | Method of Forming Fine Patterns - A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate. | 05-21-2015 |
| 20150147887 | MECHANISMS FOR FORMING PATTERNS - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns. | 05-28-2015 |
| 20150294058 | MARK SEGMENTATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE APPLYING THE SAME - In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width W | 10-15-2015 |
| 20150294878 | METHOD FOR PATTERNING CONTACT OPENINGS ON A SUBSTRATE - Techniques herein include methods for patterning substrates including methods for patterning contact openings. Using techniques herein, slot contacts and other openings can be created having a selectable width between approximately 1-30 nanometers or less. Methods include creating trench widths defined by diffusion lengths of photo acid as part of a double patterning scheme. These trenches can then be filled and a separate mask can then be used to isolate segments of trenches. The segments can then be extruded resulting in slot contact openings which are ready to be metallized. These slot contacts have a length defined by lithographic exposure techniques and a width defined by photo acid diffusion lengths. | 10-15-2015 |
| 20150303055 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SURFACE TREATING FOR DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes surface treating exposed portions of an anti-reflective coating (ARC) that overlie a semiconductor substrate to form surface treated ARC portions. A neutral layer is formed overlying the anti-reflective coating including over the surface treated ARC portions. First portions of the neutral layer are selectively removed and second portions of the anti-reflective coating that are disposed under the first portions laterally adjacent to the surface treated ARC portions are exposed to define a guide pattern. A block copolymer layer is deposited overlying the guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the guide pattern. | 10-22-2015 |
| 20150303067 | MECHANISMS FOR FORMING PATTERNS - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns. | 10-22-2015 |
| 20150311442 | METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method for forming pattern includes forming a guide layer on a substrate, forming a copolymer layer of a high-molecular block copolymer on the guide layer; and forming a phase-separation structure with a phase-separation cycle d by self-assembling the copolymer layer. The high-molecular block copolymer includes a first and a second polymer. The guide layer includes a first and a second region disposed on the substrate. Widths of the first and second region respectively are approximately (d/2)×n and (d/2)×m. Both of the first and second region are to be pinned with none of the first and second polymer. Surface energies of the first and second region are different from one another. Integers n and m are odd numbers. Value d is a phase-separation cycle of the high-molecular block copolymer. | 10-29-2015 |
| 20150316850 | RESIST UNDERLAYER FILM-FORMING COMPOSITION COMPRISING CARBONYL-CONTAINING POLYHYDROXY AROMATIC RING NOVOLAC RESIN - There is provided resist underlayer film for lithography process with high dry etching resistance, wiggling resistance, and heat resistance. Resist underlayer film-forming composition for lithography including polymer having unit structure of Formula (1): wherein A is hydroxy group-substituted C | 11-05-2015 |
| 20150322212 | COMPOSITION FOR FORMING SILICON-CONTAINING RESIST UNDERLAYER FILM HAVING CYCLIC DIESTER GROUP - A resist underlayer film that can be used as a hardmask. A resist underlayer film forming composition for lithography, includes: as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein the hydrolyzable silane includes a hydrolyzable silane of Formula (1) or a hydrolyzable silane containing a combination of a hydrolyzable silane of Formula (1) with a hydrolyzable silane of Formula (2) in a content of less than 50% by mole in all silanes; | 11-12-2015 |
| 20150325453 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer. | 11-12-2015 |
| 20150325744 | METHOD OF MANUFACTURING OPTOELECTRONIC ELEMENT HAVING ROUGH SURFACE - A method of forming a rough surface includes: providing an article having a top surface, forming a plurality of agglomerated grains on the top surface by a deposition process, and patterning the top surface to form a rough surface by using the plurality of agglomerated grains as a mask. | 11-12-2015 |
| 20150340239 | Method of Forming Multiple Patterning Spacer Structures - Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening. | 11-26-2015 |
| 20150340246 | METHOD OF FORMING PATTERNS AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME - A method of forming patterns may use an organic reflection-preventing film including a polymer having an acid-liable group. A photoresist film is formed on the organic reflection-preventing film. A first area selected from the photoresist film is exposed to generate an acid in the first area. Hydrophilicity of a first surface of the organic reflection-preventing film facing the first area of the photoresist film may be increased. The photoresist film including the exposed first area is developed to remove a non-exposed area of the photoresist film. The organic reflection-preventing film and a target layer are anisotropically etched by using the first area of the photoresist film as an etch mask. | 11-26-2015 |
| 20150340611 | METHOD FOR A DRY EXHUMATION WITHOUT OXIDATION OF A CELL AND SOURCE LINE - Various embodiments of the present invention are directed to a method for fabricating a memory cell comprising performing a passivation step on a cell structure and cell source lines prior to exhuming a masking layer to prevent oxidation of the cell structure and source lines. | 11-26-2015 |
| 20150348794 | HARDMASK COMPOSITION AND METHOD OF FORMING PATTERN BY USING THE HARDMASK COMPOSITION - A hardmask composition may include a solvent and a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen or a 2-dimensional carbon nanostructure precursor thereof. A content of oxygen in the 2-dimensional carbon nanostructure precursor may be lower than about 0.01 atom % or greater than about 40 atom %. The hardmask composition may be used to form a fine pattern. | 12-03-2015 |
| 20150357183 | METHODS FOR FORMING INTERCONNECT STRUCTURE UTILIZING SELECTIVE PROTECTION PROCESS FOR HARDMASK REMOVAL PROCESS - Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate. | 12-10-2015 |
| 20150357196 | Reducing Defects in Patterning Processes - A method includes forming a mask layer forming a first photo resist over the mask layer, performing a first patterning step on the first photo resist, and performing a first etching step on the mask layer using the first photo resist as an etching mask. The first photo resist is then removed. The method further includes forming a particle-fixing layer on a top surface and sidewalls of the mask layer, forming a second photo resist over the particle-fixing layer and the mask layer, performing a second patterning step on the second photo resist, and performing a second etching step on the particle-fixing layer and the mask layer using the second photo resist as an etching mask. The particle-fixing layer is etched through. A target layer underlying the mask layer is etched using the mask layer as an etching mask. | 12-10-2015 |
| 20150357204 | QUATERNARY AMMONIUM SALT COMPOUND, COMPOSITION FOR FORMING A RESIST UNDER LAYER FILM, AND PATTERNING PROCESS - A quaternary ammonium salt compound is represented by the following formula (A-1), | 12-10-2015 |
| 20150362838 | RESIST UNDERLAYER FILM-FORMING COMPOSITION - A composition forms a resist underlayer film showing improved adhesiveness to a resist pattern. A resist underlayer film-forming composition for lithography, including: a polymer that has a structure of Formula (1a), Formula (1b), or Formula (2) below on an end of the polymer; and an organic solvent: | 12-17-2015 |
| 20150364334 | METHOD OF FORMING PATTERNS AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE - Provided are a method of forming patterns and a method of manufacturing an integrated circuit device. In the method of forming patterns, a photoresist pattern having a first opening exposing a first region of a target layer is formed. A capping layer is formed at sidewalls of the photoresist pattern defining the first opening. An insoluble region is formed around the first opening by diffusing acid from the capping layer to the inside of the photoresist pattern. A second opening exposing a second region of the target layer is formed by removing a soluble region spaced apart from the first opening, with the insoluble region being interposed therebetween. The target layer is etched using the insoluble region as an etch mask. | 12-17-2015 |
| 20150368504 | AROMATIC RESINS FOR UNDERLAYERS - Aromatic resin polymers and compositions containing them are useful as underlayers in semiconductor manufacturing processes. | 12-24-2015 |
| 20150371896 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-24-2015 |
| 20150378260 | RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING ARYL SULFONATE SALT HAVING HYDROXYL GROUP - There is provided a resist underlayer film-forming composition to reduce the amount of sublimate generated from the resist underlayer film at baking process and to suppress aging and have high storage stability. A resist underlayer film-forming composition including an aryl sulfonic acid salt compound having a hydroxy group of Formula (1): | 12-31-2015 |
| 20150380252 | SIDEWALL IMAGE TEMPLATES FOR DIRECTED SELF-ASSEMBLY MATERIALS - In one example, a method includes forming a template having a plurality of elements above a process layer and forming spacers on sidewalls of the plurality of elements. Portions of the process layer are exposed between adjacent spacers. At least one of the plurality of elements is removed. A mask structure is formed from a directed self-assembly material over the exposed portions. The process layer is patterned using at least the mask structure as an etch mask. | 12-31-2015 |
| 20160005595 | Photoresist and Method of Manufacture - A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating additive in order to form a floating additive region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating additive may comprise an additive group which will decompose along with a fluorine unit bonded to the additive group which will decompose. Additionally, adhesion between the middle layer and the photoresist may be increased by applying an adhesion promotion layer using either a deposition process or phase separation, or a cross-linking may be performed between the middle layer and the photoresist. | 01-07-2016 |
| 20160005596 | ULTRA-CONFORMAL CARBON FILM DEPOSITION LAYER-BY-LAYER DEPOSITION OF CARBON-DOPED OXIDE FILMS - Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source: plasma-initiating gas: dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features. | 01-07-2016 |
| 20160005603 | PATTERN FORMING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film. | 01-07-2016 |
| 20160005625 | Hardmask composition and method of forming pattern using the hardmask composition - A hardmask composition includes a first material including one of an aromatic ring-containing monomer and a polymer containing a repeating unit including an aromatic ring-containing monomer, a second material including at least one of a hexagonal boron nitride and a precursor thereof, a chalcogenide-based material and a precursor thereof, and a two-dimensional carbon nanostructure and a precursor thereof, the two-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen, and a solvent. | 01-07-2016 |
| 20160013041 | Photoresist Layer and Method | 01-14-2016 |
| 20160013059 | Method for Overcoming Broken Line and Photoresist Scum Issues in Tri-Layer Photoresist Patterning | 01-14-2016 |
| 20160020111 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device according to an embodiment, a mask material comprising at least one layer of a hafnium silicate (HfSiOn (n is a positive number)) film is formed on a processing target film. The processing target material is processed using the mask material as a mask. The hafnium silicate film is located almost at a central portion of the mask material or between the central portion of the mask material and an upper surface thereof. | 01-21-2016 |
| 20160027645 | HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNING BY USING THE HARDMASK COMPOSITION - Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition. | 01-28-2016 |
| 20160027652 | SUBSTRATE MANUFACTURING METHOD AND SUBSTRATE MANUFACTURING APPARATUS - Provided are a substrate manufacturing method and a substrate manufacturing apparatus used therefor. The substrate manufacturing method includes providing a substrate having a mask film into a chamber. A plasma reaction is induced in the chamber. A first gas and a second gas are alternately provided into the chamber to etch the substrate. Each of the first and second gases is provided into the chamber at a stabilized feed pressure including a pressure fluctuation profile comprising a square wave shape. | 01-28-2016 |
| 20160027653 | COMPOUND FOR FORMING ORGANIC FILM, AND ORGANIC FILM COMPOSITION USING THE SAME, PROCESS FOR FORMING ORGANIC FILM, AND PATTERNING PROCESS - The invention provides a compound for forming an organic film having a partial structure represented by the following formula (ii), | 01-28-2016 |
| 20160027654 | SIMPLIFIED LITHO-ETCH-LITHO-ETCH PROCESS - Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several layers above the target etch layer. The compound pattern, made from multiple patterning steps, is later transferred in one set of operations through the stack to save process steps. | 01-28-2016 |
| 20160027655 | SINGLE PLATFORM, MULTIPLE CYCLE SPACER DEPOSITION AND ETCH - A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed. | 01-28-2016 |
| 20160035571 | Lithography Using High Selectivity Spacers for Pitch Reduction - A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. | 02-04-2016 |
| 20160035578 | Method Of Forming A Semiconductor Device Including A Pitch Multiplication - Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer. | 02-04-2016 |
| 20160035628 | PATTERN FORMATION METHOD - The present invention provides a pattern formation method of forming a pattern on a substrate by partially removing a line and space pattern formed on the substrate, comprising a first formation step of forming a first layer including a plurality of first openings on the line and space pattern, a second step of forming, on the first layer, a second layer including a second opening for exposing one or more first openings, which are used to partially remove the line and space pattern, among the plurality of first openings, and a removing step of partially removing the line and space pattern through the second opening and the first opening, wherein the plurality of first openings are located on a plurality of lines of the line and space pattern. | 02-04-2016 |
| 20160042950 | MULTI MATERIALS AND SELECTIVE REMOVAL ENABLED RESERVE TONE PROCESS - Embodiments described herein generally relate to methods for device patterning. In various embodiments, a plurality of protrusions and gaps are formed on a substrate, and each gap is formed between adjacent protrusions. Each protrusion includes a first line, a second line and a third line. The first and third lines include a first material, and the second lines include a second material that is different from the first material. A fourth line is deposited in each gap and the fourth line includes a third material that is different than the first and second materials. Because the first, second and third materials are different, one or more lines can be removed by selective etching while adjacent lines that are made of a different material may not be covered by a mask. The critical dimensions (CD) and the edge displacement errors (EPE) of the mask are increased. | 02-11-2016 |
| 20160043001 | FINE PATTERNING METHODS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask. | 02-11-2016 |
| 20160049289 | APPARATUS AND METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE - In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A removing unit removes the water repellent protective film with the convex pattern being left. | 02-18-2016 |
| 20160049306 | Methods of Manufacturing Semiconductor Device - The present inventive concept provides methods of manufacturing a semiconductor device including forming an inner mask layer on an etching target film, the inner mask layer including a polymer; forming a porous film on the etching target film, the porous film covering the inner mask layer; supplying an acid source to an outer surface area of the inner mask layer through the porous film; inducing a chemical reaction of the polymer included in the inner mask layer in the outer surface area by using the acid source; forming inner mask patterns by removing a chemically reacted portion of the inner mask layer; and etching the etching target film by using at least a portion of the porous film and the inner mask patterns as an etching mask. | 02-18-2016 |
| 20160049309 | Substrate Processing Method - A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process. According to another embodiment, the method includes providing a passivated substrate in a vacuum processing tool, the passivated substrate having a fluorine-based layer thereon that is effective for protecting the passivated substrate against oxidation by an oxidizing atmosphere, removing the fluorine-based layer from the passivated substrate using a microwave plasma process in the vacuum processing tool, thereby forming a clean substrate, and processing the clean substrate under vacuum conditions. | 02-18-2016 |
| 20160053087 | ULTRAVIOLET ABSORBER, COMPOSITION FOR FORMING A RESIST UNDER LAYER FILM, AND PATTERNING PROCESS - The present invention provides an ultraviolet absorber containing a compound represented by the formula (A-1), | 02-25-2016 |
| 20160064214 | TEMPLATE MANUFACTURING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a template manufacturing method of an embodiment, a first pattern is formed on a first template. A plurality of times of imprint processing using the first template is performed. A resist pattern is formed on a plurality of areas on a second template. At this time, processing of applying resist on the second template and processing of pressing the first pattern against the resist are repeatedly performed. | 03-03-2016 |
| 20160064235 | MASK PATTERN STRUCTURES, METHODS OF FORMING HOLES USING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes. | 03-03-2016 |
| 20160068709 | NOVOLAC RESIN-CONTAINING RESIST UNDERLAYER FILM-FORMING COMPOSITION USING BISPHENOL ALDEHYDE - Resist underlayer film-forming composition for forming resist underlayer film with high dry etching resistance, wiggling resistance and exerts good flattening property and embedding property for uneven parts, including resin obtained by reacting organic compound A including aromatic ring and aldehyde B having at least two aromatic hydrocarbon ring groups having phenolic hydroxy group and having structure wherein the aromatic hydrocarbon ring groups are bonded through tertiary carbon atom. The aldehyde B may be compound of Formula (1): | 03-10-2016 |
| 20160070838 | METHOD OF DECOMPOSING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout. | 03-10-2016 |
| 20160071736 | Methods of Fabricating Semiconductor Devices with Flattened Hardmask Layers - Methods of fabricating semiconductor devices may include forming a hardmask layer including a photosensitive hardmask material on lower structures. The hardmask layer may include a lower portion and an upper portion thereon. An exposing and developing process may be performed on the hardmask layer to remove the upper portion of the hardmask layer and thereby form a hardmask structure with a substantially flat top surface. | 03-10-2016 |
| 20160071957 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer above an etching object layer, the mask layer having a plurality of first layers, a plurality of spaces each provided between the first layers, and an opening part penetrating the first layers and communicating with the spaces; and dry etching the etching object layer of a different kind of material from a kind of material of the first layers using the mask layer. | 03-10-2016 |
| 20160079076 | PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a pattern forming method is provided. The method includes making a template touch resist material to form a first resist layer. The template has a recess/protrusion pattern. The method includes making a template touch resist material to form a second resist layer. The template has a recess/protrusion pattern. The method includes etching a processing object having the first resist layer and the second resist layer formed thereon. In forming the first resist layer, the template is kept at a position where a distance between a protrusion of the recess/protrusion pattern and the processing object takes on a first length. In forming the second resist layer, the template is kept at a position where a distance between a protrusion of the recess/protrusion pattern and the processing object takes on a second length. The second length is different from the first length. | 03-17-2016 |
| 20160086815 | FLUORINE-BASED HARDMASK REMOVAL - A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. | 03-24-2016 |
| 20160090449 | POLYMER, ORGANIC LAYER COMPOSITION, ORGANIC LAYER, AND METHOD OF FORMING PATTERNS - A polymer including a moiety represented by Chemical Formula 1, an organic layer composition including the polymer, an organic layer manufactured from the organic layer composition, and a method of forming patterns using the organic layer composition are provided. | 03-31-2016 |
| 20160096978 | COMPOSITION FOR FORMING A COATING TYPE BPSG FILM, SUBSTRATE, AND PATTERNING PROCESS - A composition for forming a coating type BPSG film, containing one or more silicic acid skeletal structures represented by formula (1), one or more phosphoric acid skeletal structures represented by formula (2), one or more boric acid skeletal structures represented by formula (3), and one or more silicon skeletal structures represented by formula (4), wherein the composition contains a coupling between units in formula (4). The composition is capable of forming a BPSG film that has excellent adhesiveness in fine patterning, can be easily wet etched by a removing liquid which does not cause damage to a semiconductor substrate and a coating type organic film or a CVD film mainly consisting of carbon which is required in the patterning process, can maintain the peelability even after dry etching, and can suppress generation of particles by forming it in the coating process. | 04-07-2016 |
| 20160099154 | MATERIAL DEPOSITION FOR HIGH ASPECT RATIO STRUCTURES - Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall. | 04-07-2016 |
| 20160104613 | Precise Critical Dimension Control Using Bilayer ALD - Methods for self-aligned multiple patterning including controlled slimming of features during spacer layer deposition. Multiple spacer layer deposition process conditions produce a balance between controlling the damage to the features and increasing production throughput. | 04-14-2016 |
| 20160104628 | Self-Aligned Patterning using Directed Self-Assembly of Block Copolymers - Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield. | 04-14-2016 |
| 20160111287 | METHOD FOR FORMING MULTI-LAYER FILM AND PATTERNING PROCESS - A method for forming multi-layer film on substrate, which includes steps ( | 04-21-2016 |
| 20160111295 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method includes the following steps. A substrate including a memory cell region and a peripheral region is provided, and a plurality of isolation structures are formed in the substrate. Each of the isolation structures contains an exposed portion protruding beyond the surface of the substrate. A first dielectric layer is formed on the substrate. A protective layer is formed on a sidewall of the exposed portion of each of the isolation structures. The first dielectric layer on the peripheral region is removed. A second dielectric layer is formed on the substrate of the peripheral region. | 04-21-2016 |
| 20160118247 | METHOD OF FORMING SEMICONDUCTOR DEVICE - Provided is a method of forming a semiconductor device. The method can include loading a semiconductor substrate into semiconductor equipment. A base layer can be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material. A first silicon layer can be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material. A first nitrided silicon layer can be formed by nitriding the first silicon layer using a first nitridation process. The semiconductor substrate having the first nitrided silicon layer can be unloaded from the semiconductor equipment. | 04-28-2016 |
| 20160118264 | ETCHING METHOD, ETCHING SOLUTION USED IN SAME, ETCHING SOLUTION KIT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE PRODUCT - There is provided an etching method of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing at least one specific metal element selected from nickel platinum (NiPt), titanium (Ti), nickel (Ni), and cobalt (Co), the method including: bringing an etching solution which contains an alkali compound into contact with the second layer and selectively removing the second layer. | 04-28-2016 |
| 20160118295 | Method for Forming Contact Vias - A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique. | 04-28-2016 |
| 20160126091 | CLEANING PROCESS FOR OXIDE - A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NH | 05-05-2016 |
| 20160139509 | RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING SUBSTITUTED CROSSLINKABLE COMPOUND - A resist underlayer film for use in lithography process which generates less sublimate, has excellent embeddability at the time of applying onto a substrate having a hole pattern, and has high dry etching resistance, wiggling resistance and heat resistance, etc. A resist underlayer film-forming composition including a resin and a crosslinkable compound of Formula (1) or Formula (2): | 05-19-2016 |
| 20160148805 | CYCLIC ALUMINUM OXYNITRIDE DEPOSITION - A process for depositing aluminum oxynitride (AlON) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to an oxygen precursor to form AlON. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to an oxygen precursor together constitute an AlON deposition cycle. A plurality of AlON deposition cycles may be performed to deposit an AlON film of a desired thickness. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma. | 05-26-2016 |
| 20160148815 | Method for Patterning a Plurality of Features For Fin-Like Field-Effect Transistor (FINFET) Devices - A method for patterning fins for FinFET devices are disclosed. The method includes forming elongated protrusions on a semiconductor substrate and forming a mask covering a first portion of the elongated protrusions. The method further includes forming a spacer surrounding the mask. The mask and the spacer together cover a second portion of the elongated protrusions. The method further includes removing a portion of the elongated protrusions not covered by the mask and the spacer. In an embodiment, an outer boundary of the spacer and the mask corresponds to an outer boundary of a non-rectangular pattern. | 05-26-2016 |
| 20160152771 | POLYMER, ORGANIC LAYER COMPOSITION, ORGANIC LAYER, AND METHOD OF FORMING PATTERNS | 06-02-2016 |
| 20160155632 | Anti-Reflective Layer and Method | 06-02-2016 |
| 20160155648 | Systems and Methods for In SITU Maintenance of a Thin Hardmask During an Etch Process | 06-02-2016 |
| 20160172187 | METHOD OF FORMING FINE PATTERN AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE METHOD | 06-16-2016 |
| 20160179010 | COATING LIQUID TO BE APPLIED TO RESIST PATTERN AND METHOD FOR FORMING REVERSE PATTERN | 06-23-2016 |
| 20160181113 | METHOD FOR FORMING STAIR-STEP STRUCTURES | 06-23-2016 |
| 20160187777 | COMPOSITION AND PATTERN-FORMING METHOD - A composition includes a metal compound and a solvent. The metal compound includes: a plurality of metal atoms of titanium, tantalum, zirconium, tungsten or a combination thereof; oxygen atoms each crosslinking the metal atoms; and polydentate ligands each coordinating to the metal atom. An absolute molecular weight of the metal compound as determined by static light scattering is no less than 8,000 and no greater than 50,000. A pattern-forming method includes applying the composition on an upper face side of a substrate to form an inorganic film. A resist pattern is formed on an upper face side of the inorganic film. The inorganic film and the substrate are dry-etched, by each separate etching operation, using the resist pattern as a mask such that the substrate has a pattern. | 06-30-2016 |
| 20160187782 | PHOTOLITHOGRAPHIC METHODS - Provided are photolithographic methods. The method comprise: (a) providing a semiconductor substrate comprising an organic layer to be etched; (b) applying a layer of a photoresist composition directly on the organic layer, wherein the photoresist composition comprises: a resin comprising an acid cleavable leaving group, the cleavage of which forms an acid group and/or an alcohol group; a photoacid generator; and a solvent; (c) exposing the photoresist layer to activating radiation through a patterned photomask; (d) heating the photoresist layer, wherein acid generated by the acid generator causes cleavage of the acid cleavable leaving group, thereby forming the acid group and/or the alcohol group; (d) developing the exposed photoresist composition layer with an organic solvent developer to form a negative resist pattern comprising the acid group and/or the alcohol group; (e) applying a silicon-containing composition over the resist pattern, wherein the composition comprises a silicon-containing polymer and a solvent and is free of crosslinkers; (f) rinsing residual silicon-containing composition from the substrate, leaving a portion of the silicon-containing polymer on a surface of the resist pattern; and (g) selectively etching the organic layer. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns. | 06-30-2016 |
| 20160189970 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure. | 06-30-2016 |
| 20160196975 | Method of Providing An Implanted Region In A Semiconductor Structure | 07-07-2016 |
| 20160203995 | INTEGRATING ATOMIC SCALE PROCESSES: ALD (ATOMIC LAYER DEPOSITION) AND ALE (ATOMIC LAYER ETCH) | 07-14-2016 |
| 20160204034 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF FINS AND AN ALIGNMENT/OVERLAY MARK | 07-14-2016 |
| 20160379820 | COMPOUND FINFET DEVICE INCLUDING OXIDIZED III-V FIN ISOLATOR - A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer. | 12-29-2016 |
| 20160379833 | METHOD FOR CLEANING PLASMA PROCESSING CHAMBER AND SUBSTRATE - A method for cleaning a plasma processing chamber is provided. The method includes introducing an organic gas into a plasma processing chamber. The organic gas includes an organic compound including carbon and hydrogen. The method includes generating an organic plasma by exciting the organic gas. The organic plasma reacts with metal compound residues over an interior surface of the plasma processing chamber to volatilize the metal compound residues into a gaseous metal compound. The method includes removing the gaseous metal compound from the plasma processing chamber. | 12-29-2016 |
| 20160379868 | METHOD AND APPARATUS FOR DEPOSITING A SILICON-CONTAINING FILM - A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a second surface of a substrate by supplying the silicon-containing gas to the substrate. A silicon component contained in the silicon-containing gas adsorbed on the first surface of the depression is partially etched by supplying an etching gas to the substrate. A silicon-containing film is deposited in the depression by supplying a reaction gas reactable with the silicon component to the substrate so as to produce a reaction product by causing the reaction gas to react with the silicon component left in the depression without being etched. | 12-29-2016 |
| 20170236719 | METHOD AND APPARATUS FOR MULTI-FILM DEPOSITION AND ETCHING IN A BATCH PROCESSING SYSTEM | 08-17-2017 |
| 20170236720 | PATTERN FORMING METHOD | 08-17-2017 |
| 20190146341 | POSITIVE PHOTORESIST COMPOSITION, VIA-FORMING METHOD, DISPLAY SUBSTRATE AND DISPLAY DEVICE | 05-16-2019 |
| 20190148146 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE | 05-16-2019 |
| 20190148147 | FINE LINE PATTERNING METHODS | 05-16-2019 |
