Entries |
Document | Title | Date |
20080200034 | METHOD TO REMOVE BEOL SACRIFICIAL MATERIALS AND CHEMICAL RESIDUES BY IRRADIATION - A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability. | 08-21-2008 |
20080214010 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND PATTERN FORMATION MOLD - According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by sequentially transferring the pattern for each shot, wherein one of a dicing region and a monitor pattern formation region of the substrate to be processed is coated with the imprinting material. | 09-04-2008 |
20080233752 | METHOD FOR MANUFACTURING FLOATING STRUCTURE OF MICROELECTROMECHANICAL SYSTEM - Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate. | 09-25-2008 |
20080233753 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR MANUFACTURING EQUIPMENT - A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing. | 09-25-2008 |
20080242095 | Method for forming trench in semiconductor device - A method for fabricating a trench in a semiconductor device includes forming a mask pattern over a substrate, and etching the substrate to form a trench with a vertical profile, the etching performed at an etching rate of approximately 40 A/sec or less using an etching gas including a gas generating polymers | 10-02-2008 |
20080254631 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film. | 10-16-2008 |
20080280445 | Manufacturing method of nitride semiconductor device and nitride semiconductor device - Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed. | 11-13-2008 |
20080305637 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device which includes sequentially forming a non-etching layer and a sacrificial layer on a semiconductor substrate; and then forming a plurality of photo-resist layer patterns having a plurality of openings exposing the sacrificial layer; and then forming a plurality of first pattern grooves in the sacrificial layer etching the exposed sacrificial layer using the photo-resist patterns as an etching barrier; removing the photo-resist layer; and then forming an oxidation layer having a plurality of second pattern grooves on the sacrificial layer and in the first pattern grooves by performing a thermal oxidation process on the sacrificial layer; and then forming a plurality of first through-holes exposing the non-etching layer by completely removing the sacrificial layer remaining in oxidation layer; and then forming a plurality of patterns in the non-etching layer by etching the exposed portions of the non-etching layer using the oxidation layer as an etching barrier. | 12-11-2008 |
20080305638 | Coating compositions for use in forming patterns and methods of forming patterns - A coating composition for forming etch mask patterns may include a polymer and an organic solvent. The polymer may have an aromatic ring substituted by a vinyl ether functional group. The polymer may be, for example, a Novolak resin partially substituted by a vinyl ether functional group or poly(hydroxystyrene) partially substituted by a vinyl ether functional group. | 12-11-2008 |
20080311755 | Method for treating a dielectric film to reduce damage - A method of treating a dielectric layer on a substrate is described. The method comprises forming the dielectric layer on the substrate, wherein the dielectric layer comprises a dielectric constant value less than the dielectric constant of SiO | 12-18-2008 |
20080311756 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 12-18-2008 |
20090017628 | SPACER LITHOGRAPHY - Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer. Embodiments include forming the first mask pattern from a photoresist material capable of generating an acid, depositing a cross-linkable material comprising a material capable of undergoing a cross-linking reaction in the presence of an acid, and removing portions of the non-cross-linked layer and cross-linked spacer from the upper surface of the first mask pattern before removing the remaining portions of the first mask pattern and remaining noncross-linked layer. | 01-15-2009 |
20090017629 | METHOD OF FORMING CONTACT STRUCTURE WITH CONTACT SPACER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a contact structure with a contact spacer and a method of fabricating a semiconductor device using the same. In the method of forming a contact structure, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is patterned, thereby forming a contact hole for exposing a predetermined region of the semiconductor substrate. A contact spacer is formed on a sidewall of the contact hole using a deposition method having an inclined deposition direction with respect to a main surface of the semiconductor substrate. The deposition direction may be set between the main surface and a normal with respect to the main surface. Further, there is provided a method of fabricating a semiconductor device using the method of forming the contact structure. | 01-15-2009 |
20090035943 | Method of Fabricating for Semiconductor Device Fabrication - A method of fabricating a semiconductor device, includes providing a substrate having at least one first portion and at least one second portion. The first portion includes a semiconductor material and the second portion includes an electrically isolating material. An etching step is performed using an etchant in order to at least partially remove the first and the second portions. The etchant includes a NF | 02-05-2009 |
20090042396 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELECTIVE ETCHING OF AN ACTIVE REGION THROUGH A HARDMASK - A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench. | 02-12-2009 |
20090053897 | Method of fabricating a circuit board - A method of fabricating a circuit board is disclosed. The method includes: forming a trench in a base and forming an electroless plating layer over a surface of the base and an inner surface of the trench; providing a carrier, on one side of which a plating resist is coated; forming a transcribed part on the surface of the base by stacking the carrier onto the base and transcribing the plating resist onto the surface of the base; forming a pattern in the trench by plating, and removing the transcribed part; and removing portions of the electroless plating layer and the pattern. This method makes it possible to form circuit patterns with a uniform thickness and to provide high workability. | 02-26-2009 |
20090061634 | Method for metallizing a pattern in a dielectric film - A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO | 03-05-2009 |
20090068843 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 03-12-2009 |
20090081873 | Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations - Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates. | 03-26-2009 |
20090163027 | METHOD FOR FABRICATING VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE - A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench. | 06-25-2009 |
20090176374 | PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND STORAGE MEDIUM - A pattern forming method includes (a) forming pairs of deposits on sidewalls of mask portions in first mask patterns by forming a thin film thereon, etching it to leave deposits, and exposing a top surface of a second-layer film between the deposits; (b) forming second mask patterns formed of mask portions corresponding to the deposits by removing the mask portion, plasma etching the second-layer film, and removing the deposits; (c) forming a thin film thereon, and etching it to leave deposits on sidewalls of mask portions facing each other and to expose a third-layer film between the deposits while leaving deposits between adjacent mask portions; and (d) forming grooves thereon by removing the second mask portion, and etching off the third-layer film. | 07-09-2009 |
20090253266 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-08-2009 |
20090269931 | ELECTRONIC DEVICE AND METHOD FOR MAKING THE SAME - The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer | 10-29-2009 |
20090275202 | SILICON STRUCTURE HAVING AN OPENING WHICH HAS A HIGH ASPECT RATIO, METHOD FOR MANUFACTURING THE SAME, SYSTEM FOR MANUFACTURING THE SAME, AND PROGRAM FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING ETCHING MASK FOR THE SILICON STRUCTURE - Provided are a silicon structure having an opening which has a high aspect ratio and an etching mask for forming the silicon structure. A step of performing hole etching or trench etching of silicon so as to substantially expose a portion of at least a bottom surface of etched silicon and a step of forming a silicon oxide film by a CVD method on the silicon structure formed by the step of performing the hole etching or the trench etching are conducted. Thereafter, a step of exposing the formed silicon oxide film to a gas containing a hydrogen fluoride vapor is conducted. Further, the above-mentioned step of performing the hole etching or the trench etching is conducted again. | 11-05-2009 |
20090305507 | Method of processing solid surface with gas cluster ion beam - A solid surface is processed while corner portions of a relief structure are protected from deformation. A method of processing a solid surface with a gas cluster ion beam includes a cluster protection layer formation step of forming, on the solid surface, a relief structure having protrusions with a cluster protection layer formed to cover an upper part thereof and recesses without the cluster protection layer; an irradiation step of emitting a gas cluster ion beam onto the solid surface having the relief structure formed in the cluster protection layer formation step; and a removal step of removing the cluster protection layer. A thickness T of the cluster protection layer satisfies | 12-10-2009 |
20100029083 | Method for Forming Laterally Extending Dielectric Layer in a Trench-Gate FET - A field effect transistor (FET) is formed as follows. A trench is formed in a silicon region. An oxidation barrier layer is formed over a surface of the silicon region adjacent the trench and along the trench sidewalls and bottom. A protective layer is formed over the oxidation barrier layer inside and outside the trench. The protective layer is partially removed such that a portion of the oxidation barrier layer extending at least along the trench bottom becomes exposed and portions of the oxidation barrier layer extending over the surface of the silicon region adjacent the trench remain covered by remaining portions of the protective layer. | 02-04-2010 |
20100055914 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths. | 03-04-2010 |
20100112818 | METHOD FOR FORMING HIGH DENSITY PATTERNS - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 05-06-2010 |
20100120252 | Method of Positioning Patterns from Block Copolymer Self-Assembly - A method of controlling both alignment and registration (lateral position) of lamellae formed from self-assembly of block copolymers, the method comprising the steps of obtaining a substrate having an energetically neutral surface layer comprising a first topographic “phase pinning” pattern and a second topographic “guiding” pattern; obtaining a self-assembling di-block copolymer; coating the self-assembling di-block copolymer on the energetically neutral surface to obtain a coated substrate; and annealing the coated substrate to obtain micro-domains of the di-block copolymer. | 05-13-2010 |
20100144154 | Method of manufacturing semiconductor device, and etching apparatus - Aimed at suppressing roughening in a circumferential portion of a layer to be etched in the process of removing a hard mask formed thereon, an etching apparatus of the present invention has a process chamber, an electrode, a stage, and a shadow ring, wherein the process chamber allows an etching gas to be introduced therein; the electrode is disposed in the process chamber, and is used for generating plasma by ionizing the etching gas; the stage is disposed in the process chamber, onto which a substrate is disposed; the shadow ring has an irregular pattern on the inner circumferential edge thereof, and is disposed in the process chamber and placed above the stage | 06-10-2010 |
20100144155 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device comprising: forming a first hard mask layer and a second hard mask layer on the layer to be etched (S | 06-10-2010 |
20100159702 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed. | 06-24-2010 |
20100167550 | METHOD FOR MANUFACTURING SEMICONDUCTOR - A method for manufacturing a semiconductor includes forming an active region for an ESD device, an active region for a first polygate and the semiconductor, and a second polygate having a form of a blanket trench on a substrate, forming an interlayer dielectric layer including first and second insulating on the substrate, planarizing the interlayer dielectric layer, forming a contact pattern to open a portion of the interlayer dielectric layer over the first polygate, forming a first polygate trench by performing a first etch process with respect to the second insulating layer below the contact pattern, and performing a second etch process to remove the first insulating layer inside the first polygate trench and to remove the first insulating layer over the active region of the semiconductor other than the second polygate. | 07-01-2010 |
20100178771 | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks - Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers. | 07-15-2010 |
20100190345 | Selective Etch-Back Process for Semiconductor Devices - A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH | 07-29-2010 |
20100197140 | ANGLED-WEDGE CHROME-FACE WALL FOR INTENSITY BALANCE OF ALTERNATING PHASE SHIFT MASK - A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees with the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist. | 08-05-2010 |
20100216311 | Trench forming method - A trench forming method for forming trenches without creating gouges at the boundary between a masking oxide film and a semiconductor layer and at the boundary between an oxide film insulating layer and the semiconductor layer, includes at least three etching steps each using, as the etching gas, one of at least two types of etching gases that respectively contain different components. | 08-26-2010 |
20100233881 | METHOD OF MANUFACTURING SUPPORTING STRUCTURES FOR STACK CAPACITOR IN SEMICONDUCTOR DEVICE - A method of manufacturing a supporting structure for a stack capacitor in a semiconductor device is provided. The method includes the following steps. The first step is providing a multi-layer structure including an etching stop layer, a silicon oxide layer and a silicon nitride layer. The second step is etching the silicon nitride layer and the silicon oxide layer to form a plurality of filling recesses in the silicon oxide layer, in which each the filling recess has a lateral surface and a bottom surface. The third step is forming a protecting layer at each the lateral surface. The fourth step is etching the silicon oxide layer to expose the etching stop layer. The fifth step is removing the protecting layer on the each lateral surface, thereby forming the supporting structure. | 09-16-2010 |
20100248482 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, TEMPLATE, AND METHOD OF CREATING PATTERN INSPECTION DATA - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes mask layer on a processing target, pressing a template having a pattern having closed loop structure against the mask layer via an imprint material to solidify the imprint material, etching the mask layer by using the imprint material to form a mask, removing a part of the pattern having the closed loop of the mask, and etching the processing target by the mask including the pattern, the part of which is removed. | 09-30-2010 |
20100248483 | METHOD OF PRODUCING SEMICONDUCTOR ELEMENT - A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed. | 09-30-2010 |
20100248484 | Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby - Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. | 09-30-2010 |
20110021028 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING AZEOTROPIC DRYING PROCESSES - Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the steps of providing a partially-completed semiconductor device including a first feature formed in a porous material, wet cleaning the partially-completed semiconductor device with an aqueous cleaning solvent, exposing the partially-completed semiconductor device to a liquid chemical that forms an azeotropic mixture with water, and inducing evaporation of the azeotropic mixture to remove residual water from within the porous material absorbed during the wet cleaning step. | 01-27-2011 |
20110039413 | METHOD FOR FORMING TRENCHES HAVING DIFFERENT WIDTHS AND THE SAME DEPTH - A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred. | 02-17-2011 |
20110111598 | METHOD FOR PREPARING PATTERNED SUBSTRATE BY USING NANO- OR MICRO- PARTICLES - A method for preparing patterned substrate by using nano- or micro-particles is disclosed, which comprises the following steps: (A) providing a substrate with a photoresist layer formed thereon; (B) coating a surface of the photoresist layer with plural nano- or micro-particles, to form a particle layer; (C) exposing and developing the photoresist layer to obtain a patterned photoresist layer; and (D) removing the particle layer. In addition, after the particle layer is removed, the method of the present invention further comprises: (E1) using the patterned photoresist layer as an etching template to etch the substrate; and (E2) removing the patterned photoresist layer to obtain a patterned substrate with plural cavities formed thereon. | 05-12-2011 |
20110143542 | Method to remove capping layer of insulation dielectric in interconnect structures - A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process. | 06-16-2011 |
20110143543 | Method of Forming Capacitors, and Methods of Utilizing Silicon Dioxide-Containing Masking Structures - Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water. | 06-16-2011 |
20110201203 | METHODS OF FORMING A HOLE HAVING A VERTICAL PROFILE AND SEMICONDUCTOR DEVICES HAVING A VERTICAL HOLE - In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F | 08-18-2011 |
20110223768 | Method for Forming Contact Opening - A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas. | 09-15-2011 |
20120028472 | Method of Controlling Critical Dimensions of Vias in a Metallization System of a Semiconductor Device During Silicon-ARC Etch - When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts. | 02-02-2012 |
20120034784 | Methods of Forming Fine Patterns in Semiconductor Devices - Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure. | 02-09-2012 |
20120064722 | ETCHING SOLUTION AND TRENCH ISOLATION STRUCTURE-FORMATION PROCESS EMPOLYING THE SAME - The present invention provides an etching solution less affected by trench structures and also provides an isolation structure-formation process employing the solution. The etching solution contains hydrofluoric acid and an organic solvent. The organic solvent has a δH value defined by Hansen solubility parameters in the range of 4 to 12 inclusive and the saturation solubility thereof in water is 5 wt % or more at 20° C. This solution can be adopted instead of known etching solutions used in conventional production processes of semiconductor elements. | 03-15-2012 |
20120094496 | Process For Locally Dissolving The Oxide Layer In A Semiconductor-On-Insulator Type Structure - A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer. | 04-19-2012 |
20120129349 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns. | 05-24-2012 |
20120142192 | OXIDE-RICH LINER LAYER FOR FLOWABLE CVD GAPFILL - The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion. | 06-07-2012 |
20120149204 | METHOD OF FORMING VIA HOLES - A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections. | 06-14-2012 |
20120178260 | MULTI-LAYER CHIP CARRIER AND PROCESS FOR MAKING - Provided are processes for making multi-layer chip carriers comprising an asymmetric cross-linked polymeric dielectric film. | 07-12-2012 |
20120190203 | METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 07-26-2012 |
20120208366 | PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER - A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch. | 08-16-2012 |
20120214309 | METHOD AND APPARATUS OF FABRICATING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface. | 08-23-2012 |
20120238098 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device for forming a deep hole in a substrate by using a photoresist film formed on the substrate includes a positioning step of positioning a substrate inside an etching chamber, the substrate having a photoresist film including an opening part formed thereon, a first etching step of performing plasma etching on the substrate positioned inside the etching chamber by using a first mixed gas including at least SiF | 09-20-2012 |
20120244709 | PLASMA ETCHING METHOD AND STORAGE MEDIUM - Disclosed is a plasma etching method capable of carrying out an etching process while preventing an etching shape defect such as a bowing from occurring. The plasma etching method includes etching an organic film formed on the substrate to a middle depth using an inorganic film as a mask by generating plasma between an upper electrode a surface of which is formed with a silicon containing material and a lower electrode where a substrate to be processed is placed thereon in a processing chamber; forming a protective film including the silicon containing material of the upper electrode on a side wall of an etching region formed from the etching process by applying a negative DC voltage on the upper electrode while generating the plasma; and continuing the etching process using the plasma thereby etching the organic film to a predetermined depth. | 09-27-2012 |
20120270404 | METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES - The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained. | 10-25-2012 |
20120302067 | Methods of Etching Trenches into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF | 11-29-2012 |
20120329281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A shape defect in a transfer pattern formed over the major surface of a substrate is prevented by using an immersion exposure method. When exposure light is radiated onto a resist, immersion water is held in a first immersion area between each of the lower surfaces of an optical element of a projection optical system and a nozzle portion, and a resist; and when a focus, optical system alignment, or the like, is regulated, the immersion water is held in a second immersion area between each of the lower surfaces of the optical element of the projection optical system and the nozzle portion, and the upper surface of a measurement stage. A transverse spread of the immersion water held in the first immersion area is made smaller than that of the immersion water held in the second immersion area. | 12-27-2012 |
20130017684 | PROCESS OF FORMING SLIT IN SUBSTRATEAANM Wang; Wen-ChiehAACI Taoyuan CountyAACO TWAAGP Wang; Wen-Chieh Taoyuan County TWAANM Chen; Yi-NanAACI Taipei CityAACO TWAAGP Chen; Yi-Nan Taipei City TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl | 01-17-2013 |
20130034963 | METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICE - Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask. | 02-07-2013 |
20130045602 | METHOD FOR FORMING CONTACT HOLES - A method for forming contact holes is applied in a transistor array substrate. The transistor array substrate includes first contact pads, second contact pads located over the first contact pads, a first insulation layer covering the first contact pads, and a second insulation layer covering the second contact pads. Firstly, a photoresist pattern layer having recesses and first openings is formed on the second insulation layer. The first openings expose the second insulation layer partially. Then, the first insulation layer and the second insulation layer inside the first openings are removed partially, to expose the first contact pads. Then, the thickness of the photoresist pattern layer is reduced, so that the recesses form a plurality of second openings which expose the second insulation layer partially. After that, a part of the second insulation layer which is located inside the second openings is removed, to expose the second contact pads. | 02-21-2013 |
20130109185 | METHOD OF FABRICATING MINIATURIZED SEMICONDUCTOR OR OTHER DEVICE | 05-02-2013 |
20130178068 | DUAL DAMASCENE PROCESS AND APPARATUS - A method comprising providing at least one dielectric layer above a semiconductor substrate, the at least one dielectric layer having a top surface and a bottom surface; forming a photoresist layer on the top surface of the at least one dielectric layer; providing a single photomask having at least one first pattern corresponding to a conductive via and at least one second pattern corresponding to a conductive trace; patterning the photoresist layer using the single photomask, for forming a trench in the photoresist corresponding to the conductive trace and an opening in a bottom surface of the trench corresponding to the via with a single photo exposure step; and etching the dielectric through the photoresist layer to form the trench and via therein. This application also relates to photomasks for use in the methods of this application. | 07-11-2013 |
20130189846 | Methods of Forming Patterns - Some embodiments include methods in which photolithographically-patterned photoresist features are used as templates during formation of a series of annular structures. The annular structures have linear segments. The linear segments are within a pattern having a pitch which is less than or equal to about half of a pitch of a pattern containing the photoresist features. An expanse of photoresist is formed across the annular structures. The expanse is photolithographically patterned to form chop patterns over ends of the annular structures, and to form at least one opening over at least one of the linear segments. The annular structures are etched while using the patterned photoresist expanse as a mask. In some embodiments, an opening in a photoresist expanse aligns to an edge of a linear segment through scum generated during photolithographic patterning of the photoresist expanse. | 07-25-2013 |
20130210232 | CUT-MASK PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer. | 08-15-2013 |
20130237060 | FORMATION OF SiOCl-CONTAINING LAYER ON EXPOSED LOW-K SURFACES TO REDUCE LOW-K DAMAGE - A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature. | 09-12-2013 |
20130302989 | REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES - Generally, the present disclosure is directed to methods for reducing line edge roughness in hardmask integration schemes that are used for forming interconnect structures, such as conductive lines and the like. One illustrative method disclosed herein includes, among other things, forming a metal hardmask above a dielectric material and forming a first opening in the metal hardmask, the first opening comprising sidewalls, and the sidewalls having a surface roughness. The disclosed method further includes reducing the surface roughness of the sidewalls, and using the first opening with the sidewalls of reduced surface roughness to form a second opening in the dielectric material. | 11-14-2013 |
20130309870 | METHODS OF REDUCING SUBSTRATE DISLOCATION DURING GAPFILL PROCESSING - Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them. | 11-21-2013 |
20130344699 | SIDEWALL PROTECTION OF LOW-K MATERIAL DURING ETCHING AND ASHING - A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process. | 12-26-2013 |
20140024218 | Integrated Circuit Method With Triple Patterning - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features. | 01-23-2014 |
20140038417 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess. | 02-06-2014 |
20140045335 | PHOTO LITHOGRAPHIC RINSE SOLUTION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A photolithographic rinse solution includes deionized water, and a surfactant, the surfactant including a cyclic amine group and at least one non-amine cyclic group joined to or fused with the cyclic amine group, wherein the cyclic amine group includes a ring having a carbon number of 4 to 6, and the non-amine cyclic group includes a ring having a carbon number of 5 to 8. | 02-13-2014 |
20140099793 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask. | 04-10-2014 |
20140148012 | TONE INVERSION OF SELF-ASSEMBLED SELF-ALIGNED STRUCTURES - A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch. | 05-29-2014 |
20140154886 | Methods of Processing Semiconductor Substrates In Forming Scribe Line Alignment Marks - A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning. | 06-05-2014 |
20140199846 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The method may comprise: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modifying layer in the plurality of first openings; and etching the opening modifying layer until the substrate is exposed, resulting in a plurality of second openings, wherein the second openings have a depth-to-width ratio greater than that of the first openings. In this way, a deep hole with a relatively large dimension can be formed in silicon oxide by conventional photolithography processes. After that, a film of silicon nitride can be deposited into the hole to achieve a desired CD, and then etched with the fluorocarbon gas(es) to implement an arrangement with a relatively great depth-to-width ratio. | 07-17-2014 |
20140206195 | PROCESS FOR REMOVING CARBON MATERIAL FROM SUBSTRATES - A method of removing carbon materials, preferably amorphous carbon, from a substrate includes dispensing a liquid sulfuric acid composition including sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially uniformly coat the carbon material coated substrate. The liquid sulfuric acid composition is exposed to water vapor in an amount effective to increase the temperature of the liquid sulfuric acid composition above the temperature of the liquid sulfuric acid composition prior to exposure to the water vapor. In preferred embodiments, amorphous carbon is selectively removed as compared to a silicon oxide (e.g., silicon dioxide) and/or silicon nitride. | 07-24-2014 |
20140273464 | Method of Fabricating a FinFET Device - A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins. | 09-18-2014 |
20140302678 | INTERNAL PLASMA GRID APPLICATIONS FOR SEMICONDUCTOR FABRICATION - The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes. | 10-09-2014 |
20140349486 | Methods of Utilizing Block Copolymer to Form Patterns - Some embodiments include methods of forming patterns utilizing copolymer. A main body of copolymer may be formed across a substrate, and self-assembly of the copolymer may be induced to form a pattern of structures across the substrate. A uniform thickness throughout the main body of the copolymer may be maintained during the inducement of the self-assembly. In some embodiments, the uniform thickness may be maintained through utilization of a wall surrounding the main body of copolymer to impede dispersal of the copolymer from the main body. In some embodiments, the uniform thickness may be maintained through utilization of a volume of copolymer in fluid communication with the main body of copolymer. | 11-27-2014 |
20150024601 | METHOD OF MANUFACTURING SI-BASED HIGH-MOBILITY GROUP III-V/GE CHANNEL CMOS - A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO | 01-22-2015 |
20150037980 | SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER - Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided. | 02-05-2015 |
20150064915 | METHODS FOR PROVIDING SPACED LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method is disclosed for forming a row of mutually spaced lithography features on a substrate, such as contact electrodes for a NAND device. The method involves forming and/or using a narrow slot over the substrate defined between the edge of a hard mask layer and a side wall of a trench in a resist layer overlying the edge and the substrate. A self-assemblable block copolymer is deposited and ordered in the trench for use as a further resist for patterning the substrate along the slot. The method allows for a sub-resolution contact array to be formed using UV lithography by overlapping the trench with the hard mask edge to provide the narrow slot in which the contact electrodes may be formed. | 03-05-2015 |
20150072528 | Hard Mask Edge Cover Scheme - A method includes forming at least one trench in a dielectric layer using a hard mask. An edge cover layer is formed over the hard mask. The at least one trench is filled with a metal layer. | 03-12-2015 |
20150079791 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer. | 03-19-2015 |
20150104943 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable material. The first dielectric region is cured. A portion of the second dielectric region is etched to form an opening and leave a remaining portion of the second dielectric region. After the etching step, the remaining portion of the second dielectric region is cured. | 04-16-2015 |
20150140823 | SILICON ETCHING METHOD - A silicon etching method of etching a silicon substrate to form silicon trenches having different width dimensions includes: S | 05-21-2015 |
20150318184 | DIRECTIONAL CHEMICAL OXIDE ETCH TECHNIQUE - A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench. | 11-05-2015 |
20150340243 | PLASMA ETCHING METHOD - In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order, the etching mask having an etching pattern formed thereon and being formed of polysilicon, a silicon-containing deposit is deposited on a surface of the etching mask using a plasma generated from a processing gas, while applying a negative direct current voltage to an upper electrode formed of silicon. Furthermore, in the plasma etching method, the silicon oxide film is etched using plasma generated from a first CF-based gas using, as a mask, the etching mask having the silicon-containing deposit deposited thereon. | 11-26-2015 |
20150357203 | PATTERNING METHOD AND PATTERNING APPARATUS - A patterning method is described. A patterned mask layer is formed on a material layer, having therein a first opening exposing a portion of the material layer. A pre-treatment process is performed to modify the material layer exposed in the first opening and form a modified region therein. An etching process is performed to remove the material layer in the modified region at least and form a second opening in the material layer. | 12-10-2015 |
20160049305 | METHOD FOR CRITICAL DIMENSION REDUCTION USING CONFORMAL CARBON FILMS - Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded. | 02-18-2016 |
20160064216 | PATTERN FORMATION METHOD - According to an embodiment, a guide pattern having a first opening pattern and a second opening pattern shallower than the first opening pattern, is formed on a film to be processed. A directed self-assembly material is set into the first and second opening patterns. The directed self-assembly material is phase-separated into first and second phases in the first and second opening patterns. A third opening pattern is formed by removing the first phase. The third opening pattern in the second opening pattern is eliminated, and the second and third opening patterns are transferred to the film to be processed, by one etching to be processed from the tops of the second and third opening patterns. | 03-03-2016 |
20160064246 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF PROCESSING A SUBSTRATE - A method of processing a substrate is provided. A substrate is placed on a turntable provided in a process chamber. The process chamber includes a process area for supplying an etching gas and a purge area for supplying a purge gas. The process area and the purge area are arranged along a rotational direction of the turntable and divided from each other. The etching gas is supplied into the process area. The purge gas is supplied into the purge area. The turntable rotates to cause the substrate placed on the turntable to pass through the process area and the purge area once per revolution, respectively. A film deposited on a surface of the substrate is etched when the substrate passes the process are. An etching rate of the etching or a surface roughness of the film is controlled by changing a rotational speed of the turntable. | 03-03-2016 |
20160064247 | ETCHING METHOD - A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride includes a first step of exposing a target object having the first region and the second region to a plasma of a processing gas containing a fluorocarbon gas, etching the first region, and forming a deposit containing fluorocarbon on the first region and the second region. The method further includes a second step of etching the first region by a radical of the fluorocarbon contained in the deposit. In the first step, the plasma is generated by a high frequency power supplied in a pulsed manner. Further, the first step and the second step are repeated alternately. | 03-03-2016 |
20160071740 | PATTERN FORMING METHOD - A pattern forming method according to the present embodiment forms a self-assembly material layer including a liquid-crystal material in at least one block thereof on a surface of a base material. An external field in a first region of the self-assembly material layer is applied locally, the first region of the self-assembly material layer is rubbed locally, or a film thickness of the first region of the self-assembly material layer is changed locally. The self-assembly material layer is phase-separated. | 03-10-2016 |
20160086845 | A METHOD FOR PROCESSING AN INNER WALL SURFACE OF A MICRO VACANCY - There is provided a method for processing an inner wall surface of a micro vacancy, capable of reliably etching or cleaning even if the hole provided to the substrate to be processed is narrow and deep. The substrate has a surface and a micro vacancy with an opening on the surface. An aspect ratio of the micro vacancy being at least 5, or the aspect ratio being less than 5 and a ratio of a micro vacancy volume to a surface area of the opening being at least 3. The micro vacancy is exposed to an atmosphere for forming a silicon oxide film so as to form a silicon oxide film on the inner wall surface of the micro vacancy. Subsequently a processing solution with a wettability with respect to silicon oxide is introduced into the micro vacancy so as to perform processing of the inner wall surface. | 03-24-2016 |
20160204220 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE | 07-14-2016 |