| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438695000 | Simultaneous etching and coating | 34 |
| 20080286972 | ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST - A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks. | 11-20-2008 |
| 20080318429 | Fabrication method of semiconductor integrated circuit device - An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A cleaning gas converted into plasma in a plasma gas generator is introduced into a chamber to remove an unnecessary film deposited over the interior wall of the chamber or electrode. By an RF power source adjusted to low output from the film formation time, a high frequency voltage is applied to a lower electrode and an upper electrode. This voltage is detected by an RF sensor and amplified by an electronic module. The voltage thus amplified by the electronic module is input to a termination controller. The termination controller automatically judges the termination of cleaning when the voltage thus input becomes substantially constant at a predetermined voltage or greater. | 12-25-2008 |
| 20090191711 | HARDMASK OPEN PROCESS WITH ENHANCED CD SPACE SHRINK AND REDUCTION - Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may be varied to meet different process requirements. In one embodiment, the process gently etches the substrate while shrinking critical dimension of the structures formed within the substrate. The dimension of the structures may be shank by coating a photoresist like polymer to sidewalls of the formed structure, but substantially no polymer accumulation on the bottom surface of the formed structure on the substrate. The embodiments described herein also provide high selectivity in between each layers formed on the substrate during the fabricating process and preserving a good control of profile formed within the structure. | 07-30-2009 |
| 20100105208 | SILICON ETCH WITH PASSIVATION USING CHEMICAL VAPOR DEPOSITION - A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped. | 04-29-2010 |
| 20100167549 | SUBSTRATE PROCESSING METHOD - In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O | 07-01-2010 |
| 20110151670 | METHOD OF CONTROLLING ETCH MICROLOADING FOR A TUNGSTEN-CONTAINING LAYER - A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A plasma is formed from the provided etch gas. A tungsten containing layer patterned with wide and narrow features is etched with the provided plasma. | 06-23-2011 |
| 20110151671 | METHOD OF TEXTURING SEMICONDUCTOR SUBSTRATES - Semiconductor substrates are cleaned and subsequently oxidized. After the semiconductor is oxidized it is textured to reduce incident light reflectance. The textured semiconductors can be used in the manufacture of photovoltaic devices. | 06-23-2011 |
| 20110318930 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate. | 12-29-2011 |
| 20120100720 | SILICON ETCH WITH PASSIVATION USING PLASMA ENHANCED OXIDATION - A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor. | 04-26-2012 |
| 20130034961 | Plasma Etching Method - A plasma etching method capable of forming a tapering etching structure having a smooth surface is provided. A fluorine-containing gas and a nitrogen gas are used and plasma is generated from these gases simultaneously, and a silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma and then a fluorine-containing gas and an oxygen-containing gas are used and plasma is generated from these gases simultaneously, and the silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma generated from the oxygen-containing gas, thereby forming a tapering etching structure H having a wide top opening width and a narrow bottom width. | 02-07-2013 |
| 20130109184 | PLASMA ETCHING METHOD | 05-02-2013 |
| 20130149867 | SUBSTRATE PROCESSING SYSTEM, GAS SUPPLY UNIT, METHOD OF SUBSTRATE PROCESSING, COMPUTER PROGRAM, AND STORAGE MEDIUM - The present invention is to provide a technique for uniformly processing a substrate surface in the process of processing a substrate by supplying a gas. The inside of a shower head having gas-jetting pores for supplying a gas to a substrate is partitioned into a center section from which a gas is supplied to the center portion of a substrate, and a peripheral section from which a gas is supplied to the peripheral portion of the substrate, and the same process gas is supplied to the substrate from these two sections at flow rates separately regulated. The distance from the center of the center section of the gas supply unit to the outermost gas-jetting pores in the center section is set 53% or more of the radius of the substrate. Moreover, an additional gas is further supplied to the peripheral portion of the substrate. | 06-13-2013 |
| 20140363975 | SUBSTRATE ETCHING METHOD AND SUBSTRATE PROCESSING DEVICE - A substrate etching method and a substrate processing device, the substrate etching method includes: S1: placing a substrate to be processed into a reaction chamber; S2: supplying etching gas into the reaction chamber; S3: turning on an excitation power supply to generate plasma in the reaction chamber; S4: turning on a bias power supply to apply bias power to the substrate; S5: turning off the bias power supply, and meanwhile, starting to supply deposition gas into the reaction chamber; S6: stopping supply of the deposition gas into the reaction chamber, and meanwhile, turning on the bias power supply; S7: repeating steps S5-S6, until the etching process is completed. In the whole etching process, the etching operation is always performed, and the deposition operation is performed sometimes. Therefore, during the deposition operation, the plasma in the reaction chamber can etch away at least a part of deposited polymers formed by the deposition operation on a sidewall of an etched section, so that the sidewall of the etched section of the substrate is smooth. | 12-11-2014 |
| 20150104942 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus. | 04-16-2015 |
| 20150376498 | LOW-[HF] ROOM TEMPERATURE WET CHEMICAL GROWTH (RTWCG) CHEMICAL FORMULATION - This present invention relates to a Room Temperature Wet Chemical Growth (RTWCG) formulations, methods and processes. In one embodiment, the present invention further relates to RTWCG formulations, methods and processes that utilize a low-[HF]. In another embodiment, the present invention relates to RTWCG formulations with improved bath life. | 12-31-2015 |
| 20160093493 | Photoacid Generator Bound to Floating Additive Polymer - Methods and materials for making a semiconductor device are described. The method includes providing a substrate, forming a middle layer comprising a floating additive polymer (FAP) at an upper surface of the middle layer, the FAP chemically bound to a photoacid generator (PAG) and including a fluorine-containing material over the substrate, forming a photoresist layer over the middle layer, exposing the photoresist layer and the middle layer to an exposure energy to produce acid bound to the middle layer in the exposed areas of the middle layer, and developing the photoresist layer. | 03-31-2016 |
| 20160093574 | PHOTOLITHOGRAPHY ALIGNMENT MARK STRUCTURES, SEMICONDUCTOR STRUCTURES, AND FABRICATION METHOD THEREOF - A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; thrilling a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center along a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer: and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer. | 03-31-2016 |
| 20160099148 | METHOD OF PROCESSING TARGET OBJECT - A controllability of a size of a mask can be improved in a multi-patterning method. A process of forming a silicon oxide film on a first mask and an antireflection film is performed. In this process, plasma of a first gas including a silicon halide gas and plasma of a second gas including an oxygen gas are alternately generated. Then, a region of the silicon oxide film is removed such that only a region along a side wall of the first mask is left, and then, the first mask is removed and the antireflection film and an organic film is etched. | 04-07-2016 |
| 20160118256 | METHOD FOR SELECTIVITY ENHANCEMENT DURING DRY PLASMA ETCHING - A method of etching a layer on a substrate is described. The method includes disposing a substrate having a heterogeneous layer composed of a first material and a second material in a processing space of a plasma processing system, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material to a plasma environment in the processing space, and performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material. The modulated plasma etching process includes a modulation cycle that preferentially reacts an etchant with the first material during a first phase of the modulation cycle, and differentially adheres a passivant on the second material relative to the first material during a second phase of the modulation cycle. | 04-28-2016 |
| 20160133464 | Method of Patterning Incorporating Overlay Error Protection - Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions. | 05-12-2016 |
| 20160147152 | ADDITIVE FOR RESIST UNDERLAYER FILM-FORMING COMPOSITION AND RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING THE SAME - An additive for a resist underlayer film-forming composition that modifies a surface state of a resist underlayer film into a hydrophobic state to enhance adhesion between the resist underlayer film and a resist pattern formed on the resist underlayer film, and a resist underlayer film-forming composition containing the additive. An additive for a resist underlayer film-forming composition including a polymer having a structural unit of Formula (1): | 05-26-2016 |
| 20160155639 | Mechanisms for Forming Patterns Using Lithography Processes | 06-02-2016 |
| 20160163532 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N | 06-09-2016 |
| 20160163548 | Masking Process and Structures Formed Thereby - A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses. | 06-09-2016 |
| 20160181102 | HARD-MASK DEFINED BIT PATTERN SUBSTRATE | 06-23-2016 |
| 20160181115 | Method of Forming a Mask for Substrate Patterning | 06-23-2016 |
| 20160186006 | RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING POLYMER WHICH CONTAINS NITROGEN-CONTAINING RING COMPOUND - The present invention provides a resist underlayer film that has a wide focus position range within which a good resist shape can be obtained. A resist underlayer film-forming composition for lithography comprising a linear polymer that is obtained by a reaction of a diepoxy group-containing compound (A) with a dicarboxyl group-containing compound (B). The linear polymer has structures of the following formulae (1), (2), and (3) derived from the diepoxy group-containing compound (A) or the dicarboxyl group-containing compound (B): | 06-30-2016 |
| 20160202611 | METHODS OF MANUFACTURING PHOTOMASKS, METHODS OF FORMING PHOTORESIST PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 07-14-2016 |
| 20160203983 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 07-14-2016 |
| 20160203996 | SUBSTRATE MANUFACTURING METHOD AND SUBSTRATE MANUFACTURING APPARATUS | 07-14-2016 |
| 20160251546 | METAL-CONTAINING RESIST UNDERLAYER FILM-FORMING COMPOSITION CONTAINING POLYACID | 09-01-2016 |
| 20160254153 | METHODS OF FORMING PATTERNS HAVING DIFFERENT SHAPES | 09-01-2016 |
| 20160379824 | LOW ROUGHNESS EUV LITHOGRAPHY - Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed. | 12-29-2016 |
| 20180025914 | METHODS FOR HIGH TEMPERATURE ETCHING A MATERIAL LAYER USING PROTECTION COATING | 01-25-2018 |
