Class / Patent application number | Description | Number of patent applications / Date published |
438663000 | Rapid thermal anneal | 67 |
20090104770 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10Ω-μm | 04-23-2009 |
20100203725 | Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing - A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (W | 08-12-2010 |
20100323519 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE SUITABLE FOR FORMING WIRING USING DAMASCENE METHOD - (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members. | 12-23-2010 |
20110207321 | SEMICONDUCTOR DEVICE MANUFACTURIING METHOD - A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate. | 08-25-2011 |
20120064715 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up. | 03-15-2012 |
20120295439 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 11-22-2012 |
20130072015 | Inexpensive Electrode Materials to Facilitate Rutile Phase Titanium Oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 03-21-2013 |
20130122701 | Novel Passivation Composition and Process - This disclosure relates to a passivation composition containing at least one sulfonic acid, at least one compound containing a nitrate or nitrosyl ion, and water. The passivation composition is substantially free of a halide ion. | 05-16-2013 |
20130316533 | METHOD FOR REMOVING NATIVE OXIDE AND ASSOCIATED RESIDUE FROM A SUBSTRATE - Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH | 11-28-2013 |
438664000 | Forming silicide | 58 |
20080206988 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions - A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate. | 08-28-2008 |
20080261394 | Method for fabricating semiconductor device with silicided gate - A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure. | 10-23-2008 |
20080299767 | Method for Forming a Semiconductor Device Having a Salicide Layer - A method for forming a semiconductor device and selectively forming a salicide layer is described. In one embodiment, the method includes depositing a metal layer over a semiconductor substrate having a first area and a second area, wherein the first area and the second area include silicon, removing the metal layer over the second gate electrode, and reacting the metal layer with the first area to form a salicide layer over the first area. In one embodiment, the first area and the second area include a first gate electrode and a second gate electrode, respectively. | 12-04-2008 |
20080305630 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film. | 12-11-2008 |
20090004852 | Nanostructures Containing Metal Semiconductor Compounds - A network element ( | 01-01-2009 |
20090004853 | METHOD FOR FORMING A METAL SILICIDE - The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less. | 01-01-2009 |
20090017619 | METHOD FOR MANUFACTURING METAL SILICIDE LAYER IN A SEMICONDUCTOR DEVICE - A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD. Annealing is performed on the silicon substrate which is formed with the first and second metal layers to form the metal silicide. The portions of the second metal layer and the first metal layer which have not reacted during annealing are removed. | 01-15-2009 |
20090035938 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 02-05-2009 |
20090061623 | METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE - A method of forming an electrical connection structure is described. A dielectric layer is formed covering a first conductor on a substrate, and then an opening is formed in the dielectric layer exposing the first conductor. A first cleaning step is conducted using fluorine-containing plasma to clean the surfaces of the dielectric layer and the exposed first conductor, and then at least one low-temperature annealing step is conducted. A second cleaning step is conducted using argon plasma to clean the above surfaces. A second conductor is then formed in the opening. | 03-05-2009 |
20090075477 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a silicon-containing layer over a semiconductor substrate, forming a metal layer over the semiconductor substrate and the silicon-containing layer, forming a silicide-containing layer over the semiconductor substrate and the silicon-containing layer by heat treatment of the semiconductor substrate and the silicon-containing layer, and applying flash annealing to the silicide-containing layer. | 03-19-2009 |
20090155999 | METHOD FOR FABRICATING METAL SILICIDE - A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy. | 06-18-2009 |
20090191707 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate | 07-30-2009 |
20090280645 | Method of fabricating semiconductor device - Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region. | 11-12-2009 |
20090298284 | METHOD FOR PREPARING INTEGRATED CIRCUIT STRUCTURE WITH POLYMORPHOUS MATERIAL - A method for preparing an integrated circuit structure performs a deposition process to form a precursor layer on a substrate, and the precursor layer has a phase transition property in a transition temperature region. Subsequently, a first thermal treating process is performed at a first temperature to transform the precursor layer into a polymorphous layer possessing a predetermined crystalline phase, and the first temperature is higher than an upper limit of the temperature of the transition temperature region. | 12-03-2009 |
20100003817 | Method of light induced plating on semiconductors - Methods of light induced plating of nickel onto semiconductors are disclosed. The methods involve applying light at an initial intensity for a limited amount of time followed by reducing the intensity of the light for the remainder of the plating period to deposit nickel on a semiconductor. | 01-07-2010 |
20100015802 | DYNAMIC SCHOTTKY BARRIER MOSFET DEVICE AND METHOD OF MANUFACTURE - A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance. | 01-21-2010 |
20100041231 | FUSI Integration Method Using SOG as a Sacrificial Planarization Layer - A method for making a transistor | 02-18-2010 |
20100087061 | INTEGRATED CIRCUIT SYSTEM EMPLOYING BACKSIDE ENERGY SOURCE FOR ELECTRICAL CONTACT FORMATION - A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material. | 04-08-2010 |
20100112808 | Methods Of Forming A Plurality Of Transistor Gates, And Methods Of Forming A Plurality Of Transistor Gates Having At Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate. | 05-06-2010 |
20100151677 | ETCH METHOD IN THE MANUFACTURE OF A SEMICONDUCTOR DEVICE - The present invention provides a method for forming a transistor on a silicon substrate, the method comprising: providing a substrate comprising: a gate electrode with a liner comprising silicon and oxygen, and with a sidewall spacer, and source and/or drain region(s) in the substrate adjacent to the gate electrode, a layer at least 5 nm thick comprising silicon dioxide covering at least the source and/or drain regions; etching the layer comprising silicon and oxygen from at least the source and/or drain regions; and forming contacts for the source and/or drain region(s), characterized in that the layer comprising silicon and oxygen is etched from the substrate by steps comprising: forming an etchant from a plasma formed from a mixture comprising nitrogen trifluoride and ammonia; exposing the substrate to the etchant; and annealing the substrate. | 06-17-2010 |
20100178763 | METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: (a) forming an alloy film containing a precious metal on a substrate having a semiconductor layer or on a conductive film formed on the substrate; (b) heat-treating the substrate to allow the precious metal to react with silicon forming a silicide film containing the precious metal on the substrate or the conductive film; (c) removing an unreacted portion of the alloy film with a first chemical solution after the step (b); (d) forming a silicon oxide film on the top surface of the silicide film including a portion underlying a residue of the precious metal by exposing the substrate to an oxidative atmosphere; and (e) dissolving the residue of the precious metal with a second chemical solution. | 07-15-2010 |
20100178764 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes the steps of (a) forming a metal film containing a precious metal on a substrate having a semiconductor layer containing silicon or on a conductive film containing silicon formed on the substrate, (b) after step (a), heat-treating the substrate to allow the precious metal to react with silicon to form a silicide film containing the precious metal on the substrate or the conductive film, (c) after step (b), forming an oxide film on a portion of the silicide film underlying an unreacted portion of the precious metal using a first chemical solution, and (d) dissolving the unreacted portion of the precious metal using a second chemical solution. | 07-15-2010 |
20100190336 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film. | 07-29-2010 |
20100273324 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 10-28-2010 |
20110070732 | METHOD OF SILICIDE FORMATION BY ADDING GRADED AMOUNT OF IMPURITY DURING METAL DEPOSITION - A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy. | 03-24-2011 |
20110117738 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 05-19-2011 |
20110151666 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a plurality of trenches, forming first liner layers over bottom surfaces and inner sidewalls of the trenches to a first height, forming sacrificial liner layers on one of the inner sidewalls of the trenches where the first liner layers are formed, forming third sacrificial layers to a second height, so that the third sacrificial layers are buried over the trenches where the sacrificial liner layers are formed, removing portions of the sacrificial liner layers exposed by the third sacrificial layers to form sacrificial patterns, forming second liner layers on the inner sidewalls of the trenches exposed by the third sacrificial layers, and removing the third sacrificial layers to form side contact regions opening one of the inner sidewalls of the trenches in a line form. | 06-23-2011 |
20110237074 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical. | 09-29-2011 |
20110306205 | Semiconductor Device and Method of Fabricating the Same - Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi | 12-15-2011 |
20120040526 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film. | 02-16-2012 |
20120115326 | Method of Forming Metal Silicide Regions - The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure. | 05-10-2012 |
20120171863 | METAL SILICIDE FILM FORMING METHOD - There is provided a metal silicide film forming method that includes providing a substrate having thereon a silicon part (process 1); forming a metal film on a surface of the silicon part of the substrate by a CVD process using a nitrogen-containing metal compound as a film forming source material (process 2); performing an annealing process on the substrate under a hydrogen gas atmosphere; and forming a metal silicide by a reaction between the metal film and the silicon part (process 3). Here, the nitrogen-containing metal compound as the film forming source material is metal amidinate. Further, the metal film is a nickel (Ni) film. Furthermore, the metal amidinate is nickel amidinate. | 07-05-2012 |
20120190192 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 07-26-2012 |
20120202345 | METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS - Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon. | 08-09-2012 |
20120214303 | PROCESS FOR FORMING COBALT AND COBALT SILICIDE MATERIALS IN TUNGSTEN CONTACT APPLICATIONS - Embodiments of the invention generally provide methods for forming cobalt silicide. In one embodiment, a method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the substrate during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi | 08-23-2012 |
20120238092 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 09-20-2012 |
20120244700 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING METAL SILICIDE - Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a metal silicide in an upper portion of a gate electrode structure and in an active semiconductor region laterally adjacent to the gate electrode structure. A first portion of the metal silicide formed in the upper portion of the gate electrode structure is removed. | 09-27-2012 |
20120244701 | METHOD FOR FORMING NISI FILM, METHOD FOR FORMING SILICIDE FILM, METHOD FOR FORMING METAL FILM FOR USE IN SILICIDE-ANNEALING, APPARATUS FOR VACUUM PROCESSING AND FILM-FORMING APPARATUS - The method for the formation of a silicide film herein provided comprises the steps of forming an Ni film on the surface of a substrate mainly composed of Si and then heat-treating the resulting Ni film to thus form an NiSi film as an upper layer of the substrate, wherein, prior to the heat-treatment for the formation of the NiSi film, the Ni film is subjected to a preannealing treatment using H | 09-27-2012 |
20120282770 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a plurality of trenches, forming first liner layers over bottom surfaces and inner sidewalls of the trenches to a first height, forming sacrificial liner layers on one of the inner sidewalls of the trenches where the first liner layers are formed, forming third sacrificial layers to a second height, so that the third sacrificial layers are buried over the trenches where the sacrificial liner layers are formed, removing portions of the sacrificial liner layers exposed by the third sacrificial layers to form sacrificial patterns, forming second liner layers on the inner sidewalls of the trenches exposed by the third sacrificial layers, and removing the third sacrificial layers to form side contact regions opening one of the inner sidewalls of the trenches in a line form. | 11-08-2012 |
20130052819 | Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature. | 02-28-2013 |
20130065392 | METHOD FOR FORMING A SILICIDE LAYER AT THE BOTTOM OF A HOLE AND DEVICE FOR IMPLEMENTING SAID METHOD - A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole. | 03-14-2013 |
20130115768 | METHODS FOR DEPOSITING NICKEL FILMS AND FOR MAKING NICKEL SILICIDE AND NICKEL GERMANIDE - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. Nickel thin films can be used directly in silicidation and germanidation processes. | 05-09-2013 |
20130130497 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed. | 05-23-2013 |
20130137260 | MULTI-STAGE SILICIDATION PROCESS - A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices. | 05-30-2013 |
20130171818 | Method of Manufacturing A Semiconductor Device - In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process. | 07-04-2013 |
20130196505 | METHOD OF FORMING CONFORMAL METAL SILICIDE FILMS - A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios. | 08-01-2013 |
20130224950 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 08-29-2013 |
20130230984 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 09-05-2013 |
20130273737 | Method for Cleaning Semiconductor Substrate - Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate. | 10-17-2013 |
20130280907 | SILICIDATION AND/OR GERMANIDATION ON SIGE OR GE BY COSPUTTERING NI AND GE AND USING AN INTRALAYER FOR THERMAL STABILITY - Formation of a semiconductor device with NiGe or NiSiGe and with reduced consumption of underlying Ge or SiGe is provided. Embodiments include co-sputtering nickel (Ni) and germanium (Ge), forming a first Ni/Ge layer on a Ge or silicon germanium (SiGe) active layer, depositing titanium (Ti) on the first Ni/Ge or Ni/Si/Ge layer, forming a Ti intermediate layer, co-sputtering Ni and Ge on the Ti intermediate layer, forming a second Ni/Ge layer, and performing a rapid thermal anneal (RTA) process. | 10-24-2013 |
20130295765 | TWO-STEP SILICIDE FORMATION - One embodiment of the present invention comprises a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region. A silicide intermix layer is formed over both the source/drain region and a portion of the extension region. A silicide contact is formed through the silicide intermix layer over the source/drain region. | 11-07-2013 |
20140017888 | SALICIDE PROCESS - A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer. | 01-16-2014 |
20140065819 | Methods and Systems for Low Resistance Contact Formation - Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate. | 03-06-2014 |
20140206188 | METHOD OF FORMING A METAL SILICIDE LAYER - A method for forming a metal silicide layer is disclosed. The method includes the steps of: forming a first metal layer with a thickness less than 10 nm on a silicon substrate; forming a second metal layer with a thickness more than 10 nm on the first metal layer; annealing the metal layers and the silicon substrate, so that a part of the second metal layer penetrates through the first metal layer, and both the part of the second metal layer penetrating through the first metal layer and a part of the first metal layer react with the silicon substrate to form the metal silicide layer, while the remaining part of the first and second metal layers form a third metal layer; and removing the third metal layer, so that the metal silicide layer can be formed in the semiconductor substrate. | 07-24-2014 |
20140248770 | MICROWAVE-ASSISTED HEATING OF STRONG ACID SOLUTION TO REMOVE NICKEL PLATINUM/PLATINUM RESIDUES - A method is provided for removing residual Ni/Pt and/or Pt from a semiconductor substrate in a post salicidation cleaning process using microwave heating of a stripping solution. Embodiments include depositing a Ni/Pt layer on a semiconductor substrate; annealing the deposited Ni/Pt layer, forming a nickel/platinum silicide and residual Ni/Pt and/or Pt; removing the residual Ni/Pt and/or Pt from the semiconductor substrate by: microwave heating a strong acid solution in a non-reactive container; exposing the residual Ni/Pt and/or Pt to the microwave heated strong acid solution; and rinsing the semiconductor substrate with water H | 09-04-2014 |
20150332936 | DUAL SILICIDE INTEGRATION WITH LASER ANNEALING - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating more particularly to a structure and method for fabricating silicides with different compositions and/or thicknesses on a single structure having more than one type of device using laser annealing. A method is disclosed that includes using a photoresist compatible with a laser annealing process to protect a region of a semiconductor substrate from silicide formation. | 11-19-2015 |
20150364329 | Carbon Layer and Method of Manufacture - A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene. | 12-17-2015 |
20160056053 | METHOD AND APPARATUS TO DEPOSIT PURE TITANIUM THIN FILM AT LOW TEMPERATURE USING TITANIUM TETRAIODIDE PRECURSOR - Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C. | 02-25-2016 |