| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438631000 | Having planarization step | 27 |
| 20080254615 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features. | 10-16-2008 |
| 20080286962 | METHOD FOR FABRICATING METAL PAD - A method for fabricating a metal pad is disclosed. The fabrication method includes the step of selectively etching a wire insulation film formed on a semiconductor substrate to form a pattern, such as a dual damascene pattern, having plural vias in one trench. A metal film is deposited to fill the pattern and an insulation film is formed on the metal film. Further, the method includes removing the insulation film and the metal film to expose a surface of the wire insulation film to thereby form a metal pad and via contacts. | 11-20-2008 |
| 20090017611 | Semiconductor device and method for fabricating the same - In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect. | 01-15-2009 |
| 20090029543 | CLEANING PROCESS FOR MICROELECTRONIC DIELECTRIC AND METAL STRUCTURES - A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure. | 01-29-2009 |
| 20090061617 | EDGE BEAD REMOVAL PROCESS WITH ECMP TECHNOLOGY - A method and apparatus for the removal of a deposited conductive layer along an edge of a substrate using a power ring configured to electro polish an edge of the substrate are provided. The electro polishing of the substrate edge may occur simultaneously with the electrochemical mechanical processing of a substrate face. In certain embodiments a method of electrochemically polishing a substrate having a conductive material disposed thereon is provided. A substrate is coupled with a carrier head comprising a power ring which surrounds an edge of the substrate, wherein the edge of the substrate includes the conductive material. A polishing pad is contacted with a face of the substrate. A first voltage is applied to the power ring to remove conductive material from the edge of the substrate. A second voltage different from the first voltage is applied to the polishing pad to remove a portion of the conductive material from the face of the substrate. | 03-05-2009 |
| 20090137112 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body. The method also comprises forming a plurality of second parallel trenches in the block body with the second wiring material stacked thereon, the second trenches extending in a second direction crossing the first direction and having a depth reaching the upper surface of the first wiring material, thereby forming second lines extending in the second direction and memory cells self-aligned with the second lines and separated by the first and second trenches. | 05-28-2009 |
| 20090239374 | Methods of Forming Metal Interconnect Structures on Semiconductor Substrates Using Oxygen-Removing Plasmas and Interconnect Structures Formed Thereby - Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water. | 09-24-2009 |
| 20100029075 | THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS - Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts. | 02-04-2010 |
| 20100203723 | Semiconductor device and method of manufacturing semiconductor device - There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces. | 08-12-2010 |
| 20110021019 | METHOD FOR FORMING DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS - The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells. | 01-27-2011 |
| 20120077339 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both. | 03-29-2012 |
| 20120225549 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires. | 09-06-2012 |
| 20120329268 | METHOD OF MAKING A SEMICONDUCTOR DEVICE - An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized. | 12-27-2012 |
| 20140273432 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device is fabricated by forming a lower conductor in a first interlayer dielectric film. A second interlayer dielectric film is formed on the lower conductor and the first interlayer dielectric film. A first hard mask pattern is formed on the second interlayer dielectric film. The first mask pattern has a first opening extending in a first direction. A planarization layer is formed on the first hard mask pattern. A mask pattern is formed on the planarization layer. The mask pattern has a second opening extending in a second direction perpendicular to the first direction. The lower conductor is positioned under an region where the first opening and the second opening overlap. A via hole and a trench connected to the via hole is formed using the first hard mask pattern and the mask pattern. The via hole exposes an upper surface of the lower conductor. | 09-18-2014 |
| 20140335689 | Method of Fabricating a Semiconductor Interconnect Structure - A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer. | 11-13-2014 |
| 20150011083 | Through-Vias and Methods of Forming the Same - An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring. | 01-08-2015 |
| 20150147878 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed. | 05-28-2015 |
| 20160133630 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole. | 05-12-2016 |
| 438633000 | Simultaneously by chemical and mechanical means | 8 |
| 20080233736 | PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer. | 09-25-2008 |
| 20090061618 | Method of Manufacturing Metal Interconnection - A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer. | 03-05-2009 |
| 20090142919 | Semiconductor device and manufacturing method of the same - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 06-04-2009 |
| 20100120242 | METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS - One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More particularly, a semiconductor body comprising one or more exposed copper metal levels is coated with a benzotriazole (BTA) solution. The semiconductor body is then dried, resulting in a protective layer of BTA coating the copper metal levels. The protective layer of BTA passivates the exposed copper surface by forming a protective BTA layer that prevents the copper metal level from coming into direct contact with deionized water thereby preventing copper metal dissolution and providing improved integrated chip yields and reliability. | 05-13-2010 |
| 20110003471 | Fabrication of interconnects in a low-k interlayer dielectrics - A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug. | 01-06-2011 |
| 20130012019 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser. | 01-10-2013 |
| 20130178057 | Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique - Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench. | 07-11-2013 |
| 20160190005 | PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY - A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer. | 06-30-2016 |
| 438634000 | Utilizing etch-stop layer | 1 |
| 20140342549 | DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME - A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. | 11-20-2014 |
