| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438627000 | At least one layer forms a diffusion barrier | 89 |
| 20080206982 | INTERCONNECT STRUCTURES WITH A METAL NITRIDE DIFFUSION BARRIER CONTAINING RUTHENIUM AND METHOD OF FORMING - A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming metal over the surfaces of the micro-feature. The nitride-forming metal is selected from Groups IVB, VB, VIB, and VIIB of the Periodic Table, and the metal nitride diffusion barrier is formed by exposing the substrate to a precursor of the nitride-forming metal, a nitrogen precursor, and a ruthenium precursor. | 08-28-2008 |
| 20080206983 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - The present invention is a method of manufacturing a photoelectric conversion device having a multilayered interconnection (wiring) structure disposed on a semiconductor substrate, including steps of forming a hole in a region of the interlayer insulation film corresponding to an electrode of the transistor; burying an electroconductive substance in the hole; forming a hydrogen supplying film; conducting a thermal processing at a first temperature to supply a hydrogen from the hydrogen supplying film to the semiconductor substrate; forming the multilayered interconnection structure using Cu in a wiring material; and forming a protective film covering the multilayered interconnection structure, wherein the step of forming the multilayered interconnection structure, and the step of forming the protective film are conducted at a temperature not higher than the first temperature. | 08-28-2008 |
| 20080254614 | MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES - Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion. | 10-16-2008 |
| 20080261391 | Method of producing semiconductor device - A method of producing a semiconductor device includes the steps of: preparing a base member; laminating sequentially a barrier film formed of titanium nitride, a wiring portion film formed of tungsten, and a mask film formed of titanium nitride on the base member to form a multi-layer film; forming a resist mask on the mask film so that the resist mask covers a wiring portion forming area and exposes a wiring portion non-forming area; etching the mask film using a first gas in which titanium nitride has a large etching ratio with respect to tungsten; and etching the wiring portion film using a second gas in which tungsten has a large etching ratio with respect to titanium nitride so that a portion of the wiring portion film in the wiring portion non-forming area is removed and a portion of the wiring portion film in the wiring portion forming area remains. | 10-23-2008 |
| 20080280432 | Barrier Material and Process for Cu Interconnect - A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods. | 11-13-2008 |
| 20080299763 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - After a first insulating film is formed on a substrate, a wiring groove is formed in the first insulating film, and then a wire is formed inside the wiring groove. Subsequently, a protection film is formed on the first insulating film and on the wire, and then a hard mask film is formed on the protection film. After that, the hard mask film is patterned. Subsequently, the protection film and the first insulating film are partially removed using the patterned hard mask film to form an air gap groove, and then a second insulating film is formed to close an upper portion of the air gap groove for forming an air gap. | 12-04-2008 |
| 20080318411 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask | 12-25-2008 |
| 20080318412 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming an interlayer insulating film over a wiring layer, forming an opening in the interlayer insulating film, performing a first plasma treatment using a gas including hydrogen or ammonia, performing a second plasma treatment with a gas including fluorocarbon after the first plasma treatment. | 12-25-2008 |
| 20090042384 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND TARGET SUBSTRATE PROCESSING SYSTEM - A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connector member. The second interlayer insulation film is disposed on a first interlayer insulation film provided with the electric connector member. The method then includes reducing a surface of the electric connector member exposed at a bottom of the groove of the second interlayer insulation film; forming a barrier layer on the second interlayer insulation film; and forming a copper-containing conductive film to fill the groove of the second interlayer insulation film. | 02-12-2009 |
| 20090053888 | Method of depositing a diffusion barrier layer which provides an improved interconnect - A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer. | 02-26-2009 |
| 20090061616 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device capable of minimizing hillocks and voids. The method includes subjecting an interlayer dielectric having a multi-protective dielectric structure including a first barrier metal layer and a first copper line to a plurality of NH | 03-05-2009 |
| 20090068832 | THIN FILMS - Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO | 03-12-2009 |
| 20090081863 | METHOD OF FORMING METAL WIRING LAYER OF SEMICONDUCTOR DEVICE - A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring. | 03-26-2009 |
| 20090098727 | Method of Forming Metal Line of Semiconductor Device - Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating layer. The first barrier metal layer is formed such that the TiN layer is formed thinner at a bottom of the contact hole than on sidewalls and a top surface of the second insulating layer. A first metal layer is formed on the first barrier metal layer, including on the contact hole. Thermal treatment is carried to gap-fill the contact hole as the first metal layer is reflown and smooth. A second metal layer is formed on the first metal layer. The second metal layer to form an upper metal line. | 04-16-2009 |
| 20090117731 | SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening. | 05-07-2009 |
| 20090142918 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer. | 06-04-2009 |
| 20090149019 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover the upper surface of the insulating barrier film, and have a second interconnection buried therein. | 06-11-2009 |
| 20090163020 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device is provided. A first interlayer dielectric film can be formed on a semiconductor substrate, and a metal wire can be formed on the first interlayer dielectric film. A second interlayer dielectric film can be formed on the first interlayer dielectric film, including the metal wire. A photoresist pattern can be formed on the second interlayer dielectric film. The photoresist pattern can include a high pattern density region having a first plurality of openings, a low pattern density region having a second plurality of openings, and a dummy pattern region having a third plurality of openings. Via holes can be formed by etching the second interlayer dielectric film using the photoresist pattern as a mask. | 06-25-2009 |
| 20090233438 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 09-17-2009 |
| 20090263963 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film. | 10-22-2009 |
| 20090305498 | SEMICONDUCTOR DEVICE COMPRISING A COPPER ALLOY AS A BARRIER LAYER IN A COPPER METALLIZATION LAYER - By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction. | 12-10-2009 |
| 20100009530 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer. | 01-14-2010 |
| 20100068880 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer ( | 03-18-2010 |
| 20100105202 | METHOD OF FORMING AN INTERCONNECT STRUCTURE - A method of forming an interconnect structure in a semiconductor device in which via holes ( | 04-29-2010 |
| 20100130001 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP. | 05-27-2010 |
| 20100151672 | METHODS OF FORMING METAL INTERCONNECTION STRUCTURES - Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer. | 06-17-2010 |
| 20100151673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %. | 06-17-2010 |
| 20100151674 | Structures Electrically Connecting Aluminum and Copper Interconnections and Methods of Forming the Same - A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole. | 06-17-2010 |
| 20100227470 | Manufacturing Method of Semiconductor Integrated Circuit Device - In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value. According to the invention, in a via hole formation step in a damascene semi-global interconnect or the like, dry etching treatment of a via-bottom etch stop film is performed and then, after nitrogen plasma treatment in the same treatment chamber, electrostatic charge removal treatment by using argon plasma is performed. | 09-09-2010 |
| 20100248472 | Methods Of Forming Copper-Comprising Conductive Lines In The Fabrication Of Integrated Circuitry - A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the damascene material. Copper-comprising material is electrochemically deposited over the damascene material. The copper-comprising material is removed and the damascene material is exposed, and individual copper-comprising conductive lines are formed within individual of the line trenches. The damascene material is removed selectively relative to the conductive copper-comprising material. Dielectric material is deposited laterally between adjacent of the individual copper-comprising conductive lines. The deposited dielectric material is received against sidewalls of the individual copper-comprising conductive lines. A void is received laterally between immediately adjacent of the individual copper-comprising conductive lines within the deposited dielectric material. Other embodiments are contemplated. | 09-30-2010 |
| 20110021018 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole. | 01-27-2011 |
| 20110039408 | Semiconductor Device and Fabrication Method Thereof - Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer. | 02-17-2011 |
| 20110045668 | Method of manufacturing wafer level device package - There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer. | 02-24-2011 |
| 20110092067 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 04-21-2011 |
| 20110097895 | SEMICONDUCTOR DEVICES INCLUDING INTERLAYER CONDUCTIVE CONTACTS AND METHODS OF FORMING THE SAME - In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width. | 04-28-2011 |
| 20110117737 | Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics - A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element. | 05-19-2011 |
| 20110124189 | Increasing Electromigration Resistance in an Interconnect Structure of a Semiconductor Device by Forming an Alloy - By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents. | 05-26-2011 |
| 20110183512 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING CONTACT PLUG - A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern. | 07-28-2011 |
| 20110189849 | SEMICONDUCTOR DEVICE WITH A BARRIER FILM - A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film. | 08-04-2011 |
| 20110217840 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 09-08-2011 |
| 20110237066 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING APPARATUS, AND STORAGE MEDIUM - The present invention is a method of manufacturing a semiconductor device comprising: forming a recess in an interlayer insulating film formed on a substrate surface, the recess being configured to be embedded with an upper conductive channel mainly made of copper to be electrically connected to a lower conductive channel; supplying a gas containing an organic compound of manganese, and forming a barrier layer made of a compound of manganese for preventing diffusion of copper to the interlayer insulating film, such that the barrier layer covers an exposed surface of the interlayer insulating film; after the formation of the barrier layer, supplying organic acid to the barrier layer in order to increase a ratio of manganese in the compound of manganese forming the barrier layer; after the supply of the organic acid, forming a seed layer mainly made of copper on a surface of the barrier layer; after the formation of the seed-layer, heating the substrate in order to separate out manganese from on the surface of the barrier layer or from in the barrier layer onto a surface of the seed layer; supplying a cleaning liquid to the seed layer in order to remove the manganese separated out on the surface of the seed layer by the heating; and after the supply of the cleaning liquid, forming the upper conductive channel mainly made of copper in the recess. | 09-29-2011 |
| 20110237067 | STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS - The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer. The structure also includes a first metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the first metal semiconductor alloy layer and a second metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re located on, and self-aligned to the second metal semiconductor alloy layer. | 09-29-2011 |
| 20110263117 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device in which moisture is removed from a porous low-dielectric layer after a chemical mechanical polishing (CMP) process include formation of a porous low-dielectric layer on a substrate. A metal interconnection is formed on the substrate having the porous low-dielectric layer. The metal interconnection forms a planar surface with the porous low-dielectric layer to fill the openings. Ultraviolet (UV) light is irradiated to the porous low-dielectric layer to remove absorbed moisture from the porous low-dielectric layer. A capping layer is formed on the substrate having the porous low-dielectric layer and the metal interconnection. The capping layer is formed in-situ to prevent additional absorption of moisture. | 10-27-2011 |
| 20110275214 | DUAL DAMASCENE-LIKE SUBTRACTIVE METAL ETCH SCHEME - Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4. | 11-10-2011 |
| 20110300706 | METHOD FOR FABRICATING INTERCONNECTION STRUCTURE - A method for fabricating an interconnection structure includes the following steps. Firstly, a substrate having a first conductive layer thereon is provided. Next, an ultra low-k material layer is formed on the substrate. Next, a portion of the ultra low-k material layer is removed, so as to form an opening to expose the first conductive layer. Next, a dry-cleaning process is performed by using gas, so as to clean a surface of the first conductive layer exposed by the opening. The dry-cleaning process is performed at a temperature in a range from the room temperature to 100° C. | 12-08-2011 |
| 20110306201 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer. | 12-15-2011 |
| 20120003829 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer. | 01-05-2012 |
| 20120015514 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 01-19-2012 |
| 20120149190 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO | 06-14-2012 |
| 20120171860 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 07-05-2012 |
| 20120190188 | METHOD FOR FILLING A GAP - A method for filling a gap includes: providing a semiconductor substrate, at least having an metal interconnect layer and an insulating dielectric layer on top of the underlying metal interconnect layer, the insulating dielectric layer having a gap; forming a diffusion bather layer and a seed layer sequentially in the gap and on a surface of the insulating dielectric layer outside the gap; forming a mask layer on a surface of the seed layer outside of the gap; and depositing a metal layer on the semiconductor substrate with the mask layer, the metal layer filling the gap. | 07-26-2012 |
| 20120190189 | Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure. | 07-26-2012 |
| 20120196435 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes, but is not limited to, the following processes. A first interlayer insulating film is formed. A hole is formed in the first interlayer insulating film. A second interlayer insulating film is formed, which buries the hole and covers the first interlayer insulating film. An interconnect groove is formed by selectively etching the second interlayer insulating film to leave the second interlayer insulating film in the hole. The second interlayer insulating film in the hole is removed. | 08-02-2012 |
| 20120208362 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 08-16-2012 |
| 20120264288 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A generation of a void in a recessed section is inhibited. A method for manufacturing a semiconductor device includes: an operation of forming recessed sections in an insulating film, which is formed on a semiconductor substrate; an operation of forming a seed film in the recessed section; an operation of forming a cover metal film in the recessed section; an operation of selectively removing the cover metal film to expose the seed film over the bottom section of the recessed section; and an operation to carrying out a growth of a plated film to fill the recessed section by utilizing the seed film exposed in the bottom section of the recessed section as a seed. | 10-18-2012 |
| 20120270389 | METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE AND OF METAL NITRIDE LAYER THEREOF - A method for manufacturing a metal nitride layer including the following steps is provided. Firstly, a substrate is provided. Then, a physical vapor deposition process is performed at a temperature between 210° C. and 390° C. to form a metal nitride layer on the substrate. Also, the physical vapor deposition process can be performed on a pressure between 21 mTorr and 91 mTorr. The method can be used in the manufacturing process of an interconnection structure for decreasing the film stress of the metal nitride layer. Therefore, the interconnection structure can be prevented from line distortion and film collapse. | 10-25-2012 |
| 20120315751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating layer, forming a trench in the first insulating layer, forming an interconnect in the trench, forming a space between the first insulating layer and the interconnect, and disposing an upper surface of the interconnect at a position higher than an upper surface of the first insulating layer, forming an air gap in the space and forming an etching stopper film over the first insulating layer and the interconnect, forming a second insulating layer over the etching stopper film, and forming a via in the second insulating layer to be disposed over the interconnect. | 12-13-2012 |
| 20120329267 | Interconnect structures and methods for back end of the line integration - A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. | 12-27-2012 |
| 20130005137 | BARRIER SEQUENCE FOR USE IN COPPER INTERCONNECT METALLIZATION - A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber. | 01-03-2013 |
| 20130029483 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material. | 01-31-2013 |
| 20130078797 | METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT - The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability. | 03-28-2013 |
| 20130089979 | SEMICONDUCTOR DEVICE HAVING A MULTILEVEL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere. | 04-11-2013 |
| 20130149859 | TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME - A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur. | 06-13-2013 |
| 20130196500 | METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS - A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material. | 08-01-2013 |
| 20130244419 | INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer. | 09-19-2013 |
| 20130252415 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 09-26-2013 |
| 20130260552 | Reverse Damascene Process - The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. | 10-03-2013 |
| 20130302978 | METHOD OF FORMING A GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES - Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. | 11-14-2013 |
| 20140038409 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 02-06-2014 |
| 20140065815 | BEOL INTEGRATION SCHEME FOR COPPER CMP TO PREVENT DENDRITE FORMATION - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired. | 03-06-2014 |
| 20140065816 | DIELECTRIC FORMATION - Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated. | 03-06-2014 |
| 20140127896 | METHOD OF FORMING A GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES - Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material. | 05-08-2014 |
| 20140248767 | Methods Of Fabricating Integrated Circuitry - A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via. | 09-04-2014 |
| 20140329383 | SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING - A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver. | 11-06-2014 |
| 20140349477 | METHODS AND APPARATUSES FOR VOID-FREE TUNGSTEN FILL IN THREE-DIMENSIONAL SEMICONDUCTOR FEATURES - Disclosed herein are methods of filling a 3-D structure of a semiconductor substrate with a tungsten-containing material. The 3-D structure may include sidewalls, a plurality of openings in the sidewalls leading to a plurality of features having a plurality of interior regions. The methods may include depositing a first layer of the tungsten-containing material within the 3-D structure such that the first layer partially fills a plurality of interior regions of the 3-D structure, etching vertically and horizontally after depositing the first layer, and depositing a second layer of the tungsten-containing material within the 3-D structure after the vertical and horizontal etching such that the second layer fills at least a portion of the interior regions left unfilled by the first layer. Also disclosed herein are apparatuses for filling a 3-D structure of a semiconductor substrate with a tungsten-containing material having a controller with instructions for etching vertically and horizontally. | 11-27-2014 |
| 20150140805 | METHODS FOR FORMING AN INTERCONNECT PATTERN ON A SUBSTRATE - Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer. | 05-21-2015 |
| 20150140806 | WAFER-LEVEL DIE ATTACH METALLIZATION - Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias. | 05-21-2015 |
| 20150318205 | METHOD FOR FORMING INTERCONNECTION STRUCTURES - The present invention provides a method for forming interconnection structures, including the following steps: providing a semiconductor wafer with a dielectric layer; forming a first recessed area for forming the interconnection structures and a non-recessed area on the dielectric layer; forming a second recessed area for forming dummy structures on the dielectric layer; depositing a barrier layer to cover the first and second recessed areas and the non-recessed area; depositing a metal layer to fill the first and second recessed areas and cover the non-recessed area; removing the metal layer on the non-recessed area to expose the barrier layer; and removing the barrier layer on the non-recessed area to expose the dielectric layer. | 11-05-2015 |
| 20150325474 | Self-Aligned Barrier and Capping Layers For Interconnects - An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided. | 11-12-2015 |
| 20150332959 | METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION - Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions. | 11-19-2015 |
| 20150364367 | SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER - A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. | 12-17-2015 |
| 20160035618 | ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS - An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. | 02-04-2016 |
| 20160056076 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 02-25-2016 |
| 20160126185 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1. | 05-05-2016 |
| 20160172233 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160181153 | INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL | 06-23-2016 |
| 20160190008 | TUNGSTEN FEATURE FILL - Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). | 06-30-2016 |
| 20160197013 | SELF-ALIGNED VIA INTERCONNECT STRUCTURES | 07-07-2016 |
| 20160204025 | TRANSISTOR, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 07-14-2016 |
