| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438626000 | Planarization | 15 |
| 20080299761 | Interconnection process - An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole. | 12-04-2008 |
| 20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 12-04-2008 |
| 20090004844 | Forming Complimentary Metal Features Using Conformal Insulator Layer - A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface. | 01-01-2009 |
| 20090087980 | METHODS OF LOW-K DIELECTRIC AND METAL PROCESS INTEGRATION - An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-k dielectric structures, generating a protective layer on the low-k dielectric followed by cleaning the surface of the gapfill metal. Another embodiment of the present invention includes a method of protecting low-k dielectrics such as carbon doped silicon oxide. | 04-02-2009 |
| 20090142917 | METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE - Methods for fabricating a metal line of a semiconductor device are disclosed. In a disclosed example, the method includes a first step of forming a passivation film on a semiconductor substrate having a semiconductor device, a second step of forming contact holes in the passivation film to form a first contact plug, a third step of sequentially forming at least two metal layers on an entire surface of the substrate including the first contact plug, a fourth step of selectively etching one of the at least two metal layers to form a second contact plug, a fifth step of selectively etching the other of the at least two metal layers to form a metal line, and a sixth step of exposing an upper surface of the second contact plug. | 06-04-2009 |
| 20110059607 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer. | 03-10-2011 |
| 20120231623 | METHOD OF MANUFACTURING A HIGH-RELIABILITY SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring. | 09-13-2012 |
| 20130316528 | Interconnect Barrier Structure and Method - A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device. | 11-28-2013 |
| 20140162450 | INTERCONNECT STRUCTURE WITH AN ELECTROMIGRATION AND STRESS MIGRATION ENHANCEMENT LINER - An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material. | 06-12-2014 |
| 20140187036 | INTEGRATION OF Ru WET ETCH AND CMP FOR BEOL INTERCONNECTS WITH Ru LAYER - Embodiments described herein provide approaches for interconnect formation in a semiconductor device. Specifically, a Cu layer is removed to a top surface of an Ru layer using CMP, the Cu layer is removed to form a recess within each of a plurality of trenches of a dielectric of the semiconductor device, and the Ru layer is removed using an etch process (e.g., a wet etch). An additional CMP is performed to reach the desired target trench height and to planarize the wafer. | 07-03-2014 |
| 20140187037 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts. | 07-03-2014 |
| 20150072519 | Metal and Via Definition Scheme - A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. | 03-12-2015 |
| 20150364370 | Aluminum Interconnection Apparatus - A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process. | 12-17-2015 |
| 20160079181 | TRACEABLE INTEGRATED CIRCUITS AND PRODUCTION METHOD THEREOF - An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible. | 03-17-2016 |
| 20160163589 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE STRUCTURES - A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level. | 06-09-2016 |
