| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438588000 | Plural gate levels | 20 |
| 20090186474 | Nonvolatile semiconductor storage device and manufacturing method therefor - A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film. | 07-23-2009 |
| 20090280631 | Electroless Metal Deposition For Dual Work Function - The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate. | 11-12-2009 |
| 20090280632 | MOSFETS Having Stacked Metal Gate Electrodes and Method - MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate. | 11-12-2009 |
| 20090325371 | Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes - A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer. | 12-31-2009 |
| 20100240205 | METHODS OF FABRICATING THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES USING EXPANSIONS - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. | 09-23-2010 |
| 20120064707 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein. | 03-15-2012 |
| 20120164821 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer. | 06-28-2012 |
| 20120289039 | PATTERN FORMING METHOD - According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns. | 11-15-2012 |
| 20130084696 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed. | 04-04-2013 |
| 20130217218 | FABRICATING METHOD OF NON-VOLATILE MEMORY - A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction. | 08-22-2013 |
| 20130224942 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage. | 08-29-2013 |
| 20140004691 | PATTERN FORMING METHOD | 01-02-2014 |
| 20140220770 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage. | 08-07-2014 |
| 20150044860 | MULTI-TIERED SEMICONDUCTOR APPARATUSES INCLUDING RESIDUAL SILICIDE IN SEMICONDUCTOR TIER - Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described. | 02-12-2015 |
| 20150050803 | METHODS OF FORMING SEMICONDUCTOR DEVICES, INCLUDING FORMING PATTERNS BY PERFORMING AN OXIDATION PROCESS - Methods of forming semiconductor devices are provided. A method of forming a semiconductor device may include forming a structure including insulating layers and gate layers that are alternately and repeatedly stacked on a substrate. The method may include forming through-holes in the structure. The method may include forming first patterns on sidewalls of the gate layers, by performing an oxidation process. The method may include forming second patterns on portions of the substrate, by performing the oxidation process. The method may include removing the second patterns. Moreover, the method may include forming semiconductor patterns in the through-holes. | 02-19-2015 |
| 20150072512 | METHODS AND APPARATUSES INCLUDING STRINGS OF MEMORY CELLS FORMED ALONG LEVELS OF SEMICONDUCTOR MATERIAL - Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed. | 03-12-2015 |
| 20150079776 | INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 03-19-2015 |
| 20150099353 | Non-Volatile Memory Devices and Methods of Manufacturing the Same - A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern. | 04-09-2015 |
| 20150380426 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that includes a plurality of first conductive patterns stacked over a substrate, dummy patterns formed in the first conductive patterns, respectively, first barrier patterns each surrounding the respective first conductive patterns and partially interposed between the respective first conductive patterns and the respective dummy patterns, second barrier patterns each surrounding the respective first barrier patterns and the respective dummy patterns, a second conductive pattern located over or under the first conductive patterns, and a third barrier pattern surrounding the second conductive pattern, wherein the second conductive pattern has a greater thickness than the first conductive patterns. | 12-31-2015 |
| 20160093716 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished. | 03-31-2016 |
