| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438514000 |
Ion implantation of dopant into semiconductor region
| 374 |
| 438542000 |
Diffusing a dopant
| 124 |
| 438513000 |
Plasma (e.g., glow discharge, etc.)
| 96 |
| 438535000 |
By application of corpuscular or electromagnetic radiation (e.g., electron, laser, etc.)
| 8 |
| 438511000 |
Ordering or disordering | 5 |
| 20080220595 | METHOD FOR FABRICATING A HYBRID ORIENTATION SUBSTRATE - A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer. | 09-11-2008 |
| 20080268623 | SEMICONDUCTOR DOPING WITH IMPROVED ACTIVATION - A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components. | 10-30-2008 |
| 20090061605 | PROFILE ADJUSTMENT IN PLASMA ION IMPLANTER - A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment. | 03-05-2009 |
| 20090191696 | METHOD FOR INCREASING THE PENETRATION DEPTH OF MATERIAL INFUSION IN A SUBSTRATE USING A GAS CLUSTER ION BEAM - A method for infusing material below the surface of a substrate is described. The method comprises modifying a surface condition of a surface on a substrate to produce a modified surface layer, and thereafter, infusing material into the modified surface in the substrate by exposing the substrate to a gas cluster ion beam (GCIB) comprising the material. | 07-30-2009 |
| 20140213047 | FABRICATION OF ULTRA-SHALLOW JUNCTIONS - A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region. | 07-31-2014 |
| 438537000 |
Fusing dopant with substrate (i.e., alloy junction) | 3 |
| 20150017793 | FORMATION OF LOCALISED MOLTEN REGIONS IN SILICON CONTAINING MULTIPLE IMPURITY TYPES - A method for creating an inwardly extending impurity distribution profile in a substrate comprising crystalline silicon material having a background doping of a first impurity type, comprising: a) providing one or more additional impurity sources with at least two different types of impurity atoms within the substrate or in proximity to the surface of the substrate, with each of these impurity atoms having different diffusion coefficients or segregation coefficients; b) locally melting a point on the surface of the substrate with a laser, whereby the at least two different types of impurity atoms are incorporated into the melted silicon material; c) removing the laser to allow the silicon material to recrystallise; d) controlling a rate of application and/or removal of the laser to control the creation of the impurity distribution profile, with different distribution profiles for each of the at least two types of impurity atoms in the recrystallised material. | 01-15-2015 |
| 20090098718 | Multiple mask and method for producing differently doped regions - In order to produce doping regions (DG) in a substrate (S) having different dopings with the aid of a single mask (DM) different mask regions are provided which have elongated mask openings (MO) having different orientations relative to the spatial direction of an oblique implantation. The substrate is rotated between the first and second oblique implantations, wherein during the first oblique implantation maximum and minimum shadings in the different mask regions are opposite one another and the conditions are precisely reversed during the second oblique implantation after the rotation of the substrate. | 04-16-2009 |
| 20120149181 | METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture. | 06-14-2012 |
| Entries |
| Document | Title | Date |
|---|
| 20080200015 | MULTI-STEP PLASMA DOPING WITH IMPROVED DOSE CONTROL - A method of multi-step plasma doping a substrate includes igniting a plasma from a process gas. A first plasma condition is established for performing a first plasma doping step. The substrate is biased so that ions in the plasma having the first plasma condition impact a surface of the substrate thereby exposing the substrate to a first dose. The first plasma condition transitions to a second plasma condition. The substrate is biased so that ions in the plasma having the second plasma condition impact the surface of the substrate thereby exposing the substrate to a second dose. The first and second plasma conditions are chosen so that the first and second doses combine to achieve a predetermined distribution of dose across at least a portion of the substrate. | 08-21-2008 |
| 20090087968 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 04-02-2009 |
| 20090142910 | MANUFACTURING METHOD OF MULTI-LEVEL NON-VOLATILE MEMORY - A manufacturing method of a multi-level non-volatile memory includes following steps. First, a tunneling dielectric layer and a charge storage layer are sequentially formed on the substrate. At least two stacked layers are formed on the charge storage layer. Every two stacked layers include an inter-gate dielectric layer, a control gate, and a cap layer in sequence. Next, the charge storage layer between the two stacked layers is removed to form a first trench. After spacers are formed at the sidewalls of the two stacked layers and of the first trench, the charge storage layer outside the two stacked layers is removed. Thereafter, a dielectric layer is formed on the substrate. An assist gate is formed between the two stacked layers and a select gate is respectively formed on the sidewalls outside the two stacked layers. A doped region is then formed in the substrate outside the two stacked layers. | 06-04-2009 |
| 20090197400 | METHOD FOR RECYCLING OF ION IMPLANTATION MONITOR WAFERS - A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape. | 08-06-2009 |
| 20090258479 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region. | 10-15-2009 |
| 20100055885 | METHOD OF MAKING LOW WORK FUNCTION COMPONENT - A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value. | 03-04-2010 |
| 20100129997 | ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY PANEL AND METHOD OF FORMING POLYSILICON CHANNEL LAYER THEREOF - An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer. | 05-27-2010 |
| 20100151667 | DOPANT IMPLANTING METHOD AND DOPING APPARATUS - A dopant device includes: a dopant holder that holds Ge which is solid at normal temperature and liquefies the Ge near a surface of the semiconductor melt, the dopant holder including a communicating hole for delivering the liquefied Ge downwardly; a cover portion for covering the Ge held by the dopant holder; and a vent provided on the cover portion for communicating with the outside. A dopant injecting method is carried out using such a dopant device, the dopant injecting method including: loading Ge dopant in a solid state into the doping device; liquefying the solid Ge dopant loaded into the doping device while holding the doping device at a predetermined height from a surface of a semiconductor melt; and doping the semiconductor melt with the liquefied Ge that is flowed from the communicating hole. | 06-17-2010 |
| 20100190323 | Modifying catalytic behavior of nanocrystals - The present invention provides a method of providing a desired catalyst electron energy level. The method includes providing a donor material quantum confinement structure (QCS) having a first Fermi level, and providing an acceptor QCS material having a second Fermi level, where the first Fermi level is higher than the second Fermi level. According to the method the acceptor is disposed proximal to the donor to alter an electronic structure of the donor and the acceptor materials to provide the desired catalyst electron energy level. | 07-29-2010 |
| 20100323507 | SUBSTRATE PROCESSING APPARATUS AND PRODUCING METHOD OF DEVICE - A substrate processor enables realization of a proper process by combining advantages of a remote plasma and a plasma generated in an entire processing chamber. The substrate processor includes a conductive member ( | 12-23-2010 |
| 20110287616 | Bottom anode schottky diode structure and method - This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current. | 11-24-2011 |
| 20120045887 | COMPOSITIONS OF DOPED, CO-DOPED AND TRI-DOPED SEMICONDUCTOR MATERIALS - Semiconductor materials suitable for being used in radiation detectors are disclosed. A particular example of the semiconductor materials includes tellurium, cadmium, and zinc. Tellurium is in molar excess of cadmium and zinc. The example also includes aluminum having a concentration of about 10 to about 20,000 atomic parts per billion and erbium having a concentration of at least 10,000 atomic parts per billion. | 02-23-2012 |
| 20120220111 | INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN - An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes. | 08-30-2012 |
| 20120244689 | SCHOTTKY DIODE WITH CONTROL GATE FOR OPTIMIZATION OF THE ON STATE RESISTANCE, THE REVERSE LEAKAGE, AND THE REVERSE BREAKDOWN - A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode. | 09-27-2012 |
| 20130029481 | TEMPLATED CIRCUITRY FABRICATION - A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate. | 01-31-2013 |
| 20130078787 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for manufacturing a semiconductor device, including the steps of: forming a first semiconductor film ( | 03-28-2013 |
| 20130089974 | METHOD OF MANUFACTURING A NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE - A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer. | 04-11-2013 |
| 20130102136 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P | 04-25-2013 |
| 20130115761 | Methods of Forming a Semiconductor Device - Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern. | 05-09-2013 |
| 20130115762 | METHOD FOR DOPING A SEMICONDUCTOR MATERIAL - A feedstock of semiconductor material is placed in a crucible. A closed sacrificial recipient containing a dopant material is placed in the crucible. The content of the crucible is melted resulting in incorporation of the dopant in the molten material bath. The temperature increase is performed under a reduced pressure. | 05-09-2013 |
| 20130137248 | Doping Carbon Nanotubes and Graphene for Improving Electronic Mobility - A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device. | 05-30-2013 |
| 20130164922 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. The method may include forming an etch target layer on a substrate, forming a carbon layer doped with boron on the etch target layer, a top end portion of the carbon layer having a different boron concentration from a bottom end portion of the carbon layer, patterning the carbon layer to form at least one opening exposing the etch target layer, and etching the exposed etch target layer using the carbon layer as an etch mask. | 06-27-2013 |
| 20130189832 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability. | 07-25-2013 |
| 20130260542 | METHOD FOR IMPROVING WRITE MARGINS OF SRAM CELLS - The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements. | 10-03-2013 |
| 20140024205 | SEMICONDUCTOR STRUCTURE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion. | 01-23-2014 |
| 20140030878 | METHOD OF MAKING LESS ELECTRIC CURRENT DEPENDENCE OF ELECTRIC CURRENT GAIN OF SEMICONDUCTOR DEVICE - An object of the present invention is to amplify the current which varies by a factor of several orders of magnitude with a constant gain without using a complicated circuit. In order to solve the problem, with a semiconductor device includes a first semiconductor region of a first conductivity, a second semiconductor region which is an opposite conductivity opposite to the first conductivity and is in contact with the first semiconductor region and a third semiconductor region which is the first conductivity and is in contact with the second semiconductor region at the second surface, a fourth semiconductor region in contact with the second semiconductor region is provided so as to be separated from the third semiconductor region and enclose the third semiconductor region and an impurity concentration of the fourth semiconductor region is larger than that of the second semiconductor region. | 01-30-2014 |
| 20140051238 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A first resist layer ( | 02-20-2014 |
| 20140057422 | Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate - A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees. | 02-27-2014 |
| 20140154876 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region. | 06-05-2014 |
| 20140179089 | Process for Producing at Least One Silicon-Based Nanoelement in a Silicon Oxide Section and Process for the Manufacture of a Device Employing the Production Process - The process for the production of at least one silicon-based nanoelement ( | 06-26-2014 |
| 20150011079 | METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER - The present invention provides a method for manufacturing a silicon epitaxial wafer, characterized in that a silicon epitaxial layer is formed on an N-type silicon single crystal wafer manufactured by doping with arsenic to set a resistivity to 1.0 to 1.7 mΩcm and further doping with carbon, nitrogen, or both carbon and nitrogen. As a result, there can be provided the method for manufacturing a silicon epitaxial wafer that can suppress occurrence of stacking faults at the time of performing epitaxial growth on the arsenic-doped super-low resistance silicon single crystal wafer. | 01-08-2015 |
| 20150079773 | CONFORMAL DOPING FOR FINFET DEVICES - A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants. | 03-19-2015 |
| 20150333071 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed. | 11-19-2015 |
| 20160093698 | METHOD FOR DOPING A GaN-BASE SEMICONDUCTOR - The method for doping a GaN-base semiconductor to fabricate a p-n junction includes a first step consisting in providing a substrate including a GaN-base semiconductor material layer covered by a silicon-base mask. The method includes a second step of performing implantation of impurities in the mask so as to transfer additional dopant impurities of Si type by diffusion from the mask to the semiconductor material layer to form an n-type area adjacent to a p-type area. Configured heat treatment is then performed to activate the dopant impurities and the additional dopant impurities. | 03-31-2016 |
