| Entries |
| Document | Title | Date |
|---|
| 20080200014 | METHOD OF FORMING A VERTICAL DIODE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved. | 08-21-2008 |
| 20080206968 | Manufacturing method of semiconductor device - To create a laminated film of a silicon oxide film and a silicon nitride film, with large current driving force and large dielectric constant. A manufacturing method of a semiconductor device includes: forming an amorphous silicon film on the silicon oxide film; and forming a single crystal silicon film by annealing the amorphous silicon film. | 08-28-2008 |
| 20080213983 | Method for manufacturing semiconductor device - Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate. | 09-04-2008 |
| 20080233718 | Method of Semiconductor Thin Film Crystallization and Semiconductor Device Fabrication - A method of fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a patterned heat retaining layer over the amorphous silicon layer, doping the amorphous silicon layer to form a pair of doped regions in the amorphous silicon layer by using the patterned heat retaining layer as a mask, and irradiating the amorphous silicon layer to activate the pair of doped regions, forming a pair of activated regions, and form a crystallized region between the pair of activated regions. | 09-25-2008 |
| 20080268622 | METHOD FOR MANUFACTURING A CRYSTALLINE SILICON LAYER - A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask. | 10-30-2008 |
| 20080286950 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser light for improving the crystallinity. The concentration of the catalyst metal in the semiconductor film and the location of the region to be added with the catalyst metal are so selected in order that a desired crystallinity and a desired crystal structure such as a vertical crystal growth or lateral crystal growth can be obtained. Further, active elements and driver elements of a circuit substrate for an active matrix type liquid crystal device are formed by such semiconductor devices having a desired crystallinity and crystal structure respectively. | 11-20-2008 |
| 20090004835 | Method for producing semi-conducting material wafers by moulding and directional crystallization - Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by creation of a pressure difference in the device. The mould is preferably coated with a non-wettable anti-adhesive deposit. | 01-01-2009 |
| 20090042372 | Polysilicon Deposition and Anneal Process Enabling Thick Polysilicon Films for MEMS Applications - A method of forming a thick polysilicon layer for a MEMS inertial sensor includes forming a first amorphous polysilicon film on a substrate in an elevated temperature environment for a period of time such that a portion of the amorphous polysilicon film undergoes crystallization and grain growth at least near the substrate. The method also includes forming an oxide layer on the first amorphous polysilicon film, annealing the first amorphous polysilicon film in an environment of about 1100° C. or greater to produce a crystalline film, and removing the oxide layer. Lastly, the method includes forming a second amorphous polysilicon film on a surface of the crystalline polysilicon film in an elevated temperature environment for a period of time such that a portion of the second amorphous polysilicon film undergoes crystallization and grain growth at least near the surface of the crystalline polysilicon film. | 02-12-2009 |
| 20090061602 | METHOD FOR DOPING POLYSILICON AND METHOD FOR FABRICATING A DUAL POLY GATE USING THE SAME - A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced. | 03-05-2009 |
| 20090081855 | FABRICATION METHOD OF POLYSILICON LAYER - A fabrication method of a polysilicon layer is provided. First, a substrate is provided. Then, an amorphous silicon layer is formed on the substrate. After that, a patterned photomask having a light transmitting area and a light shielding area is provided, and the amorphous silicon layer is irradiated with a light by using the patterned photomask as a mask, wherein the amorphous silicon layer corresponding to the light transmitting area is transformed into a hydrophilic amorphous silicon layer, and the amorphous silicon layer corresponding to the light shielding area remains as a hydrophobic amorphous silicon layer. Next, a hydrophilic metal catalyst is provided and disposed on the hydrophilic amorphous silicon layer. After that, an annealing process is performed to transform the hydrophilic metal catalyst into a metal catalyst layer, and the metal catalyst layer reacts with the amorphous silicon layer to form a polysilicon layer. | 03-26-2009 |
| 20090124064 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 05-14-2009 |
| 20090124065 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 05-14-2009 |
| 20090124066 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 05-14-2009 |
| 20090130827 | INTRINSIC AMORPHOUS SILICON LAYER - Embodiments of the present invention may include an improved thin film solar cell device that is formed by sequentially depositing an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer during the p-i-n or n-i-p junction formation process. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction thin film solar cell devices. | 05-21-2009 |
| 20090155988 | ELEMENT OF LOW TEMPERATURE POLY-SILICON THIN FILM AND METHOD OF MAKING POLY-SILICON THIN FILM BY DIRECT DEPOSITION AT LOW TEMPERATURE AND INDUCTIVELY-COUPLED PLASMA CHEMICAL VAPOR DEPOSITION EQUIPMENT THEREFOR - A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma and substrate bias voltage. Furthermore, the atom structure of the poly-silicon thin film is aligned in regular arrangement by making use of the induction layer having optimal orientation and lattice constant close to that of the silicon, thus raising the crystallization quality of the poly-silicon thin film and reducing the thickness of the incubation layer. | 06-18-2009 |
| 20090170293 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a support in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming a semiconductor film in the cavity, and thermally oxidizing the semiconductor film. | 07-02-2009 |
| 20090221135 | Rapid Heating With Nanoenergetic Materials - The present process for rapidly heating and cooling a target material without damaging the substrate upon which it has been deposited. More specifically, target material is coated onto a first substrate. A self-propagating nanoenergetic material is selected that combusts at temperatures sufficient to change the target material and creates a flame front that propagates sufficiently quickly that the first substrate is not substantially heated. The nanoenergetic material is deposited on the target material, such that the target material and the nanoenergetic material is sandwiched between the substrate and the target material. The nanoenergetic material is ignited and the flame front of the nanoenergetic material is allowed to propagate over the second substrate and change the target material. | 09-03-2009 |
| 20100075486 | FORMATION OF SINGLE CRYSTAL SEMICONDUCTOR NANOWIRES - A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure. | 03-25-2010 |
| 20100087051 | LOCAL CRYSTALLIZATION BY HEAT TREATMENT - Disclosed is a crystallization apparatus capable of locally crystallizing amorphous silicon. The crystallization apparatus includes a heat emission part, a support part and a roller. The heat emission part emits heat upon receiving a heat emission source. The support part supports the heat emission part and provides the heat emission source to the heat emission part. The roller receives the heat emission part and has at least one opening to provide heat to a target (e.g., amorphous silicon). Local crystallization is performed without causing damage to a substrate. | 04-08-2010 |
| 20100144128 | Phase Change Memory Cell and Manufacturing Method - A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion. | 06-10-2010 |
| 20100184276 | LOW-TEMPERATURE FORMATION OF POLYCRYSTALLINE SEMICONDUCTOR FILMS VIA ENHANCED METAL-INDUCED CRYSTALLIZATION - A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices. | 07-22-2010 |
| 20100197121 | Methods of manufacturing semiconductor devices - A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure. | 08-05-2010 |
| 20100323503 | INTEGRATED EMITTER FORMATION AND PASSIVATION - Embodiments of the present invention provide a method for forming an emitter region in a crystalline silicon substrate and passivating the surface thereof by depositing a doped amorphous silicon layer onto the crystalline silicon substrate and thermally annealing the crystalline silicon substrate while oxidizing the surface thereof. In one embodiment, the deposited film is completely converted to oxide. In another embodiment, the doped amorphous silicon layer deposited onto the crystalline silicon substrate is converted into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited during emitter formation. In one embodiment, at least a portion of the converted crystalline silicon is further converted into silicon dioxide during the emitter surface passivation. | 12-23-2010 |
| 20110014781 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed. | 01-20-2011 |
| 20110021008 | Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications - Embodiments of the present invention provide a method for converting a doped amorphous silicon layer deposited onto a crystalline silicon substrate into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited. Additional embodiments of the present invention provide depositing a dielectric passivation layer onto the amorphous silicon layer prior to the conversion. A temperature gradient is provided at a temperature and for a time period sufficient to provide a desired p-n junction depth and dopant profile. | 01-27-2011 |
| 20110053355 | Plasma apparatus and method of fabricating nano-crystalline silicon thin film - A plasma apparatus having a chamber, a set of arc electrodes and a substrate holder is provided. The set of arc electrodes disposed within the chamber has an anode and a cathode, wherein an arc forming space is formed between the anode and the cathode. The anode and the cathode respectively have a crystallized silicon target. The crystallized silicon target of the anode is disposed on an end facing to that of the cathode, wherein the resistance of the crystallized silicon targets is smaller than 0.01 Ω·cm. The substrate holder is disposed within the chamber and has a carrying surface, wherein the carrying surface is face to the arc forming space. Besides, a method of fabricating nano-crystalline silicon thin film is also provided. By using the plasma apparatus, a nano-crystalline silicon thin film with high quality is formed. | 03-03-2011 |
| 20110097881 | Method of Forming Mono-Crystalline Germanium or Silicon Germanium - A method is presented for forming mono-crystalline germanium or silicon germanium in a trench. In an embodiment, the method comprises providing a substrate comprising at least one active region that is adjacent to two insulating regions, forming in the active region a trench having a width of less than 100 nm, and forming in the trench a fill layer at a temperature of less than 450° C. that comprises germanium or silicon germanium and substantially fills the trench. The method further comprises heating the fill layer to a temperature sufficient to substantially melt the fill layer and allowing re-crystallization of the substantially melted fill layer, thereby forming mono-crystalline germanium or silicon germanium in the trench. In an embodiment, the method further comprises forming a mono-crystalline germanium or silicon germanium fin by removing at least a portion of the insulating regions. The mono-crystalline fin may be comprised in a fin field-effect-transistor (finFET). | 04-28-2011 |
| 20110151651 | METHOD FOR FORMING INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 06-23-2011 |
| 20110207302 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SUBSTRATE PROCESSING METHOD AND APPARATUS - Embodiments described herein relate to improving the quality of a substrate and the performance of a semiconductor device, which is caused by contaminates or particles being engrained into a substrate with a silicon film formed thereon, and forming a silicon film with a small surface roughness. Provided is a semiconductor device manufacturing method that includes forming a silicon film on a substrate, supplying an oxidation seed onto the substrate, performing heat treatment on the silicon film, modifying the surface layer of the silicon film into an oxidized silicon film, and removing the oxidized silicon film. | 08-25-2011 |
| 20110217828 | METHODS OF FABRICATING VERTICAL SEMICONDUCTOR DEVICE UTILIZING PHASE CHANGES IN SEMICONDUCTOR MATERIALS - A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening. | 09-08-2011 |
| 20110237055 | Methods of Manufacturing Stacked Semiconductor Devices - A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer. | 09-29-2011 |
| 20120034766 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film. | 02-09-2012 |
| 20120058631 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer. | 03-08-2012 |
| 20120164819 | APPARATUS AND METHOD FOR MANUFACTURING POLY-SI THIN FILM - An apparatus and method for fabricating a polycrystalline silicon (poly-Si) thin film are provided. The apparatus includes a chamber, a substrate stage installed at a lower portion in the chamber and on which a substrate including a conductive layer is located, a power application unit installed at an upper portion in the chamber and including an electrode terminal applying power to the conductive layer, and a conductive pad interposed between the electrode terminal and the conductive layer. Thus, it is possible to form a uniform electric field on the conductive layer, and to form a good quality of poly-Si thin film. | 06-28-2012 |
| 20120190180 | Thin film crystallization device and method for making a polycrystalline composition - A method for making a polycrystalline composition, wherein the method includes the steps of a) preparing a precursor material, b) heating the precursor material to a reaction temperature in the presence of a precursor vapor supplied from a source at a preselected partial pressure, for a sufficient time to initiate an interaction between the precursor material and the precursor vapor to form a heated precursor material, and c) cooling the heated precursor material at a predetermined cooling rate, optionally, in the presence of the precursor vapor supplied at a partial pressure, to yield the polycrystalline composition. A device for implementing the method of the present invention is also provided | 07-26-2012 |
| 20130023111 | LOW TEMPERATURE METHODS AND APPARATUS FOR MICROWAVE CRYSTAL REGROWTH - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain an epitaxial layer made by providing a semiconductor substrate containing an upper surface with a single-crystal structure; forming a layer on the upper surface of the substrate, wherein the layer comprises substantially the same material as the semiconductor substrate and comprises an amorphous or polycrystalline structure; and heating the layer using low temperature microwaves to change the amorphous structure to a single-crystal structure. The epitaxial layer can also be made by providing the semiconductor substrate with an upper surface of a single-crystal material and then forming an epitaxial layer on the substrate upper surface using microwaves at a wafer temperature less than about 550° C. In-situ or implanted dopants in the epitaxial layer can be activated using the same, or separate, low temperature microwave processing. Other embodiments are described. | 01-24-2013 |
| 20130252406 | Techniques for drying and annealing thermoelectric powders - Embodiments of the invention include a method of producing a low contaminant, stoichiometrically controlled semiconductor material, the method comprising providing a colloidal suspension of a plurality of colloidally grown semiconductor nanocrystals, providing an inorganic ligand structure around a surface of the semiconductor nanocrystals of the plurality of semiconductor nanocrystals, drying the colloidal suspension into a powder, and pre-annealing the powder into a semiconductor material. | 09-26-2013 |
| 20130267081 | POST-DEPOSITION SOFT ANNEALING - The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated. | 10-10-2013 |
| 20130273724 | METHOD FOR CRYSTALLIZING AMORPHOUS SILICON THIN FILM AND METHOD FOR FABRICATING POLY CRYSTALLINE THIN FILM TRANSISTOR USING THE SAME - Provided is a method of crystallizing an amorphous silicon thin film transistor and a method of fabricating a polycrystalline thin film transistor using the same, in which the polycrystalline thin film transistor indicating leakage current characteristics of a level that is applicable for active matrix organic light emitting diode displays (AMOLEDs) can be manufactured by using a silicide seed induced lateral crystallization (SILC) method. The amorphous silicon thin film transistor crystallizing method includes the steps of: forming an amorphous silicon layer on a substrate; forming an active region by patterning the amorphous silicon layer; forming a crystallization induced metal layer in both a source region and a drain region that are placed on both side ends of the active region; forming a number of dot-shaped metal silicide seeds on the surfaces of the source region and the drain region made of amorphous silicon by removing the crystallization induced metal layer; and crystallizing the active region formed of the amorphous silicon layer by heat-treating the substrate by using the metal silicide seeds as crystallization seeds. | 10-17-2013 |
| 20130344688 | Atomic Layer Deposition with Rapid Thermal Treatment - Provided are methods and apparatus for atomic layer deposition of a film with rapid thermal treatment. Methods described can be used to convert an amorphous film to form an epitaxial film with rapid thermal treatment or to selectively deposit a film on a portion of a substrate. A thermal element in the apparatus is capable of globally or locally changing the temperature of the amorphous film or a portion of the amorphous film by temporarily rapidly raising the temperature of the amorphous film converting the film to an epitaxial film. | 12-26-2013 |
| 20130344689 | METHOD FOR PROCESSING SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SUBSTRATE PROCESSING APPARATUS - A method for processing a substrate having an insulating film in at least a portion of a surface thereof, a source portion, a drain portion, and a gate portion thereon, and a monocrystalline silicon-based structure in a gate channel disposed under the gate portion. The method for processing a substrate includes: growing amorphous doped silicon and monocrystalline doped silicon by supplying at least silicon-containing gas and doping gas; and monocrystallizing the amorphous doped silicon by using the monocrystalline doped silicon as a seed by heating the amorphous doped silicon and the monocrystalline doped silicon. | 12-26-2013 |
| 20140087547 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ANNEALING DEVICE, AND ANNEALING METHOD - According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the semiconductor layer and forming an amorphous layer on the surface of the semiconductor layer, and a heat treatment process using microwave annealing at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. and single crystallizes the amorphous layer. | 03-27-2014 |
| 20140094023 | FABRICATING METHOD OF SEMICONDUCTOR CHIP - A fabricating method of a semiconductor chip includes the following steps. Firstly, a substrate is provided, wherein an amorphous semiconductor layer is formed in a first surface of the substrate. Then, a first metal layer is formed on the amorphous semiconductor layer. Then, a thermal-treating process is performed to result in a chemical reaction between the first metal layer and a part of the amorphous semiconductor layer, thereby producing an amorphous metal semiconductor compound layer. Afterwards, a microwave annealing process is performed to recrystallize the amorphous metal semiconductor compound layer as a polycrystalline metal semiconductor compound layer. | 04-03-2014 |
| 20140256117 | METHODS OF FORMING EPITAXIAL LAYERS - A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer. | 09-11-2014 |
| 20150140793 | NANOWIRE DEVICES - A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device. | 05-21-2015 |
| 20160020093 | PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS - In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated. | 01-21-2016 |
| 20160020094 | PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS - In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated. | 01-21-2016 |
| 20160071728 | FILM FORMING METHOD AND FILM FORMING APPARATUS - There is provided a method of forming a film on a surface to be processed of a workpiece, the method including: accommodating the workpiece with a single-crystallized substance formed on the surface to be processed, into a processing chamber; supplying a crystallization suppressing process gas into the processing chamber such that a crystallization of the single-crystallized substance formed on the surface to be processed is suppressed; and supplying a source gas into the processing chamber to form an amorphous film on the surface to be processed of the workpiece. | 03-10-2016 |
| 20160141176 | PROCESS FOR FORMING SILICON-FILLED OPENINGS WITH A REDUCED OCCURRENCE OF VOIDS - In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon surface. In some embodiments, an opening in a substrate may be filled with silicon, such as amorphous silicon. The deposited silicon may have interior voids. This deposited silicon is then exposed to a silicon mobility inhibitor, such as an oxygen-containing species and/or a semiconductor dopant. The deposited silicon fill is subsequently annealed. After the anneal, the voids may be reduced in size and, in some embodiments, this reduction in size may occur to such an extent that the voids are eliminated. | 05-19-2016 |
