| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438312000 |
Having heterojunction
| 27 |
| 438311000 |
On insulating substrate or layer (i.e., SOI type)
| 23 |
| 438353000 |
Including isolation structure
| 12 |
| 438329000 |
Including passive device (e.g., resistor, capacitor, etc.) | 5 |
| 20090253239 | METHOD AND STRUCTURE FOR BALLAST RESISTOR - A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates. | 10-08-2009 |
| 20130157433 | METHODS FOR FORMING ELECTROSTATIC DISCHARGE PROTECTION CLAMPS WITH INCREASED CURRENT CAPABILITIES - Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1| 06-20-2013 | |
| 20140106532 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 04-17-2014 |
| 20140273390 | Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Bipolar Junction Transistors and Memory Arrays - Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×10 | 09-18-2014 |
| 20160020147 | IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR - A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric. | 01-21-2016 |
| 438322000 |
Complementary bipolar transistors | 5 |
| 20170236824 | COMPLEMENTARY BIPOLAR SRAM | 08-17-2017 |
| 20090203183 | Method for integrating SIGE NPN and Vertical PNP Devices - According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device. | 08-13-2009 |
| 20090305477 | INTEGRATED CIRCUIT ARRANGEMENT WITH NPN AND PNP BIPOLAR TRANSISTORS AND CORRESPONDING PRODUCTION METHOD - An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout. | 12-10-2009 |
| 20100009507 | METHOD OF CONSTRUCTING CMOS DEVICE TUBS - The present invention provides a method of fabricating an integrated circuit comprising at least one bipolar transistor and at least one field effect transistor. The method includes implanting a dopant species of a first type in a semiconductor layer that is doped with a dopant of a second type opposite the first type to form at least one sinker that contacts at least one collector of said at least one bipolar transistor. The method also includes applying heat to cause the dopant species to diffuse outwards to form at least one doped extension of said at least one sinker and forming said at least one field effect transistor in the doped extension. | 01-14-2010 |
| 20140235026 | METHODS FOR FORMING ELECTROSTATIC DISCHARGE PROTECTION CLAMPS WITH INCREASED CURRENT CAPABILITIES - Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt | 08-21-2014 |
| 438378000 |
Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.) | 5 |
| 20080280414 | Systems and Methods for Fabricating Vertical Bipolar Devices - Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and an emitter region may be defined by a CMOS mask. | 11-13-2008 |
| 20080311722 | METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
| 20090075447 | Method and fabricating a mono-crystalline emitter - Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench ( | 03-19-2009 |
| 20110250728 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 μm or more and 0.3 μm or less from the back surface of the semiconductor layer. | 10-13-2011 |
| 20120115299 | BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR - A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation. | 05-10-2012 |
| 438335000 |
Forming lateral transistor structure | 4 |
| 20080227261 | METHOD FOR FABRICATING A TRANSISTOR STRUCTURE - The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. | 09-18-2008 |
| 20140363945 | METHODS FOR FABRICATING IMPROVED BIPOLAR TRANSISTORS - Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness. | 12-11-2014 |
| 20110053331 | BIPOLAR TRANSISTOR FINFET TECHNOLOGY - This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus. | 03-03-2011 |
| 20120264270 | METHODS FOR FORMING HIGH GAIN TUNABLE BIPOLAR TRANSISTORS - Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process. | 10-18-2012 |
| 438350000 |
Forming base region of specified dopant concentration profile (e.g., inactive base region more heavily doped than active base region, etc.) | 4 |
| 20090181513 | VERTICAL ORGANIC TRANSISTOR - A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process. | 07-16-2009 |
| 20100129975 | BASE FOR A NPN BIPOLAR TRANSISTOR - An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance. | 05-27-2010 |
| 20140134820 | METHODS FOR PRODUCING BIPOLAR TRANSISTORS WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 05-15-2014 |
| 20140329368 | BIPOLAR TRANSISTOR WITH EMBEDDED EPITAXIAL EXTERNAL BASE REGION AND METHOD OF FORMING THE SAME - The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance. | 11-06-2014 |
| 438364000 |
Self-aligned | 3 |
| 20090155974 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A CHANNEL EXTENDING VERTICALLY - In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers. | 06-18-2009 |
| 20140308792 | METHODS OF PRODUCING BIPOLAR TRANSISTORS HAVING EMITTER-BASE JUNCTIONS OF VARYING DEPTHS AND/OR DOPING CONCENTRATIONS - Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements. | 10-16-2014 |
| 20090203184 | Self-Aligned Epitaxially Grown Bipolar Transistor - The illumination system has a light source ( | 08-13-2009 |
| 438342000 |
Having multiple emitter or collector structure | 3 |
| 20110039391 | Fabricating Bipolar Junction Select Transistors for Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 02-17-2011 |
| 20130130462 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector. | 05-23-2013 |
| 20130149831 | METHODS FOR FABRICATING BIPOLAR TRANSISTORS WITH IMPROVED GAIN - Insufficient gain in bipolar transistors ( | 06-13-2013 |
| 438343000 |
Mesa or stacked emitter | 3 |
| 20080227262 | Vertically base-connected bipolar transistor - Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor. | 09-18-2008 |
| 20110312146 | BIPOLAR DEVICE HAVING BURIED CONTACTS - This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector. | 12-22-2011 |
| 20150024570 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 01-22-2015 |
| 438345000 |
Walled emitter | 1 |
| 20140162426 | Bipolar transistor manufacturing method, bipolar transistor and integrated circuit - Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate ( | 06-12-2014 |
| 438341000 |
Using epitaxial lateral overgrowth | 1 |
| 20140113426 | TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE - Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R | 04-24-2014 |
| 438340000 |
Making plural bipolar transistors of differing electrical characteristics | 1 |
| 20110151638 | Method of fabricating semiconductor device - There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes. | 06-23-2011 |
| 438328000 |
Including diode | 1 |
| 20090029518 | Method of fabricating schottky barrier diode - Disclosed is a method of fabricating a Schottky barrier diode, which comprises the steps of laminating an N | 01-29-2009 |
| 438310000 |
Gettering of semiconductor substrate | 1 |
| 20130210210 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 08-15-2013 |
