| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438311000 | On insulating substrate or layer (i.e., SOI type) | 23 |
| 20080220583 | SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES - Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body. | 09-11-2008 |
| 20080261371 | VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION - The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided. | 10-23-2008 |
| 20090298250 | BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD - A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed. | 12-03-2009 |
| 20100003800 | BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR - Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided. | 01-07-2010 |
| 20100167488 | INTEGRATED CIRCUIT COMPRISING A GRADUALLY DOPED BIPOLAR TRANSISTOR AND CORRESPONDING FABRICATION PROCESS - An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone | 07-01-2010 |
| 20100178746 | METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) - A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>. | 07-15-2010 |
| 20100279481 | CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS - An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( | 11-04-2010 |
| 20110034001 | METHOD OF MAKING BIPOLAR TRANSISTOR - A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region ( | 02-10-2011 |
| 20110143513 | METHODS OF FORMING A SHALLOW BASE REGION OF A BIPOLAR TRANSISTOR - The disclosed subject matter provides a method of forming a bipolar transistor. The method includes depositing a first insulating layer over a first layer of material that is doped with a dopant of a first type. The first layer is formed over a substrate. The method also includes modifying a thickness of the first oxide layer based on a target dopant profile and implanting a dopant of the first type in the first layer. The dopant is implanted at an energy selected based on the modified thickness of the first insulating layer and the target dopant profile. | 06-16-2011 |
| 20120028432 | METHODS OF FORMING A BIPOLAR TRANSISTOR - A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor. | 02-02-2012 |
| 20120289018 | SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area. | 11-15-2012 |
| 20130171796 | METHODS OF FABRICATING TRENCH GENERATED DEVICE STRUCTURES - Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite to the conductivity type of the semiconductor substrate. Dopant is transported outwardly from the sacrificial plug into the semiconductor substrate surrounding the trench to define a doped region of the second conductivity type in the semiconductor substrate. A first contact is formed that extends through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region. A second contact is formed that extends through the semiconductor and insulator layers to the doped region. | 07-04-2013 |
| 20130260526 | SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT - A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively. | 10-03-2013 |
| 20130288447 | VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter. | 10-31-2013 |
| 20140017871 | Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths - An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well. | 01-16-2014 |
| 20140073106 | LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY - A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process. | 03-13-2014 |
| 20140170829 | LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY - A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process. | 06-19-2014 |
| 20140357043 | LATERAL BIPOLAR TRANSISTORS HAVING PARTIALLY-DEPLETED INTRINSIC BASE - A bipolar junction transistor (BJT) and method for fabricating such. The transistor includes an emitter region, a collector region, and an intrinsic-base region. The intrinsic-base region is positioned between the emitter region and the collector region. Furthermore, the physical separation between the emitter region and the collector region is less than the sum of a base-emitter space-charge region width and a base-collector space-charge region width at the transistor's standby mode. | 12-04-2014 |
| 20140370683 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |
| 20150104920 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region. | 04-16-2015 |
| 20150380513 | BIPOLAR TRANSISTOR DEVICE FABRICATION METHODS - A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions. | 12-31-2015 |
| 20160005730 | ESD Protection with Asymmetrical Bipolar-Based Device - An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device. | 01-07-2016 |
| 20160099334 | BIPOLAR TRANSISTOR MANUFACTURING METHOD - A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench. | 04-07-2016 |
