| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438296000 | Dielectric isolation formed by grooving and refilling with dielectric material | 61 |
| 20080220582 | Semiconductor device and method of fabricating the same - According to the present invention, there is provided a semiconductor device fabrication method, comprising:
| 09-11-2008 |
| 20080233700 | Methods of forming integrated circuitry - The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems. | 09-25-2008 |
| 20080242035 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n | 10-02-2008 |
| 20080268599 | STRUCTURE AND METHOD FOR A TRIPLE-GATE TRANSISTOR WITH REVERSE STI - Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 10-30-2008 |
| 20080311718 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film. The manufacturing method of a semiconductor device includes the steps of: forming a contact hole and exposing a nickel silicide layer from the bottom of the contact hole; forming a thermal reaction Ti film by a thermal reaction using a TiCl | 12-18-2008 |
| 20090061586 | Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped. | 03-05-2009 |
| 20090098702 | Method to Form CMOS Circuits Using Optimized Sidewalls - A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed. | 04-16-2009 |
| 20090111232 | SEMICONDUCTOR DEVICE HAVING DECOUPLING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer. | 04-30-2009 |
| 20090191683 | METHOD OF FORMING TRANSISTOR HAVING CHANNEL REGION AT SIDEWALL OF CHANNEL PORTION HOLE - According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern. | 07-30-2009 |
| 20090203180 | MOS TRANSISTOR HAVING PROTRUDED-SHAPE CHANNEL AND METHOD OF FABRICATING THE SAME - A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion. | 08-13-2009 |
| 20090209077 | SEMICONDUCTOR DEVICE CHANNEL TERMINATION - A semiconductor device has a channel termination region for using a trench | 08-20-2009 |
| 20090209078 | Semiconductor Integrated Circuit Device and Method of Manufacturing the Same - Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon. | 08-20-2009 |
| 20090221121 | Method of Forming a Salicide Layer for a Semiconductor Device - Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask. | 09-03-2009 |
| 20090258468 | MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION STRESS - The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor ( | 10-15-2009 |
| 20090275184 | Fabricating Method of Semiconductor Device - Disclosed is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes removing a part of an isolation layer from a semiconductor substrate such that an active area of the semiconductor substrate protrudes from the isolation layer; rounding edge portions of the active area; forming a gate insulating layer and a gate electrode on the active area; and forming source and drain impurity areas in the active area adjacent to sides of the gate electrode. | 11-05-2009 |
| 20090298248 | Two-Step STI Formation Process - A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate. | 12-03-2009 |
| 20090317956 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface. | 12-24-2009 |
| 20090317957 | Method for Forming Isolation Structures - A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body. | 12-24-2009 |
| 20100068859 | METHOD OF MANUFACTURING A FET GATE - A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region | 03-18-2010 |
| 20100075477 | Method of Manufacturing Semiconductor Device - An embodiment of the disclosure relates to a method of manufacturing semiconductor devices. According to this embodiment, a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer are sequentially formed over a semiconductor substrate. Isolation trenches are formed by etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate. Isolation structures are formed by filling the isolation trenches with an insulating layer. Upper sidewalls of the isolation trenches are exposed by etching predetermined thickness of the isolation structures. Ion implantation regions are formed in the exposed upper sidewalls of the isolation trenches by performing an ion implantation process. | 03-25-2010 |
| 20100129972 | BIT LINE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF - A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench. | 05-27-2010 |
| 20100261328 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING FIN-FIELD EFFECT TRANSISTOR - A semiconductor device includes an element isolation region formed in a semiconductor substrate, an active region surrounded by the element isolation region, and a gate electrode formed in one direction to cross the active region. The semiconductor substrate includes two gate trenches formed in parallel to a major axis direction of the active region in the active region, and a fin-shaped part which is located between the two gate trenches. The gate electrode is buried in the two gate trenches and formed on the fin-shaped part. The fin-shaped part serves as a channel region. A fin field effect transistor in which a width of the channel region is smaller than a gate length is thereby obtained. | 10-14-2010 |
| 20100285651 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer. | 11-11-2010 |
| 20110014769 | MANUFACTURING METHOD FOR PLANAR INDEPENDENT-GATE OR GATE-ALL-AROUND TRANSISTORS - The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction. | 01-20-2011 |
| 20110045648 | METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION - Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon. | 02-24-2011 |
| 20110117714 | Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation - A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer. | 05-19-2011 |
| 20110223734 | METHODS OF FORMING AN ARRAY OF MEMORY CELLS, METHODS OF FORMING A PLURALITY OF FIELD EFFECT TRANSISTORS, METHODS OF FORMING SOURCE/DRAIN REGIONS AND ISOLATION TRENCHES, AND METHODS OF FORMING A SERIES OF SPACED TRENCHES INTO A SUBSTRATE - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed. | 09-15-2011 |
| 20110244645 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film. | 10-06-2011 |
| 20120003805 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode. | 01-05-2012 |
| 20120009752 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface. | 01-12-2012 |
| 20120021581 | SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements. | 01-26-2012 |
| 20120220095 | SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL - A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon. | 08-30-2012 |
| 20120329231 | Semiconductor Processing Methods, And Methods Of Forming Isolation Structures - Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline. | 12-27-2012 |
| 20130017659 | FABRICATING METHOD OF SEMICONDUCTOR DEVICEAANM LIU; An-ChiAACI Tainan CityAACO TWAAGP LIU; An-Chi Tainan City TW - A fabricating method of a semiconductor device includes the following actions. A substrate having a silicon gate structure formed thereon is provided, and then a modification process is performed on a surface of the silicon gate structure to render the surface from being hydrophobic to be hydrophilic. After that, a mask is formed on the substrate. In succession, a dopant implantation process is performed using the silicon gate structure after the modification process and the mask. After the dopant implantation process, a cleaning process which includes a wet cleaning process is performed to remove the mask. In the above fabricating method, because the surface of the silicon gate structure is modified into a hydrophilic surface, therefore it is easy to remove the residues after the dopant implantation process using the wet cleaning process. | 01-17-2013 |
| 20130045580 | METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES - Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas. | 02-21-2013 |
| 20130045581 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method of manufacturing semiconductor devices. The method includes a step of performing a chemical mechanical planarization processing on a poly-silicon layer before fabricating a poly-silicon gate such that the poly-silicon gates obtained in subsequent fabrication process are kept at the same height, which thus avoids the silicon nitride residues issue that occurs in the prior art. Therefore, the present invention is capable of enhancing product yield of semiconductor devices and improving device performances. | 02-21-2013 |
| 20130078778 | SEMICONDUCTOR PROCESS - A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed. | 03-28-2013 |
| 20130189821 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED DAMAGE TO SHALLOW TRENCH ISOLATION (STI) REGIONS - Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device on a semiconductor substrate includes selectively implanting dopant ions to form implants in the semiconductor substrate. Trenches are formed in the semiconductor substrate and the trenches are filled with an isolation material. An upper surface of the isolation material is established substantially coplanar with the semiconductor substrate. In the method, the implants and the isolation material are then simultaneously annealed. | 07-25-2013 |
| 20130288445 | SEMICONDUCTOR DEVICE WITH GATE ELECTRODE INCLUDING A CONCAVE PORTION - A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region. | 10-31-2013 |
| 20140024192 | Method for Fabricating Semiconductor Device - A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate. | 01-23-2014 |
| 20140051222 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, patterning the first insulating film to form a first and a second opening, forming a first sidewall film on side walls of the first and the second openings, etching the semiconductor substrate with the first insulating film and the first sidewall film as a mask to dig down the first opening and the second opening, removing the first sidewall film to form a first offset portion in the first opening and a second offset portion in the second opening, the first and the second offset portion including a part of a surface of the semiconductor substrate, and etching a bottom of the first opening with the first insulating film as a mask. | 02-20-2014 |
| 20140141587 | TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION - A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure. | 05-22-2014 |
| 20140154855 | METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES - Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit. | 06-05-2014 |
| 20140213031 | FinFETs and Methods for Forming the Same - A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material. | 07-31-2014 |
| 20140302657 | METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE - A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer. A sidewall spacer is formed within the opening. A first trench is etched into the epitaxial layer through the opening. A dopant source layer is formed on the surface of the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant source layer and the spacer are removed. A sacrificial layer is then filled into the first trench. The sacrificial layer and the epitaxial layer within the first region are etched away to form a second trench. | 10-09-2014 |
| 20140342524 | INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD - An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon. | 11-20-2014 |
| 20140349458 | Source and Drain Dislocation Fabrication in FinFETs - A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region. | 11-27-2014 |
| 20140357039 | METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE - On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers. | 12-04-2014 |
| 20140363943 | Contact Structure of Semiconductor Device Priority Claim - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer. | 12-11-2014 |
| 20150044842 | Integrating Junction Formation of Transistors with Contact Formation - A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region. | 02-12-2015 |
| 20150050792 | EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES - Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench. | 02-19-2015 |
| 20150064871 | Forming Source/Drain Zones with a Delectric Plug Over an Isolation Region Between Active Regions - An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry. | 03-05-2015 |
| 20150357231 | Method of Manufacturing Semiconductor Device - To provide a semiconductor device having improved reliability at an improved production yield. | 12-10-2015 |
| 20150364575 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric. | 12-17-2015 |
| 20150380297 | METHOD FOR MANUFACTURING MOSFET - Provided is a method for manufacturing a MOSFET, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the MOSFET; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions. | 12-31-2015 |
| 20160013094 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | 01-14-2016 |
| 20160064403 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to improve the reliability of a semiconductor device. | 03-03-2016 |
| 20160118401 | METHODS OF FORMING A THIN FILM AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING USING THE SAME - Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms. | 04-28-2016 |
| 20160126143 | METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE - This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs. | 05-05-2016 |
| 20160155671 | Method of Forming a Semiconductor Device | 06-02-2016 |
| 20160196983 | SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE | 07-07-2016 |
