Entries |
Document | Title | Date |
20080268598 | SEMICONDUCTOR DEVICE HAVING SILICIDE LAYERS AND METHOD OF FABRICATING THE SAME - Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims. | 10-30-2008 |
20080286931 | SEMICONDUCTOR DEVICE INCLUDING FIELD-EFFECT TRANSISTOR USING SALICIDE (SELF-ALIGNED SILICIDE) STRUCTURE AND METHOD OF FABRICATING THE SAME - An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region. | 11-20-2008 |
20090047767 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a silicon substrate, a strain-inducing layer, a silicon layer, a FET, and an isolation region. On the silicon substrate, the strain-inducing layer is provided. On the strain-inducing layer, the silicon layer is provided. The strain-inducing layer induces lattice strain in a channel region of the FET in the silicon layer. The silicon layer includes the FET. The FET includes a source/drain region, an SD extension region, a gate electrode and a sidewall. The source/drain region and the strain-inducing layer are spaced from each other. Around the FET, the isolation region is provided. The isolation region penetrates the silicon layer so as to reach the strain-inducing layer. | 02-19-2009 |
20090203179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At least one of the source region and the drain region has a first low concentration region and a high concentration region. Also, the semiconductor device of the present invention is provided with a second low concentration region of the second conduction type between a channel stopper region formed below the element isolation and the source region, and between the channel stopper region and the drain region. The semiconductor layer immediately below the gate electrode projects to the channel stopper region side along the gate electrode, and the semiconductor layer and the channel stopper region make contact with each other. | 08-13-2009 |
20090239349 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor. | 09-24-2009 |
20090269898 | METAL OXIDE SEMICONDUCTOR (MOS) FIELD EFFECT TRANSISTOR HAVING TRENCH ISOLATION REGION AND METHOD OF FABRICATING THE SAME - A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region. | 10-29-2009 |
20090298247 | Method and device for providing a contact structure - An approach is provided for semiconductor devices and methods for providing a contact structure. Methods may include forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the active region and being disposed on the device isolation pattern, and forming a first doped region and a second doped region in the active region adjacent to opposite sides of the gate pattern, respectively. The methods may include sequentially forming a gate spacer and a sacrificial spacer on both sidewalls of the gate pattern, forming an interlayer dielectric on the entire surface of the substrate, planarizing the interlayer dielectric to expose the gate spacer and the sacrificial spacer, removing a portion of the sacrificial spacer to form a groove to expose the first doped region, and forming a contact structure in the groove. | 12-03-2009 |
20100167484 | Gate line edge roughness reduction by using 2P/2E process together with high temperature bake - A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process. | 07-01-2010 |
20100261327 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n | 10-14-2010 |
20100323486 | TRIPLE-GATE TRANSISTOR WITH REVERSE SHALLOW TRENCH ISOLATION - Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 12-23-2010 |
20110039388 | Multi-Thickness Semiconductor With Fully Depleted Devices And Photonic Integration - Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region. | 02-17-2011 |
20110053328 | METHOD FOR MANUFACTURING MEMORY CELL - In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type. | 03-03-2011 |
20110097867 | METHOD OF CONTROLLING GATE THICKNESSES IN FORMING FUSI GATES - A method of fabricating a semiconductor device is provided. In one embodiment, a gate structure is formed on a substrate, the gate structure having a gate dielectric layer and a first polysilicon layer formed above the gate dielectric layer. A passivation layer is formed above the first polysilicon layer. A second polysilicon layer is formed above the passivation layer. The second polysilicon layer and the passivation layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed. | 04-28-2011 |
20110171802 | Methods of Making a Semiconductor Memory Device - One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held. | 07-14-2011 |
20110183485 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for making a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions. | 07-28-2011 |
20110195554 | Strain Bars in Stressed Layers of MOS Devices - A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region. | 08-11-2011 |
20110212589 | Semiconductor device manufacturing method - A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; | 09-01-2011 |
20110312143 | STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor. | 12-22-2011 |
20110312144 | NOVEL METHOD TO ENHANCE CHANNEL STRESS IN CMOS PROCESSES - The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current. | 12-22-2011 |
20120070952 | REMOVING METHOD OF A HARD MASK - A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate. | 03-22-2012 |
20120115297 | METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR - The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics. | 05-10-2012 |
20120164807 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region. | 06-28-2012 |
20120220094 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer. | 08-30-2012 |
20120309155 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region. | 12-06-2012 |
20130040434 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 02-14-2013 |
20130065371 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide. | 03-14-2013 |
20130089961 | Methods of Forming Semiconductor Devices Including an Epitaxial Layer and Semiconductor Devices Formed Thereby - Methods of forming a semiconductor device are provided. The methods may include forming an epitaxial layer by growing a crystalline layer using a semiconductor source gas in a reaction chamber, and by etching the crystalline layer using an etching gas in the reaction chamber. | 04-11-2013 |
20130130459 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 05-23-2013 |
20130137235 | MOS TRANSISTOR USING STRESS CONCENTRATION EFFECT FOR ENHANCING STRESS IN CHANNEL AREA - A MOS transistor ( | 05-30-2013 |
20130143376 | CURRENT IN ONE-TIME-PROGRAMMABLE MEMORY CELLS - A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I | 06-06-2013 |
20130149829 | DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR - In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks. | 06-13-2013 |
20130171792 | Methods for Semiconductor Regrowth - A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region. | 07-04-2013 |
20130171793 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING ELECTROLYZED SULFURIC ACID (ESA) - A method of forming a semiconductor device may include forming a metal layer on a silicon portion of a substrate, and reacting the metal layer with the silicon portion to form a metal silicide. After reacting the metal layer, unreacted residue of the metal layer may be removed using an electrolyzed sulfuric acid solution. More particularly, a volume of sulfuric acid in the electrolyzed sulfuric acid solution may be in the range of about 70% to about 95% of the total volume of the electrolyzed sulfuric acid solution, a concentration of oxidant in the electrolyzed acid solution may be in the range of about 7 g/L to about 25 g/L, and a temperature of the electrolyzed sulfuric acid solution may be in the range of about 130 degrees C. to about 180 degrees C. | 07-04-2013 |
20130189820 | SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR - A method for manufacturing a semiconductor includes:
| 07-25-2013 |
20130252391 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 09-26-2013 |
20130260525 | LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION - A static random access memory fabrication method includes forming a gate stack on a substrate, forming isolating spacers adjacent the gate stack, the isolating spacers and gate stack having a gate length, forming a source and drain region adjacent the gate stack, which generates an effective gate length, wherein the source and drain regions are formed from a low extension dose implant that varies a difference between the gate length and the effective gate length. | 10-03-2013 |
20130288444 | High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same - An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device. | 10-31-2013 |
20130337624 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure. | 12-19-2013 |
20130344672 | SEMICONDUCTOR DEVICE WITH SELF-BIASED ISOLATION - A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region. | 12-26-2013 |
20140024191 | METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES - A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist. | 01-23-2014 |
20140065782 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure. | 03-06-2014 |
20140087536 | SEMICONDUCTOR STRUCTURE THAT REDUCES THE EFFECTS OF GATE CROSS DIFFUSION AND METHOD OF FORMING THE STRUCTURE - Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration. | 03-27-2014 |
20140154854 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide. | 06-05-2014 |
20140179081 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer. | 06-26-2014 |
20140206169 | Methods of Fabricating Semiconductor Device Using Nitridation of Isolation Layers - A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess. | 07-24-2014 |
20140322883 | METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates. | 10-30-2014 |
20150311310 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer. | 10-29-2015 |
20150349089 | TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION - In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided. | 12-03-2015 |
20160013307 | Dynamic Threshold MOS and Methods of Forming the Same | 01-14-2016 |
20160020322 | METHODS OF FORMING STRAINED SEMICONDUCTOR CHANNELS - In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein. | 01-21-2016 |
20160027701 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells. | 01-28-2016 |
20160035860 | CONTACT TECHNIQUES AND CONFIGURATIONS FOR REDUCING PARASITIC RESISTANCE IN NANOWIRE TRANSISTORS - Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor. | 02-04-2016 |
20160035864 | FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS - After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process. | 02-04-2016 |
20160064486 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations. | 03-03-2016 |
20160099155 | METHODS OF FORMING A HARD MASK LAYER AND OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N | 04-07-2016 |
20160118266 | Method for Fabricating Semiconductor Devices - The invention relates to a method for fabricating a semiconductor device. The method comprises forming a first etching layer and a second etching layer stacked on a substrate, and forming a recess region by etching the first and second etching layers under plasma generated from an etching gas including a compound. The compound comprises at least one of 1,1,1,2,3,3-hexafluoropropane, 2,2,2-trifluoroethane-1-thiol, 1,1,1,3,3-pentafluoropropane, 1,1,2,2,3-pentafluoropropane and 1,1,2,2-tetrafluoro-1-iodoethane, 2,3,3,3-tetrafluoropropene and 1,1-difluoroethene. | 04-28-2016 |
20160118477 | METHOD OF PRODUCTION OF FIELD-EFFECT TRANSISTOR WITH LOCAL SOURCE/DRAIN INSULATION - A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region and along the sidewalls of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. | 04-28-2016 |
20160133509 | Methods and Apparatus of Metal Gate Transistors - In some embodiments, a method of manufacturing a device includes providing a first device with an isolation area, an active area next to the isolation area, a metal gate above the isolation area and the active area, and a dielectric layer above the metal gate. The method also includes forming a first opening within a conductive layer of the metal gate, and a second opening within the dielectric layer. The first opening and the second opening are connected, and are of a first shape. The method further includes expanding the first opening to form a third opening of a second shape within the conductive layer of the metal gate and beneath the dielectric layer, forming a first contact part by filling the third opening, and forming a second contact part by filling the second opening, the first contact part being connected to the second contact part. | 05-12-2016 |
20160181399 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES | 06-23-2016 |
20160204223 | HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES | 07-14-2016 |