Class / Patent application number | Description | Number of patent applications / Date published |
438114000 | Utilizing a coating to perfect the dicing | 57 |
20080233679 | Semiconductor package with plated connection - A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material. | 09-25-2008 |
20080242000 | WAFER-LEVEL-CHIP-SCALE PACKAGE AND METHOD OF FABRICATION - A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate. | 10-02-2008 |
20080261352 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 10-23-2008 |
20080280397 | METHOD FOR MANUFACTURING STRIP LEVEL SUBSTRATE WITHOUT WARPAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate. | 11-13-2008 |
20080305579 | Method for fabricating semiconductor device installed with passive components - A method for fabricating a semiconductor device installed with passive components is provided. The method includes: having at least a passive component make a bridge connection between a ground circuit and a power circuit of each of a plurality of substrate units; electrically connecting a conductive circuit on a cutting path between substrate units to the ground circuit and the power circuit, and forming a short circuit loop; or electrically connecting the conductive circuit on the cutting path between the substrate units to the power circuit and the ground circuit via bonding wires, and forming a short circuit loop; or applying a wire bonding machine to form a stud bump on the power circuit, and then forming a short circuit loop via the power circuit and ground loop of the wire bonding machine; therefore, via the short circuit loop, the passive component is capable of releasing electricity filled therein from previous plasma clean process of substrate units and chips; and grounding the chips and the substrate units and electrically connecting powers and signals to prevent the chips from being damaged due to sudden current impulses resulting from the discharging of the passive components when the passive components are electrically connected to the chips. | 12-11-2008 |
20090004779 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced. | 01-01-2009 |
20090004780 | Method for Fabricating Semiconductor Chip - After a film layer | 01-01-2009 |
20090011543 | Enhanced Reliability of Wafer-Level Chip-Scale Packaging (WLCSP) Die Separation Using Dry Etching - An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die. | 01-08-2009 |
20090075428 | ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE - Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure. | 03-19-2009 |
20090093088 | ROLL-ON ENCAPSULATION METHOD FOR SEMICONDUCTOR PACKAGES - A low-viscosity resin is deposited using an apparatus with a movable and heatable wheel and a heater stage. A tape is provided, which includes a layer ( | 04-09-2009 |
20090098683 | METHOD FOR CUTTING SOLID-STATE IMAGE PICKUP DEVICE - A method for cutting a solid-state image pickup device with high accuracy and high quality is provided which does not cause any chipping and prevents damages to a wafer surface. A temporary bonding agent is coated to a back surface of a glass cover plate which is opposite to the surface having a spacer, and a transparent protective wafer having a surface to which an adhesive sheet having a reducible adhesive strength is attached is adhered to the surface of the glass cover plate to which the temporary bonding agent is coated, with the adhesive sheet facing to the glass cover plate surface. The adhered glass cover plate and protective wafer are cut from the surface of the glass cover plate to the temporary bonding agent. After a CCD wafer is bonded to the cut glass cover plate, the protective wafer, the adhesive sheet, and the temporary bonding agent are peeled off, and the CCD wafer is cut to obtain individual chips. In this way, a cutting of a solid-state image pickup device with high accuracy and high quality is achieved without any damage to a wafer surface. | 04-16-2009 |
20090098684 | Method of Producing a Thin Semiconductor Chip - A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips. | 04-16-2009 |
20090209066 | DIE BONDING METHOD AND DIE BONDER - In a die bonding method, a bonding film is stuck to a rear surface of a wafer and to a dicing tape stuck to a dicing frame. The wafer is thus supported by the dicing frame. Predetermined dividing lines are completely cut and the bonding film is incompletely cut to leave a cut-residual portion. The dicing tape is stretched to break the cut-remaining portion. The die to which the bonding film is stuck is picked up from the dicing tape and bonded to a mount-targeted substrate. | 08-20-2009 |
20090233402 | WAFER LEVEL IC ASSEMBLY METHOD - A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced. | 09-17-2009 |
20090298233 | Method for Fabricating Semiconductor Elements - The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements. | 12-03-2009 |
20090298234 | METHOD OF FABRICATING SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR WAFER, AND METHOD OF SAWING THE SEMICONDUCTOR WAFER - A method of fabricating a semiconductor chip package, in which a protection layer is formed on a scribe lane of a wafer including a plurality of semiconductor chips, an encapsulation layer is formed on the semiconductor chips and the protection layer, and at least two types of lasers having different respective wavelengths are sequentially irradiated to the scribe lane so as to separate the semiconductor chips. Therefore, the wafer can be protected from the laser that is used to saw the encapsulation layer. | 12-03-2009 |
20090311831 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. As a part of the method, one surface of a substrate is molded with resin where the substrate and the resin are heated in a first heating process and maintained in a flat condition. The substrate and the resin are returned to room temperature while being maintained in the flat condition after the first heating process. The resin is cut after the substrate and the resin are returned to room temperature from a surface of the resin that is opposite the surface of the resin where the substrate contacts the resin. The substrate is left intact when the resin is cut. Thereafter, the substrate is separated. | 12-17-2009 |
20100029045 | PACKAGING AN INTEGRATED CIRCUIT DIE WITH BACKSIDE METALLIZATION | 02-04-2010 |
20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 06-24-2010 |
20100233856 | METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices, the second lead forming the second external electrode; and cutting the sealing member between the plurality of semiconductor devices to separate the plurality of semiconductor devices from each other. | 09-16-2010 |
20100261314 | THERMOSETTING DIE BONDING FILM - The present invention has been made and an object thereof is to provide a thermosetting die-bonding film which can remarkably reduce working hours at the time of die bonding of a semiconductor chip, and a dicing die-bonding film including the thermosetting die-bonding film and a dicing film layered to each other. The present invention relates to a thermosetting die-bonding film used to produce a semiconductor device, comprising a thermosetting catalyst in a non-crystalline state in an amount within a range from 0.2 to 1 part by weight based on 100 parts by weight of an organic component in the film. | 10-14-2010 |
20110003435 | ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE - Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure. | 01-06-2011 |
20110039372 | MEMS PACKAGE AND A METHOD FOR MANUFACTURING THE SAME - A method is provided for manufacturing a plurality of packages. The method comprises the steps of: applying a means for adhering two or more covers to a substrate; positioning the two or more covers onto the substrate to create one or more channels bounded by the two or more covers and the substrate; coupling the covers to the substrate; depositing a material into the one or more channels; performing a process on the material to affix the material; and singulating along the channels to create the plurality of packages. | 02-17-2011 |
20110097852 | WAFER PROCESSING METHOD WITHOUT OCCURRENCE OF DAMAGE TO DEVICE AREA - A wafer processing method of processing a wafer having on a front surface a device area where a plurality of devices are formed by being sectioned by predetermined dividing lines, and an outer circumferential redundant area surrounding the device area, includes the steps of: sticking a protection tape to the front surface of the wafer; holding a protection tape side of the wafer by a rotatable chuck table, positioning a cutting blade on a rear surface of the wafer, and rotating the chuck table to cut a boundary portion between the device area and the outer circumferential redundant area to form a separation groove; grinding only the rear surface of the wafer corresponding to the device area to form a circular recessed portion to leave the ring-like outer circumferential redundant area as a ring-like reinforcing portion, the wafer being such that the device area and the ring-like outer circumferential redundant area are united by the protection tape; and conveying the wafer supported by the ring-like reinforcing portion via the protection tape. | 04-28-2011 |
20110151624 | Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die - A coating for a microelectronic device comprises a polymer film ( | 06-23-2011 |
20110171782 | METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE HAVING A GROUND PLANE - A method of placing a die includes providing an embedded plane. The embedded plane has a openings, grid lines, and protruding portions. Each of the plurality of openings are surrounding by a subset of the plurality of grid lines. At least one of the protruding portions extends into one of the openings. A die is placed into one of the openings and at least one of the protruding portions bends during such placement so that it is in contact with at least a portion of a minor surface of the die. | 07-14-2011 |
20110183470 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a plurality of element groups over an upper surface of a substrate; forming an insulating film so as to cover the plurality of element groups; selectively forming an opening to the insulating film which is located in a region between neighboring two element groups in the plurality of element groups to expose the substrate; forming a first film so as to cover the insulating film and the opening; exposing the element groups by removing the substrate; forming a second film so as to cover the surface of the exposed element groups; and cutting off between the plurality of element groups so as not to expose the insulating film. | 07-28-2011 |
20110201156 | Method of manufacturing wafer level package including coating resin over the dicing lines - A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units. | 08-18-2011 |
20110207264 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes cutting a part of a resin insulating layer formed on a surface of a semiconductor substrate with a cutting tool. The cutting the part of the resin insulating layer includes cutting a portion of the resin insulating layer that has a surface on which a metal layer is disposed. The cutting the portion of the resin insulating layer is performed in such a manner that, in a stress distribution inside the resin insulating layer along an edge portion of the cutting tool and a peripheral portion of the edge portion, a width at 90% of a maximum value is not more than 1.3 μm. | 08-25-2011 |
20110256668 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus includes forming back surface electrode | 10-20-2011 |
20110306167 | Methods of Packaging Semiconductor Devices Including Bridge Patterns - A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line. | 12-15-2011 |
20110318879 | METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor chip with an adhesive film, which includes: preparing a laminate in which a semiconductor wafer, an adhesive film and a dicing tape are laminated in that order, the adhesive film having a thickness in the range of 1 to 15 μm and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load, and the semiconductor wafer having a section, for dividing the semiconductor wafer into a plurality of semiconductor chips, which is formed by irradiating with laser light; dividing the semiconductor wafer into a plurality of semiconductor chips without dividing the adhesive film, by expanding the dicing tape; and dividing the adhesive film by picking up the plurality of semiconductor chips. | 12-29-2011 |
20120028418 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material layer, a first pressure-sensitive adhesive layer and a second pressure-sensitive adhesive layer stacked in this order, and a film for semiconductor back surface stacked on the second pressure-sensitive adhesive layer of the dicing tape, in which a peel strength Y between the first pressure-sensitive adhesive layer and the second pressure-sensitive adhesive layer is larger than a peel strength X between the second pressure-sensitive adhesive layer and the film for semiconductor back surface, and in which the peel strength X is from 0.01 to 0.2 N/20 mm, and the peel strength Y is from 0.2 to 10 N/20 mm. | 02-02-2012 |
20120064669 | Manufacturing method of semiconductor device - The present invention relates to a method for manufacturing a semiconductor device, containing: a first step of producing a first component part of a semiconductor device on a first surface of a semiconductor wafer; a second step of laminating a support plate to the first surface of the semiconductor wafer, on which the first component part has been produced, through only a silicone resin layer therebetween; a third step of grinding a second surface opposing the first surface of the semiconductor wafer, in the state of the support plate being laminated, and then producing a second component part of the semiconductor device on the ground surface; and a fourth step of peeling off the silicone resin layer from the semiconductor wafer on which the first component part and the second component part have been produced, thereby removing the silicone resin layer and the support plate, and cutting the semiconductor wafer into a chip. | 03-15-2012 |
20120077315 | SEMICONDUCTOR SUBSTRATE CUTTING METHOD - A wafer having a front face formed with a functional device is irradiated with laser light while positioning a light-converging point within the wafer with the rear face of the wafer acting as a laser light incident face, so as to generate multiphoton absorption, thereby forming a starting point region for cutting due to a molten processed region within the wafer along a line. Consequently, a fracture can be generated from the starting point region for cutting naturally or with a relatively small force, so as to reach the front face and rear face. Therefore, when an expansion film is attached to the rear face of the wafer by way of a die bonding resin layer after forming the starting point region for cutting and then expanded, the wafer and die bonding resin layer can be cut along the line. | 03-29-2012 |
20120088333 | DICING/DIE-BONDING FILM, METHOD OF FIXING CHIPPED WORK AND SEMICONDUCTOR DEVICE - A dicing/die-bonding film including a pressure-sensitive adhesive layer ( | 04-12-2012 |
20120149153 | Thin Semiconductor Device Having Embedded Die Support and Methods of Making the Same - Ultra-thin semiconductor devices, including piezoresistive sensing elements can be formed in a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes. | 06-14-2012 |
20120184070 | METHOD FOR FORMING CHIP PACKAGE - An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads. | 07-19-2012 |
20120231583 | DIE-BONDING FILM AND USE THEREOF - A die-bonding film contains a glycidyl-group-containing acrylic copolymer (a) having a weight-average molecular weight of 500,000 or more and a phenolic resin (b), wherein the weight ratio (x/y) of the content x of the glycidyl-group-containing acrylic copolymer (a) to the content y of the phenolic resin (b) is 5 or more and 30 or less, and the die-bonding film substantially does not contain an epoxy resin having a weight-average molecular weight of 5000 or less. Thus, a die-bonding film having a high reliability is provided by which a sufficient adhering strength and an elastic modulus at a high temperature can be obtained before and after curing; the workability is good; air bubbles (voids) do not stay at the boundary between the die-bonding film and the adherend; and the die-bonding film can withstand a humidity resistance solder reflow test. | 09-13-2012 |
20130017650 | COATING FOR A MICROELECTRONIC DEVICE, TREATMENT COMPRISING SAME,AND METHOD OF MANAGING A THERMAL PROFILE OF A MICROELECTRONIC DIE - A coating for a microelectronic device comprises a polymer film ( | 01-17-2013 |
20130217187 | FILM FOR FORMING PROTECTIVE LAYER - The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×10 | 08-22-2013 |
20130316499 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer. | 11-28-2013 |
20140073090 | SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC INSULATING FILM AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film. | 03-13-2014 |
20140141570 | RESIN FILM FORMING SHEET FOR CHIP, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP - A sheet for forming a resin film for a chip, with which a semiconductor device is provided with a gettering function, is obtained without performing special treatment to a semiconductor wafer and the chip. The sheet has a release sheet, and a resin film-forming layer, which is formed on the releasing face of the release sheet, and the resin film-forming layer contains a binder polymer component, a curing component, and a gettering agent. | 05-22-2014 |
20140141571 | INTEGRATED CIRCUIT MANUFACTURING FOR LOW-PROFILE AND FLEXIBLE DEVICES - A process for manufacturing low-profile and flexible integrated circuits includes manufacturing an integrated circuit on a wafer having a thickness larger than the desired thickness. After the integrated circuit is manufactured the integrated circuit may be released with a portion of the wafer leaving a remainder of the bulk portion of the wafer. A second integrated circuit may be manufactured on the remainder of the wafer and the process repeated to manufacture additional integrated circuits from a single wafer. The integrated circuits may be released from the wafer by etching vias through the integrated circuit and into the wafer. The via may be used to start an etch process inside the wafer that undercuts the integrated circuit separating the integrated circuit from the wafer. | 05-22-2014 |
20140248745 | Three-Dimensional Integrated Circuit (3DIC) - An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. | 09-04-2014 |
20150118797 | Method for Singulating Packaged Integrated Circuits and Resulting Structures - A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure. | 04-30-2015 |
20150125997 | Method for Singulating Packaged Integrated Circuits and Resulting Structures - A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure. | 05-07-2015 |
20160042962 | PROCESSING METHOD FOR WORKPIECE - A workpiece has a plurality of low-dielectric-constant insulation films and a metallic pattern stacked on a surface of a semiconductor substrate. Devices are formed in a plurality of regions partitioned by streets formed in a grid pattern. Surfaces of the devices formed on the workpiece are covered with a surface protective member, leaving the streets exposed. A dispersion of abrasive grains in an etching liquid capable of dissolving the metallic pattern is blasted against the workpiece together with compressed gas so as to remove the low-dielectric-constant insulation films and the metallic pattern on the streets, thereby exposing the semiconductor substrate. The workpiece is divided with the semiconductor substrate exposed by the wet blasting step subjected to dry etching so as to divide the workpiece along the streets. | 02-11-2016 |
20160042998 | METHOD OF PROCESSING A SUBSTRATE AND A METHOD OF PROCESSING A WAFER - According to various embodiments, a method of processing a substrate may include: forming a plurality of trenches into a substrate between two chip structures in the substrate, the trenches defining at least one pillar between the two chip structures and a sidewall on each of said two chip structures; disposing an auxiliary carrier on the substrate to hold the chip structures and the at least one pillar; at least partially filling the trenches with encapsulation material to cover the at least one pillar and the sidewalls, thereby at least partially encapsulating the chip structures; removing a portion of the encapsulation material to expose at least a portion of the at least one pillar; and at least partially removing the at least one pillar. | 02-11-2016 |
20160079204 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness. | 03-17-2016 |
20160104626 | METHODS FOR SINGULATING SEMICONDUCTOR WAFER - Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies. | 04-14-2016 |
20160118272 | Interconnect Structure for Wafer Level Package - A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. | 04-28-2016 |
20160126200 | SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRATED ANTENNA FOR WIRELESS APPLICATIONS - A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon: a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip. | 05-05-2016 |
20160141208 | METHOD FOR PROCESSING A SEMICONDUCTOR SUBSTRATE AND A METHOD FOR PROCESSING A SEMICONDUCTOR WAFER - According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies. | 05-19-2016 |
20160190010 | METHOD OF DIVIDING WAFER INTO DIES - A method of dividing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area with no devices formed around the device area, into dies is provided. The method comprises: attaching an adhesive tape for protecting devices on the wafer to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices; connecting a carrier for supporting the adhesive tape to the side of the adhesive tape being opposite to the side in contact with the devices by connecting means; grinding that side of the wafer being opposite the one side for adjusting the wafer height; and cutting the wafer along the division lines. The method is characterized by locating the connecting means completely outward of the device area of the wafer in a top view thereon. | 06-30-2016 |
20160254188 | WAFER DIVIDING METHOD | 09-01-2016 |