Class / Patent application number | Description | Number of patent applications / Date published |
438111000 | Using strip lead frame | 65 |
20080311703 | LEAD FRAME AND A METHOD OF MANUFACTURING THE SAME - A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased. | 12-18-2008 |
20090061563 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS - A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame. | 03-05-2009 |
20090087949 | Method of Making a Microelectronic Package Using an IHS Stiffener - A method of making a microelectronic package. The method includes: providing a carrier; providing a tacky pad on the carrier; placing a die onto the tacky pad such that an active surface of the die adheres to the tacky pad, bonding an IHS onto a backside of the die after placing to form a die-IHS combination, removing the die-IHS combination from the tacky pad; and mounting the die-IHS combination onto a package substrate to form the package. | 04-02-2009 |
20090093086 | LEAD FORMING APPARATUS AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A lead forming apparatus has a function of bending leads of a semiconductor device having leads into a gull wing shape. The lead forming apparatus includes: a lead bending die, as a lower die, allowing thereon placement of the semiconductor device and accepting the leads in the bending leads; a lead bending punch, as an upper die, descending towards the lead bending die so as to move the leads of the semiconductor device towards the lead bending die, to thereby bend the leads into a gull wing shape; and a first stopper specifying the bottom dead center of the lead bending punch, so as to ensure a distance not smaller than thickness of the leads between the bottom surface of the lead bending punch and the top surface of a portion, allowing thereon placement of the leads, of the lead bending die. | 04-09-2009 |
20100120201 | METHOD OF FABRICATING QUAD FLAT NON-LEADED PACKAGE - A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed. | 05-13-2010 |
20100151626 | Locking Feature and Method for Manufacturing Transfer Molded IC Packages - The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics. | 06-17-2010 |
20100233853 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the second direction to move so as to form solder bumps. | 09-16-2010 |
20110237030 | DIE LEVEL INTEGRATED INTERCONNECT DECAL MANUFACTURING METHOD AND APPARATUS - A die level integrated interconnect decal manufacturing method and apparatus for implementing the method. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps. | 09-29-2011 |
20110281397 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components. | 11-17-2011 |
20110306166 | APPARATUS AND METHOD FOR TESTING MULTIPLE INTEGRATED CIRCUIT DEVICES ON A FILM FRAME HANDLER - Film frame assemblies and apparatus for testing and singulating integrated circuit packages, as well as associated methods for forming a film frame assembly, and testing and singulating integrated circuit packages are disclosed. A plurality of leads on a lead frame are cut to form singulated integrated circuit packages. Apparatus and methods are disclosed for mechanically aligning a set of electrical contacts attached to a contactor body with a plurality of leads on a singulated integrated circuit package. | 12-15-2011 |
20120094438 | APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS - A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more parallel passes across the frame. Each heat slug pad has a top exposed surface and a bottom interfacing surface. The bottom interfacing surface typically interfaces with a package. In some embodiments, the top exposed surface is modified. | 04-19-2012 |
20120238058 | METHOD OF PACKAGING SEMICONDUCTOR DIE WITH CAP ELEMENT - A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units. | 09-20-2012 |
20130011969 | METHOD FOR FABRICATING THE FLEXIBLE ELECTRONIC DEVICE - The disclosure provides a method for fabricating the flexible electronic devices, including: providing a first rigid carrier substrate and a second rigid carrier substrate, wherein at least one flexible electronic device is formed between the first rigid carrier substrate and the second rigid carrier substrate, and a plurality of first de-bonding areas, a first flexible substrate, the flexible electronic device, a second flexible substrate, a plurality of second de-bonding areas and the second rigid carrier substrate are formed on the first rigid carrier substrate; performing a first cutting step to cut through the first de-bonding areas; separating the first rigid carrier substrate from the first de-bonding areas; removing the first rigid carrier substrate from the first de-bonding areas; and performing a second cutting step to cut through the second de-bonding areas; separating and removing the second rigid carrier substrate from the second de-bonding areas. | 01-10-2013 |
20160111293 | MANUFACTURING METHOD OF WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE - A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion. | 04-21-2016 |
438112000 | And encapsulating | 51 |
20080286901 | Method of Making Integrated Circuit Package with Transparent Encapsulant - A method for making an IC package with transparent encapsulant includes providing a leadframe, where the leadframe includes a first die pad and a second die pad, disposing a first die on the first die pad and a second die on the second die pad, forming a cavity on the leadframe, where the cavity includes the first die pad and the second die pad, injecting an encapsulant material into the cavity and cutting the injected encapsulant material and the leadframe to form a first IC package and a second IC package. The encapsulant material is transparent for visible wavelengths. The injection of the encapsulant material is performed at an encapsulant temperature ranging from 140° C. to 160° C. | 11-20-2008 |
20090023248 | METHOD OF PACKAGING A SEMICONDUCTOR DIE - A method of packaging a semiconductor die includes the steps of providing a flange ( | 01-22-2009 |
20090053855 | Indented lid for encapsulated devices and method of manufacture - A method for providing improved gettering in a vacuum encapsulated device is described. The method includes forming a plurality of small indentation features in a device cavity formed in a lid wafer. The gettering material is then deposited over the indentation features. The indentation features increase the surface area of the getter material, thereby increasing the volume of gas that the getter material can absorb. This may improve the vacuum maintained within the vacuum cavity over the lifetime of the vacuum encapsulated device. | 02-26-2009 |
20090068792 | MANUFACTURING PROCESS FOR A CHIP PACKAGE STRUCTURE - A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated. | 03-12-2009 |
20090068793 | MANUFACTURING PROCESS FOR A CHIP PACKAGE STRUCTURE - A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated. | 03-12-2009 |
20090075427 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 03-19-2009 |
20090233401 | THIN QUAD FLAT PACKAGE WITH NO LEADS (QFN) FABRICATION METHODS - Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material. | 09-17-2009 |
20100068852 | Method of Manufacturing A Semiconductor Device - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 03-18-2010 |
20110039371 | FLIP CHIP CAVITY PACKAGE - A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages. | 02-17-2011 |
20110059577 | MANUFACTURING METHOD OF LEADFRAME AND SEMICONDUCTOR DEVICE - In order to remove plating burrs generated in etching step, there is provided a manufacturing method of semiconductor devices on each of unit leadframes in a leadframe material in which a plurality of the unit leadframes are arranged in plural rows or a single row, wherein at least two types of plating burr removals are conducted after a half-etching is performed onto a front surface side of the leadframe material, using a first plating layer as resist film. | 03-10-2011 |
20110244629 | Packaging Process to Create Wettable Lead Flank During Board Assembly - A method and apparatus are described for fabricating a low-pin-count chip package ( | 10-06-2011 |
20110263077 | METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES INCLUDING SAW SINGULATION - A method of assembling semiconductor devices for surface mounting includes forming an array of lead frames in which supporting frame structures of adjacent lead frames include an intermediate common bar connecting on both its sides with sets of leads of the respective adjacent lead frames. The semiconductor devices are singulated by sawing through the leads on each side of the common bars without sawing the common bars longitudinally. The material sawn off from the common bars in a first direction is removed by washing it away before sawing off the intermediate common bars that run in an orthogonal direction. The supporting frame structures include bars surrounding the array and singulation includes sawing beside the surrounding bars to saw them off before sawing off the intermediate common bars. | 10-27-2011 |
20110294261 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode. | 12-01-2011 |
20120009737 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly. | 01-12-2012 |
20120270368 | MOLD ARRAY PROCESS METHOD TO ENCAPSULATE SUBSTRATE CUT EDGES - Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages. | 10-25-2012 |
20120315727 | Thin Power Package - In one embodiment, a method for manufacturing a power semiconductor package is provided. The method includes attaching a plurality of solders balls onto a power semiconductor device. The plurality of solder balls are attached onto a lead frame using a flip bond processing step. The flip bond processing step bonds the semiconductor device to the lead frame and interconnects the lead frame to the semiconductor device in a single processing step. The semiconductor device, plurality of solder balls, and the lead frame are molded to form the power semiconductor package, wherein semiconductor device is exposed on a first side of the semiconductor package. | 12-13-2012 |
20130005087 | METHOD AND APPARATUS FOR MOLDING SEMICONDUCTOR DEVICE - An apparatus for molding a semiconductor device includes an upper mold chase and a lower mold chase. The mold chases are capable of being aligned with each other, forming spaced cavities for receiving a lead frame array that includes semiconductor dies for encapsulation. The cavities are aligned in spaced, vertical columns and gates are provided at the opening of each column of cavities. A molding compound is passed through the gates and flows uninterrupted through each cavity and encapsulates the semiconductor dies. | 01-03-2013 |
20130017649 | PACKAGING FOR CLIP-ASSEMBLED ELECTRONIC COMPONENTSAANM Touzet; DominiqueAACI Savigne Sous le LudeAACO FRAAGP Touzet; Dominique Savigne Sous le Lude FRAANM Coirault; PascalAACI Ballan-MireAACO FRAAGP Coirault; Pascal Ballan-Mire FR - A system for assembling electronic chips in a package, including a first lead frame defining chip reception areas; and a second lead frame defining chip coverage areas, the frames including, at least at their periphery, pairs of mutually-cooperating elements for maintaining the frames together. | 01-17-2013 |
20130078766 | METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices. | 03-28-2013 |
20130089953 | Wafer Level Packaging Using a Lead-Frame - Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. | 04-11-2013 |
20130203217 | SEMICONDUCTOR DEVICE - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. | 08-08-2013 |
20130210195 | PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) - A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove. | 08-15-2013 |
20130237014 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a technique in which an excessive resin can be stably cut and removed in a molding step. In a step for separating part of a runner leading to a resin-sealing body from the resin-sealing body, the runner is formed by a first runner and a second runner coupled to the first runner and the resin-sealing body. The runner is separated from a middle of the second runner by supporting, with a first supporting portion, the second runner from the side of the second surface of a lead frame, and by pushing down, with a break pin, the first runner in the direction from the side of the first surface of the lead frame toward the side of the second surface thereof, while the resin-sealing body is in a condition of floating in the air. | 09-12-2013 |
20130288432 | METHOD OF MANUFACTURING LEADLESS INTEGRATED CIRCUIT PACKAGES HAVING ELECTRICALLY ROUTED CONTACTS - A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto. | 10-31-2013 |
20130309812 | INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry. | 11-21-2013 |
20130316496 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING NO CHIP PAD - A method of manufacturing a semiconductor package having no chip pad includes preparing a polyimide tape on which an adhesive layer is arranged; forming lead members on the adhesive layer so as to form a plurality of semiconductor packages in a matrix form; attaching the polyimide tape to a carrier; performing wire bonding to mount semiconductor chips on the polyimide tape and connect the lead members and the semiconductor chips; forming an encapsulation member to encapsulate the semiconductor chips, the lead members, and wires; detaching the encapsulation member from the carrier and the polyimide tape; forming conductive layers each on a surface of the lead member exposed through a surface of the encapsulation member; and performing a singulation process on the encapsulation member with the conductive layers formed thereon to define unit semiconductor packages. | 11-28-2013 |
20140087520 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region). | 03-27-2014 |
20140127861 | Semiconductor Packages Utilizing Leadframe Panels with Grooves in Connecting Bars - According to an exemplary implementation, a method includes utilizing a leadframe panel comprising a plurality of leadframe modules, each of the plurality of leadframe modules having a leadframe pad. The leadframe panel has a plurality of bars each having a plurality of grooves, where the plurality of bars connect the plurality of leadframe modules. The method further includes attaching a device to the leadframe pad. The method also includes molding the leadframe panel while leaving a bottom of the leadframe pad exposed. Furthermore, the method includes sawing through the plurality of grooves of the plurality of bars to singulate the plurality of leadframe modules into separate packaged modules. | 05-08-2014 |
20140134799 | WETTABLE LEAD ENDS ON A FLAT-PACK NO-LEAD MICROELECTRONIC PACKAGE - Methods of manufacturing a flat-pack no-lead microelectronic package ( | 05-15-2014 |
20140220738 | LEAD FRAME ARRAY PACKAGE WITH FLIP CHIP DIE ATTACH - A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation. | 08-07-2014 |
20140242755 | MAKING AN INTEGTATED CIRCUIT MODULE WITH DUAL LEADFRAMES - A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe. | 08-28-2014 |
20140357022 | A QFN WITH WETTABLE FLANK - Methods of fabricating a QFN with wettable flank are described. In an embodiment, a leadframe is used which comprises regions of reduced thickness dam bar which extend across an edge of a kerf width and the QFN are formed using film assisted molding with a shaped mold chase that comprises raised portions which correspond in shape and position to the one or more regions of reduced thickness in the leadframe. The shaped mold chase prevents mold compound from filling recesses under the regions of reduced thickness of leadframe and once diced, each QFN has an edge structure which comprises a small step, into which solder will wet where there are exposed plated leads. | 12-04-2014 |
20150147848 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device is manufactured by mounting semiconductor elements on respective die pad portions of a frame. Electrodes on the surface of the semiconductor elements are wire bonded to lead portions of the frame. The die pad portions, semiconductor elements and lead portions are encapsulated with resin, leaving a bottom surface part of the lead portions exposed. The lead portions are partially cut by a rotary blade from an upper side of the resin to form concave parts in the lead portions, which are wet-etched to form exposed lead upper end parts. A plated layer is formed on the lead upper end parts and the lead bottom surface parts. The remaining parts of the lead portions with the plated layer are cut to separate the resin-encapsulated semiconductor device into individual pieces. | 05-28-2015 |
20150303134 | Universal Lead Frame for Flat No-Leads Packages - A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided. | 10-22-2015 |
20150340248 | FABRICATION METHOD OF PACKAGE HAVING ESD AND EMI PREVENTING FUNCTIONS - A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits. | 11-26-2015 |
20150371874 | SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES - The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front. | 12-24-2015 |
20150380384 | Universal Surface-Mount Semiconductor Package - In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam. | 12-31-2015 |
20160005712 | STRUCTURE AND METHOD OF PACKAGED SEMICONDUCTOR DEVICES WITH BENT-LEAD QFN LEADFRAMES - A method for fabricating a semiconductor device package provides a metallic leadframes with a plurality of device sites. Each site including a pad and a plurality of leads with solderable surfaces. At least one set of leads are aligned in a row and are connected by rails to respective leads of an adjacent site. The leads and rails of the row having a surface in a common plane. The strip with the assembled sites and connecting rails are encapsulated in a packaging material, leaving the common-plane lead and rail surfaces un-encapsulated. Trenches are cut between adjacent sites by removing packaging material until reaching the rails. Thus, creating sidewalls of device packages connected by rails. Device packages are singulated from the strip by severing the connecting rails between adjacent sites in approximate halves, leaving a respective rail half as a straight protrusion attached to each lead. The protrusions are bent at an angle away from the common plane towards the package sidewall. | 01-07-2016 |
20160013075 | INTEGRATED CIRCUIT PACKAGE AND PROCESS FOR FABRICATING THE SAME | 01-14-2016 |
20160013122 | METHODS OF FABRICATING QFN SEMICONDUCTOR PACKAGE AND METAL PLATE | 01-14-2016 |
20160043042 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion. | 02-11-2016 |
20160079188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND MOUNTING METHOD OF SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film. | 03-17-2016 |
20160086826 | RESIN-ENCAPSULATD SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading end portions thereof are opposed to the die pad portion, and thin metal wires for connecting together electrodes of the semiconductor element and the lead portions. Those members are partially encapsulated by a resin. A bottom surface part of the die pad portion and a lead bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulation resin. After a cutout part devoid of the encapsulation resin is formed above a lead upper end part, a plating layer is formed on the lead bottom surface part and the lead upper end part. | 03-24-2016 |
20160100490 | MAKING A PLURALITY OF INTEGRATED CIRCUIT PACKAGES - A method of making a plurality of integrated circuit packages provides a metal strip. A first leadframe having a first die pad is formed on the metal strip. Also formed are a first plurality of leads with proximal ends adjacent to the first die pad, free distal ends positioned outwardly from the first die pad, and a first leadframe dam bar intersecting the proximal ends of the first plurality of leads. A second leadframe having a second die pad, a second plurality of leads with proximal ends adjacent to the second die pad and free distal ends positioned outwardly from the second die pad and a second leadframe dam bar intersecting the proximal ends of the second plurality of leads are formed on the metal strip. The free distal ends of said second plurality of leads are aligned with and adjacent to said free distal ends of said first plurality of leads. | 04-07-2016 |
20160126164 | CAVITY PACKAGE WITH PRE-MOLDED CAVITY LEADFRAME - A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow. | 05-05-2016 |
20160172307 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 06-16-2016 |
20160181225 | CORROSION-RESISTANT COPPER BONDS TO ALUMINUM | 06-23-2016 |
20160190095 | SEMICONDUCTOR PACKAGES AND RELATED METHODS - Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages. | 06-30-2016 |
20160379846 | SEMICONDUCTOR PACKAGES SEPARATED USING A SACRIFICIAL MATERIAL - One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages. | 12-29-2016 |
20160379917 | POWER SEMICONDUCTOR PACKAGE DEVICE HAVING LOCKING MECHANISM, AND PREPARATION METHOD THEREOF - A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off. Therefore, the size of the power semiconductor package device is reduced. | 12-29-2016 |
20170236754 | Integrated Clip and Lead and Method of Making a Circuit | 08-17-2017 |