| Entries |
| Document | Title | Date |
|---|
| 20080213941 | Bump-on-Lead Flip Chip Interconnection - A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process. | 09-04-2008 |
| 20080213942 | Method for fabricating semiconductor device and carrier applied therein - This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs. | 09-04-2008 |
| 20080227238 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MULTI-PACKAGE MODULE TECHNIQUES - An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device. | 09-18-2008 |
| 20080233676 | Integrated circuit device with embedded passive component by flip-chip connection and method for manfacturing the same - An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip. | 09-25-2008 |
| 20080241993 | GANG FLIPPING FOR IC PACKAGING - A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine. | 10-02-2008 |
| 20080241994 | Print Mask and Method of Manufacturing Electronic Components Using The Same - A print mask is used to form bumps on barrier metal layers of a wafer. The mask comprises a plurality of elongated perforations disposed in a linear arrangement such that paste can be applied to an object to be printed on via the perforations. Each of the perforations includes an edge disposed along the longitudinal direction, and the edge is inclined with respect to the direction perpendicular to the direction of arranging the perforations. | 10-02-2008 |
| 20080248610 | THERMAL BONDING PROCESS FOR CHIP PACKAGING - The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging. | 10-09-2008 |
| 20080248611 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature. The chip after the second stage can be stacked in the state where there is no warp in the first stage chip, by this, and the quality and reliability of the semiconductor device (semiconductor package) can be improved. | 10-09-2008 |
| 20080268571 | Apparatus for heating chip, flip chip bonder having the apparatus, and method for bonding flip chip using the same - An apparatus for heating a chip includes: a laser generator for emitting a laser beam to a semiconductor chip to heat the semiconductor chip; and a beam intensity adjuster disposed on a laser emission path between the semiconductor chip and the laser generator to equalize the intensity of the laser beam to be emitted to the semiconductor chip. A flip chip bonder having the chip heating apparatus, and a method for bonding a flip chip using the same are also provided. | 10-30-2008 |
| 20080268572 | CHIP PACKAGE - A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. | 10-30-2008 |
| 20080274589 | Wafer-level flip-chip assembly methods - A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors. | 11-06-2008 |
| 20080274590 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of the semiconductor device including a step of forming solder balls on the circuit face of a mother chip, a step of making flip chip bonding of the daughter chip after the step of forming solder balls on the circuit face of the mother chip, and a step of making flip chip bonding of the mother chip on a circuit board using the solder balls. | 11-06-2008 |
| 20080299705 | Chip Scale Package Having Flip Chip Interconnect on Die Paddle - A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed. | 12-04-2008 |
| 20080311701 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package includes the steps of: forming a material layer containing conductive particles on a semiconductor chip having a plurality of bonding pads on the upper surface thereof, baking the material layers to a non-flowing state; attaching the semiconductor chip in a face down manner to a substrate having connecting pads on the location corresponding to the bonding pads by using the material layers containing conductive particles; applying voltage for a electrical signal exchange to the semiconductor chip and the substrate so that the conductive particles are gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate; and curing the conductive particles of the material layers so that the conductive particles gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate to an non-flowing state. | 12-18-2008 |
| 20090004776 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 01-01-2009 |
| 20090023245 | FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD - The invention involves mounting a solder resin composition ( | 01-22-2009 |
| 20090023246 | EMBEDDED CHIP PACKAGE PROCESS - An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer. | 01-22-2009 |
| 20090029504 | WAFER-LEVEL ACA FLIP CHIP PACKAGE USING DOUBLE-LAYERED ACA/NCA - A method of manufacturing a wafer-level flip chip package is capable of being used to produce a flip chip package by directly coating a flip chip package using anisotropic conductive adhesives (ACA) and non conductive adhesives (NCA) in a solution state as a double layer on a wafer. The method can be used to manufacture a non-conductive mixed solution and a conductive mixed solution and directly coat them on a substrate, such that it is possible to: increase productivity; simplify a manufacturing process; suppress a shadow effect; easily perform thickness control that is difficult with the anisotropic conductive adhesive paste or the non-conductive adhesive paste; and obtain the non-conductive layer and the anisotropic conductive layer in an initial state of a B-stage with a level not losing latent of hardening through a simple drying process to volatilize an organic solvent. Above all, the non-conductive layer and the anisotropic conductive layer is sequentially stacked on the substrate formed with the non-solder bump, making it possible to make the selectivity of electrical conduction and the stability of a connection process excellent, shorten process time and costs, and dramatically reduce consumption of the conductive particles which account for a large portion of total production costs. | 01-29-2009 |
| 20090035891 | METHOD AND APPARATUS FOR FLIP-CHIP BONDING - Provided are a laser flip-chip bonding method having high productivity and excellent bonding reliability and a flip-chip bonder employing the same. The flip-chip bonder includes: a bonding stage on which a substrate rests; a bonding head picking up a semiconductor chip and attaching the semiconductor chip to the substrate; and a semiconductor chip heating unit heating the semiconductor chip to a bonding temperature. The semiconductor chip heating unit includes: a laser light source; and a lens assembly refracting a laser beam emitted by the laser light source to a top surface of the semiconductor chip so that a central position of the laser beam varies across the top surface of the semiconductor chip. | 02-05-2009 |
| 20090047754 | PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice | 02-19-2009 |
| 20090075425 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included. | 03-19-2009 |
| 20090087947 | FLIP CHIP PACKAGE PROCESS - A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids. | 04-02-2009 |
| 20090087948 | FLIP CHIP PACKAGE WITH ADVANCED ELECTRICAL AND THERMAL PROPERTIES FOR HIGH CURRENT DESIGNS - A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip. | 04-02-2009 |
| 20090111213 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 04-30-2009 |
| 20090117688 | FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD - A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin | 05-07-2009 |
| 20090142884 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising the steps of (1) applying an underfill composition to a surface of a silicon wafer, (2) dicing the silicon wafer into chips, (3) positioning the chip, and (4) bonding the chip to the substrate, characterized in that
| 06-04-2009 |
| 20090155955 | THERMAL MECHANICAL FLIP CHIP DIE BONDING - A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate. | 06-18-2009 |
| 20090170244 | METHOD FOR MANUFACTURING A FLIP CHIP PACKAGE - A method for manufacturing a flip chip package uses a dipping method to cohere liquid-state stannum onto a plurality of gold bumps of a chip. The gold bumps are correspondingly connected to a plurality of first pads of a substrate so as to connect the chip and the substrate. Finally, a protecting gel layer is disposed between the substrate and the chip, and covers the gold bumps. By utilizing the manufacturing method of the invention, the production cost can be reduced, and the manufacturing method of the invention can apply to processes in which the bump pitch is less than 60 microns. In addition, through the manufacturing method of the invention, the gold bumps are strongly joined with the first pads. Moreover, the manufacturing method of the invention can apply to various processes, so the application has a wide range of uses. | 07-02-2009 |
| 20090170245 | ELECTRONIC APPARATUS MANUFACTURING METHOD - An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of,, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps. | 07-02-2009 |
| 20090197370 | Method and apparatus for manufacturing semiconductor device - There is provided a method and an apparatus for manufacturing a semiconductor device having a lidless and highly reliable flip-chip structure. The method for manufacturing a semiconductor device wherein an underfill resin is filled in a space between a substrate and a semiconductor chip includes injecting a first underfill resin in said space under a first injecting condition; specifying a location where the fillet height of the underfill resin formed on the side of said semiconductor chip does not meet a prescribed standard; and injecting a second underfill resin in a location where the fillet height does not meet the prescribed standard under a second injecting condition. Since the fillet heights can uniformly meet the prescribed standard, the concentration of stress can be avoided, and a semiconductor device having a lidless and highly reliable flip-chip structure can be manufactured. | 08-06-2009 |
| 20090197371 | Integrated Circuit Packaging Using Electrochemically Fabricated Structures - Embodiments of the invention provide methods for packaging integrated circuits and/or other electronic components with electrochemically fabricated structures which include conductive interconnection elements. In some embodiments the electrochemically produced structures are fabricated on substrates that include conductive vias while in other embodiments, the substrates are solid blocks of conductive material, or conductive material containing passages that allow the flow of fluid to maintain desired thermal properties of the packaged electronic components. | 08-06-2009 |
| 20090203169 | FLIP CHIP MOUNTING BODY AND METHOD FOR MOUNTING SUCH FLIP CHIP MOUNTING BODY AND BUMP FORMING METHOD - In a flip chip mounted body in which a semiconductor chip ( | 08-13-2009 |
| 20090203170 | FLIP CHIP MOUNTING METHOD, FLIP CHIP MOUNTING APPARATUS AND FLIP CHIP MOUNTING BODY - A flip chip mounting method includes holding a circuit board ( | 08-13-2009 |
| 20090209062 | Method of manufacturing semiconductor device and the semiconductor device - A method of manufacturing a semiconductor device which can reduce the number of times of resin-injection, thereby facilitating the miniaturization of the semiconductor device, and the semiconductor device. After resin is injected into a space between at least two second semiconductor chips flip-chip joined to a first semiconductor chip through an injection opening, the resin is hardened. | 08-20-2009 |
| 20090239338 | Method of Forming an Interconnect on a Semiconductor Substrate - The present invention relates to a method of forming a wire bond-free conductive interconnect area on a semiconductor substrate. A semiconductor substrate with an electrically conductive protrusion, defining a bond pad, is provided as well as a plurality of carbon nanotubes. The plurality of carbon nanotubes is immobilized on the bond pad by allowing at least one random portion along the length of the carbon nanotubes to attach to the surface of the bond pad. Thus an aggregate of loops of carbon nanotubes is formed on the surface of the bond pad. Thereby a conductive interconnect area is formed on the electrically conductive protrusion without heat treatment. | 09-24-2009 |
| 20090246911 | SUBSTRATE FOR MOUNTING ELECTRONIC COMPONENTS AND ITS METHOD OF MANUFACTURE - A substrate for mounting electronic components includes an insulating layer and a pad formed on a surface of the insulating layer, the pad configured to mount an electronic component to the substrate. A solder bump is formed on the pad and configured to connecting the pad to a bump of an electronic component, the solder bump including a metal as a major component of the solder bump. A metal film is formed on a surface of the solder bump, the metal film comprising a different metal from the major component of said solder | 10-01-2009 |
| 20090258460 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes a film state underfill resin adhering step wherein film state underfill resin in a semi-cured state is adhered on the first surface of the board main body without forming a gap between the first surface of the board main body and the pad; a flattening step wherein an upper surface of the film state underfill resin is flattened; a chip connecting step wherein the semiconductor chip is pressed onto the upper surface of the film state underfill resin after the flattening step so that the semiconductor chip is flip chip connected to the pad; and an underfill resin forming step wherein the film state underfill resin is cured so that the underfill resin is formed between the semiconductor chip and the wiring board. | 10-15-2009 |
| 20090258461 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the eutectic alloy so as a part of the eutectic alloy enters between the wiring and the base substrate. | 10-15-2009 |
| 20090269883 | Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semiconductor Devices - A device has a first semiconductor chip ( | 10-29-2009 |
| 20090269884 | ACTIVE SOCKET FOR FACILITATING PROXIMITY COMMUNICATION - One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads. | 10-29-2009 |
| 20090286355 | FLIP-CHIP PROCESS BY PHOTO-CURING ADHESIVE - A flip-chip process includes the steps of disposing a plurality of spherical contact members on a surface of a wafer; forming a photo-curing adhesive layer on the surface of the wafer, wherein said photo-curing adhesive layer covers a part of each of the spherical contact members to expose the spherical contact members of the photo-curing adhesive layer; solidifying the photo-curing adhesive layer by exposure; cutting the wafer into a plurality of chip units; placing the chip units on a substrate to let the spherical contact members lie against contact points of the substrate; and pressurizing the chip units and then heating the spherical contact potions to enable the spherical contact members to be welded and electrically connected with the chip units and the contact points of the substrate | 11-19-2009 |
| 20090291524 | COMBINED METALLIC BONDING AND MOLDING FOR ELECTRONIC ASSEMBLIES INCLUDING VOID-REDUCED UNDERFILL - A method for forming electronic assemblies includes providing a plurality of IC die each having IC bonding conductors and a workpiece having workpiece bonding conductors. A curable dielectric film is applied to the IC bonding conductors or the workpiece surface. The plurality of IC die are placed on the workpiece surface so that the plurality of IC bonding conductors are aligned to and face the plurality of workpiece bonding conductors to provide a first bonding. The placing is performed at a vacuum level corresponding to a pressure <1 kPa, and at a temperature sufficient to provide tackiness to the curable dielectric film. The plurality of IC die are then pressed to provide a second bonding. A temperature during pressing cures the curable dielectric film to provide an underfill and forms metallic joints between the plurality of IC bonding conductors and the plurality of workpiece bonding conductors. | 11-26-2009 |
| 20090291525 | METHOD FOR FABRICATING ELECTRONIC DEVICE HAVING FIRST SUBSTRATE WITH FIRST RESIN LAYER AND SECOND SUBSTRATE WITH SECOND RESIN LAYER ADHERED TO THE FIRST RESIN LAYER - The electronic device includes a first substrate | 11-26-2009 |
| 20090298227 | METHOD OF FABRICATING A STACKED TYPE CHIP PACKAGE STRUCTURE AND A STACKED TYPE PACKAGE STRUCTURE - A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps. | 12-03-2009 |
| 20090298228 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A resin layer made of thermoplastic resin is formed on a supporting substrate, and then, an insulating layer is formed on the first resin layer. Then, an interlayer connector is formed through the insulating layer and then, a wiring layer is formed on the first resin layer so as to be electrically connected with the interlayer connector. Thereafter, a first semiconductor chip is mounted on the wiring layer. Then, the first resin layer is heated so that the supporting substrate and the insulating layer are relatively shifted one another to shear the first resin layer, thereby separating the supporting substrate and the insulating layer and forming a semiconductor device. | 12-03-2009 |
| 20090298229 | FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip. | 12-03-2009 |
| 20100003785 | STACKED INTEGRATED CIRCUIT ASSEMBLY - In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC. | 01-07-2010 |
| 20100087034 | Method of manufacturing a semicondictor package - A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming a cavity by etching a center portion of a metal oxide layer; mounting a second chip inside the cavity; forming at least one via such that the via penetrates an edge of the metal oxide layer; placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon. | 04-08-2010 |
| 20100093132 | CHIP MODULE FOR COMPLETE POWER TRAIN - A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die. | 04-15-2010 |
| 20100151625 | BURIED VIA TECHNOLOGY FOR THREE DIMENSIONAL INTEGRATED CIRCUITS - A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer. | 06-17-2010 |
| 20100159643 | BONDING IC DIE TO TSV WAFERS - A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks. | 06-24-2010 |
| 20100167466 | SEMICONDUCTOR PACKAGE SUBSTRATE WITH METAL BUMPS - An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method for attaching the package substrate to a printed circuit board (PCB). | 07-01-2010 |
| 20100190293 | Manufacturing Method of Semiconductor Device - The present invention has been achieved reflecting such situation, and its object is to provide a manufacturing method of a semiconductor device capable of continuously performing the mounting process which applies a so-called DBG process and a flip chip bonding method, and can contribute to simplify the manufacturing process and to improve the reliability with no void in the product. The manufacturing method of a semiconductor device according to the present invention comprises:
| 07-29-2010 |
| 20100190294 | METHODS FOR CONTROLLING WAFER AND PACKAGE WARPAGE DURING ASSEMBLY OF VERY THIN DIE - Various exemplary embodiments provide materials and methods for flip-chip packaging a thin TSV semiconductor die, which uses other packaging components, for example, a second die, as a packaging carrier to attach the thin TSV semiconductor die to a package substrate. Warpage and mis-alignment can be reduced or eliminated during the packaging process of the thin TSV die. | 07-29-2010 |
| 20100203675 | FLIP CHIP MOUNTING BODY, FLIP CHIP MOUNTING METHOD AND FLIP CHIP MOUNTING APPARATUS - The flip chip mounted body of the present invention includes: a circuit board ( | 08-12-2010 |
| 20100233851 | SYSTEM FOR IMPROVING FLIP CHIP PERFORMANCE - A system for improving flip chip performance is provided. In one embodiment, the invention relates to an assembly configured to improve performance of a flip chip device, the assembly including a semiconductor die having an active surface and a back surface, the active surface including a plurality of conductive pads, an interposer substrate having a first surface in electrical contact with the active surface of the semiconductor die and a second surface, a space between the active surface of the semiconductor die and the first surface of the interposer substrate, where the space is essentially free of underfill material, and a carrier substrate having a top surface in electrical contact with the second surface of the interposer. | 09-16-2010 |
| 20100279466 | APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR COMPONENTS, METHODS OF MANUFACTURING APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals. The apparatus further includes a second board having a first side laminated to the front side of the first board, a second side, openings through the second board aligned with individual package areas that define die cavities, and arrays of front contacts at the second side electrically coupled to the second backside terminals by interconnects extending through the first board and the second board. | 11-04-2010 |
| 20100291737 | Method of manufacturing semiconductor package - A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs. | 11-18-2010 |
| 20100297812 | METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME - A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked. | 11-25-2010 |
| 20100317152 | METHOD FOR ASSEMBLING STACKABLE SEMICONDUCTOR PACKAGES - A method for assembling a stackable semiconductor package includes providing a substrate having a first surface and a second surface. The first surface includes bond pads and one or more die pads. Conductive bumps are formed on the bond pads and one or more semiconductor dies are attached to the one or more die pads. The first surface of the substrate, the semiconductor dies and the conductive bumps are placed in a side-gate molding cast and a mold material is supplied to the first surface of the substrate to form a stackable semiconductor package. Similarly formed semiconductor packages may be stacked, one on another to form a stacked semiconductor package. | 12-16-2010 |
| 20100330743 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 12-30-2010 |
| 20110003432 | FLIP CHIP MLP WITH FOLDED HEAT SINK - A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board. | 01-06-2011 |
| 20110008933 | DUAL SIDE COOLING INTEGRATED POWER DEVICE MODULE AND METHODS OF MANUFACTURE - An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module. | 01-13-2011 |
| 20110008934 | NEAR CHIP SCALE PACKAGE INTEGRATION PROCESS - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 01-13-2011 |
| 20110008935 | SEMICONDUCTOR DIE PACKAGE INCLUDING LEADFRAME WITH DIE ATTACH PAD WITH FOLDED EDGE - A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe structure and at least a portion of the semiconductor die. The opposite surface is exposed through the molding material and terminal ends of the leads do not extend past lateral edges of the molding material. | 01-13-2011 |
| 20110020983 | FLIP-CHIP MOUNTING METHOD, FLIP-CHIP MOUNTING APPARATUS AND TOOL PROTECTION SHEET USED IN FLIP-CHIP MOUNTING APPARATUS - A flip-chip mounting apparatus has a shield film ( | 01-27-2011 |
| 20110076801 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body. | 03-31-2011 |
| 20110076802 | EMBEDDED CHIP PACKAGE PROCESS - An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole. | 03-31-2011 |
| 20110092021 | METHOD FOR MANUFACTURING PACKAGE SYSTEM INCORPORATING FLIP-CHIP ASSEMBLY - A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle. | 04-21-2011 |
| 20110143498 | SEMICONDUCTOR PACKAGE WITH A SUPPORT STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions. | 06-16-2011 |
| 20110159638 | Method for Making a Chip Package - The present invention relates to a method for making a chip package. The method includes the following steps: (a) providing a substrate having at least one conductive via; (b) disposing the substrate on a carrier; (c) removing part of the substrate, so as to expose the conductive via, and form at least one through via; (d) disposing a plurality of chips on a surface of the substrate, wherein the chips are electrically connected to the through via of the substrate; (e) forming an encapsulation; (f) removing the carrier; (g) conducting a flip-chip mounting process; (h) removing the encapsulation; and (i) forming a protective material. Whereby, the carrier and the encapsulation can avoid warpage of the substrate during the manufacturing process. | 06-30-2011 |
| 20110165732 | Semiconductor Package Having Buss-Less Substrate - A ball grid array device with an insulating substrate ( | 07-07-2011 |
| 20110171779 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween. | 07-14-2011 |
| 20110183464 | DUAL CARRIER FOR JOINING IC DIE OR WAFERS TO TSV WAFERS - A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article. | 07-28-2011 |
| 20110183465 | Array-Molded Package-On-Package Having Redistribution Lines - A semiconductor device with a sheet-like insulating substrate ( | 07-28-2011 |
| 20110183466 | PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice. | 07-28-2011 |
| 20110183467 | PACKAGING METHOD INVOLVING REARRANGEMENT OF DICE - A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice. | 07-28-2011 |
| 20110195544 | SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFOR - The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening. | 08-11-2011 |
| 20110207262 | Method For Manufacturing A Semiconductor Structure - The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips. | 08-25-2011 |
| 20110217812 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING SAME WITH AN INTERPOSER SUBSTRATE - Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a second surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semiconductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit device is described. | 09-08-2011 |
| 20110230012 | METHOD FOR FILLING MULTI-LAYER CHIP-STACKED GAPS - A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity. | 09-22-2011 |
| 20110237028 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes placing a semiconductor chip by flip-chip mounting on a substrate by using an insulating resin adhesive film (NCF) and preventing overflow of the NCF and the intervention of an insulating resin or an inorganic filler between a bump and an electrode during hot pressing. The method also includes temporarily affixing an NCF of a size that is substantially 60 to 100% the area of a region enclosed with a plurality of bumps of the semiconductor chip arranged in a peripheral alignment, and having a minimum melt viscosity of 2×10 | 09-29-2011 |
| 20110256664 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOUNTABLE INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect. | 10-20-2011 |
| 20110275177 | SEMICONDUCTOR PACKAGE HAVING INK-JET TYPE DAM AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed on the pad forming unit of the substrate, a semiconductor chip disposed on the chip mounting unit of the substrate, a dam disposed on the first surface of the substrate between the semiconductor chip and the pad forming unit, and wherein the dam separates at least a portion of the pads from the semiconductor chip. In addition, the semiconductor package further includes an underfill material disposed between an active surface of the semiconductor chip and the first surface of the substrate and wherein an upper surface of the dam is rounded due to surface tension. | 11-10-2011 |
| 20110294260 | Semiconductor package and method of forming the same - Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip. | 12-01-2011 |
| 20120015481 | METHOD OF MANUFACTURING STACK TYPE SEMICONDUCTOR PACKAGE - A method of manufacturing a stack type semiconductor package is provided. A lower semiconductor package including a circuit board on which a semiconductor chip and electrode pads are formed is provided. A plurality of metal pins are adhered and fixed to the electrode pads of the circuit board of the lower semiconductor package, respectively. An upper semiconductor package is vertically stacked on the lower semiconductor package via the metal pins. | 01-19-2012 |
| 20120015482 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 01-19-2012 |
| 20120021564 | Method for packaging semiconductor device - The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased. | 01-26-2012 |
| 20120064668 | METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT - A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed. | 03-15-2012 |
| 20120077312 | FLIP-CHIP BONDING METHOD TO REDUCE VOIDS IN UNDERFILL MATERIAL - Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing. | 03-29-2012 |
| 20120088331 | WAFER LEVEL STACK DIE PACKAGE - This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components. | 04-12-2012 |
| 20120094436 | EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME - A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other. | 04-19-2012 |
| 20120115279 | CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism. | 05-10-2012 |
| 20120135567 | METHODS AND APPARATUSES FOR TRANSFERRING HEAT FROM STACKED MICROFEATURE DEVICES - Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap. | 05-31-2012 |
| 20120135568 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a substrate and a first semiconductor element. The substrate comprises an inner layer conductor and a cavity comprising the bottom surface on which a part of the inner layer conductor is exposed. The first semiconductor element contacts, in the cavity, the inner layer conductor directly or via a good heat conductor material. | 05-31-2012 |
| 20120149150 | VENTED DIE AND PACKAGE - A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly. | 06-14-2012 |
| 20120244662 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component. | 09-27-2012 |
| 20120288996 | METHODS AND APPARATUS FOR APPLYING AN ADHESIVE TO A CIRCUIT BOARD - Methods and apparatus for curing an adhesive on a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes isolating a first portion of a surface of a circuit board from a second portion of the surface with a flexible gasket. An adhesive is applied to the first portion of the surface. The adhesive is thermally cured. The flexible gasket prevents constituents outgassed from the adhesive from contaminating the second portion of the surface. | 11-15-2012 |
| 20120295402 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, FLIP CHIP PACKAGE HAVING THE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE FLIP CHIP PACKAGE - A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer. | 11-22-2012 |
| 20120322205 | METHOD FOR MANUFACTURING WIRING SUBSTRATE - A method for manufacturing a wiring substrate includes forming a first pad and a second pad on one side of a substrate, plating a surface of the second pad to form a bonding pad used for a wire-bonded connection, covering a surface of the first pad with an adhesive layer, adhering solder powder to the adhesive layer, applying flux containing halogen to the substrate, and melting the solder powder and covering the first pad with a solder to form a connection pad used for a flip-chip-connection. The flux has a halogen concentration of less than or equal to 0.15 wt %. | 12-20-2012 |
| 20120322206 | METHOD FOR WAFER LEVEL PACKAGING OF ELECTRONIC DEVICES - A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device. | 12-20-2012 |
| 20130005085 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below. | 01-03-2013 |
| 20130059416 | FLIP-CHIP BGA ASSEMBLY PROCESS - A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate until the flip chip solder bumps on the chip come in contact with the ball grid array substrate, whereby the chip attaches to the ball grid array substrate in an upside-down orientation, and subjecting the chip and the ball grid array substrate to a thermal process whereby the solder spheres reflow and form solder balls and the flip chip solder bumps reflow and form solder joints between the chip and the ball grid array. | 03-07-2013 |
| 20130084678 | Method Of Manufacturing Package-On-Package (Pop) - A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant. | 04-04-2013 |
| 20130102111 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 04-25-2013 |
| 20130115735 | Apparatus and Methods for Molded Underfills in Flip Chip Packaging - Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed. | 05-09-2013 |
| 20130137216 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED ONE ANOTHER - Disclosed herein is a method of manufacturing a semiconductor device that includes stacking a plurality of semiconductor chips to form a first chip laminated body, providing an underfill material to fill gaps between the semiconductor chips so that a fillet portion is formed around the first chip laminated body, and trimming the fillet portion to form a second chip laminated body. | 05-30-2013 |
| 20130157413 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 06-20-2013 |
| 20130178016 | METHODS OF FABRICATING A PACKAGE-ON-PACKAGE DEVICE AND PACKAGE-ON-PACKAGE DEVICES FABRICATED BY THE SAME - Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved. | 07-11-2013 |
| 20130273692 | LEADLESS ARRAY PLASTIC PACKAGE WITH VARIOUS IC PACKAGING CONFIGURATIONS - A leadless integrated circuit (IC) package comprising an IC chip mounted to a die-attach area and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die-attach area are all covered with a molding material, with portions of the electrical contacts and die-attach area protruding from a bottom surface of the molding material. | 10-17-2013 |
| 20130288430 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided. | 10-31-2013 |
| 20130288431 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 10-31-2013 |
| 20130295721 | APPARATUS TO FABRICATE FLIP-CHIP PACKAGES AND METHOD OF FABRICATING FLIP-CHIP PACKAGES USING THE SAME - An apparatus to fabricate a flip-chip package (FCP), and a method of fabricating an FCP using the same. The method includes providing a semiconductor chip such that an active surface on which a bump is formed faces upward, picking up the semiconductor chip using a pickup transfer and rotating the semiconductor chip such that the active surface of the semiconductor chip faces downward, directly transferring the semiconductor chip from the pickup transfer to a mount transfer, and mounting the semiconductor chip on a transfer unit using the mount transfer such that the active surface faces downward. | 11-07-2013 |
| 20130302940 | Graphene Channel-Based Devices and Methods for Fabrication Thereof - Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. | 11-14-2013 |
| 20130302941 | MICROELECTRONIC WORKPIECES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES USING SUCH WORKPIECES - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection. In several embodiments, a microelectronic die can be coupled to the corresponding bond sites carried by the projection in a flip-chip configuration. | 11-14-2013 |
| 20130309811 | WAFER LEVEL PACKAGED GaN POWER DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a GaN-based compound power semiconductor device and a manufacturing method thereof, in which on a GaN power semiconductor element, a contact pad is formed for flip-chip bonding, and a bonding pad of a module substrate to be mounted with the GaN power semiconductor element is formed with a bump so as to modularize an individual semiconductor element. In the disclosed GaN-based compound power semiconductor device, an AlGaN HEMT element is flip-chip bonded to the substrate, so that heat generated from the element can be efficiently radiated. | 11-21-2013 |
| 20130316495 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF - Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed. | 11-28-2013 |
| 20130323883 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 12-05-2013 |
| 20130344654 | Process For Flip-Chip Connection of an Electronic Component - The invention relates to a process for flip-chip connection of an electronic component (D) to a substrate (B), characterized in that it comprises producing at least one interconnect pad (PC) by etching a thick conductive film and bonding it, by means of at least one conductive adhesive, between a receiving pad or area of said electronic component and a receiving pad or area (PAS) of said substrate. | 12-26-2013 |
| 20140017852 | METHODS FOR FLIP CHIP STACKING - A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip. | 01-16-2014 |
| 20140024175 | METHODS FOR PROTECTING A DIE SURFACE WITH PHOTOCURABLE MATERIALS - In a first aspect of the present invention, a method for manufacturing a flip chip package is provided comprising the steps of a) providing a chip having electrically conductive pads on an active surface thereof, b) coating at least a portion the chip with a protectant composition comprising a polymerizable component comprising a thermosetting epoxy resin, at least 50 weight percent of a substantially transparent filler having a coefficient of thermal expansion of less than 10 ppm/° C., a photoinitator, and a solvent carrier, wherein the protectant composition comprises a thixotropic index of less than 1.5, c) masking the coated chip to mask areas where vias through the protectant are desired, d) exposing the masked chip to a light source sufficient to partially crosslink the protectant composition in the unmasked areas, e) removing the uncured portions of the protectant composition thereby creating vias through the protectant composition to the electrically conductive pads on the surface of the chip, f) applying an electrically conductive material to the chip through the vias, wherein the electrically conductive material protrudes from the surface of the protectant composition, and g) heating the chip to a temperature sufficient to reflow the electrically conductive material and thermoset the protectant composition. | 01-23-2014 |
| 20140030849 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 01-30-2014 |
| 20140038354 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board. | 02-06-2014 |
| 20140038355 | Flip-Chip Assembly Process for Connecting Two Components to Each Other - The invention relates to a flip-chip assembly process for connecting two microelectronic components ( | 02-06-2014 |
| 20140045300 | WARPAGE CONTROL IN A PACKAGE-ON-PACKAGE STRUCTURE - The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure. | 02-13-2014 |
| 20140045301 | THROUGH SILICON VIA DIES AND PACKAGES - A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings. | 02-13-2014 |
| 20140057392 | Copper Post Solder Bumps on Substrates - A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill. | 02-27-2014 |
| 20140087519 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices. | 03-27-2014 |
| 20140113411 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip | 04-24-2014 |
| 20140120661 | FLIP CHIP PACKAGING METHOD - Disclosed are various flip chip packaging methods. In one embodiment, a method can include: (i) arranging a plurality of pads on a chip; (ii) arranging a plurality of first connecting structures on the plurality of pads, where each of the first connecting structures comprises a first metal; (iii) arranging a plurality of second connecting structures on the plurality of first connecting structures, where each second connecting structure comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal; and (iv) flipping the chip with the first and second connecting structures and arranging corresponding of the second connecting structures on pads of a substrate to form electrical connection between the chip and the substrate via the first and second connecting structures. | 05-01-2014 |
| 20140120662 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved. The height of the semiconductor device can also be reduced since the upper surface of the semiconductor element is not enclosed with the molding portion. | 05-01-2014 |
| 20140141567 | Flip-chip Semiconductor Chip Packing Method - Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected. | 05-22-2014 |
| 20140141568 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-22-2014 |
| 20140154838 | MOUNTING APPARATUS AND MOUNTING METHOD - In one embodiment the mounting apparatus mounts an upper chip on a lower chip, and thermally presses the upper chip with the lower chip. The mounting apparatus includes a first movement part for mounting the upper chip on the lower chip and preliminarily bonding by thermal pressing, and a second movement part for mainly bonding the plurality of upper chips preliminarily bonded with the plurality of lower chips for a longer time. The second movement part thermally presses the upper chips preliminarily bonded on the lower chip in a state that the upper chips are adsorbed on an adsorption surface parallel to a loading surface of the lower chip on which the upper chips are loaded. | 06-05-2014 |
| 20140162404 | METHOD FOR PACKAGING LOW-K CHIP - Provided is a method for packaging a low-k chip, comprising: attaching onto a carrier wafer a layer of temporary strippable film; arranging inversely a chip ( | 06-12-2014 |
| 20140170810 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film. | 06-19-2014 |
| 20140170811 | METHOD OF FABRICATING A 3D INTEGRATED ELECTRONIC DEVICE STRUCTURE INCLUDING INCREASED THERMAL DISSIPATION CAPABILITIES - A method of fabricating a microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is physically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein. | 06-19-2014 |
| 20140193952 | Methods for Metal Bump Die Assembly - Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating. | 07-10-2014 |
| 20140206141 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die. | 07-24-2014 |
| 20140206142 | FLIP-CHIP WAFER LEVEL PACKAGE AND METHODS THEREOF - An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package. | 07-24-2014 |
| 20140220737 | FLIP-CHIP HYBRIDIZATION OF MICROELECTRONIC COMPONENTS USING SUSPENDED FUSIBLE RESISTIVE CONNECTION ELEMENTS - A method of forming a hybridized device comprising forming a first microelectronic component provided, on a surface, with metal balls, and a second microelectronic component provided, on a surface, with connection elements corresponding to said metal balls, and hybridizing the first and second components to attach the metal balls of the first component to the connection elements of the second component. The manufacturing of the second microelectronic component comprises forming a substrate provided with cavities at the locations provided for the connection elements, and forming resistive elements made of fusible metal respectively suspended above the cavities. The hybridizing of the first and second components comprises transferring the first component onto the second component to have the metal balls rest on the suspended resistive elements, and circulating an electric current through the resistive elements to melt said elements. | 08-07-2014 |
| 20140235017 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. | 08-21-2014 |
| 20140242752 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. | 08-28-2014 |
| 20140242753 | FLIP CHIP PACKAGING METHOD, AND FLUX HEAD MANUFACTURING METHOD APPLIED TO THE SAME - Flip chip packaging methods, and flux head manufacturing methods used in the flip chip packaging methods may be provided. In particular, a flip chip packaging method including printing flux on a pad of a printed circuit board (PCB), mounting the die in a flip chip manner on the PCB such that a bump of the die faces the pad of the PCB, and bonding the bump of the die to the pad of the PCB using the flux may be provided. | 08-28-2014 |
| 20140248743 | SEMICONDUCTOR MEMORY MODULES AND METHODS OF FABRICATING THE SAME - The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon. | 09-04-2014 |
| 20140273349 | Power Module Having Stacked Flip-Chip and Method for Fabricating the Power Module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 09-18-2014 |
| 20140295618 | Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding - Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package. | 10-02-2014 |
| 20140295619 | BUMP, METHOD FOR FORMING THE BUMP, AND METHOD FOR MOUNTING SUBSTRATE HAVING THE BUMP THEREON - A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer. | 10-02-2014 |
| 20140295620 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED ONE ANOTHER - Disclosed herein is a method of manufacturing a semiconductor device that includes stacking a plurality of semiconductor chips to form a first chip laminated body, providing an underfill material to fill gaps between the semiconductor chips so that a fillet portion is formed around the first chip laminated body, and trimming the fillet portion to form a second chip laminated body. | 10-02-2014 |
| 20140302640 | FCoC (Flip Chip on Chip) Package and Manufacturing Method thereof - A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit. | 10-09-2014 |
| 20140322866 | Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package. | 10-30-2014 |
| 20140342504 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING, AND ELECTRONIC DEVICE MANUFACTURING APPARATUS - According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other. | 11-20-2014 |
| 20150050778 | METHOD AND APPARATUS FOR PRODUCING SEMICONDUCTOR DEVICE - Disclosed is a method for producing a semiconductor device in which solder joints are made between a semiconductor chip with bumps and a substrate with electrodes corresponding to the bumps through a thermosetting adhesive layer, the method including the successive steps of: (A) forming a thermosetting adhesive layer in advance on a surface including bumps of the semiconductor chip; (B) laying a surface on the thermosetting adhesive layer side of the semiconductor chip, on which the thermosetting adhesive layer is formed, and a substrate one upon another, followed by pre-bonding using a heat tool to obtain a pre-bonded laminate; and (C) interposing a protective film having a thermal conductivity of 100 W/mK or more between the heat tool and a surface on the semiconductor chip side of the pre-bonded laminate, melting a solder between the semiconductor chips and the substrate and simultaneously curing the thermosetting adhesive layer using the heat tool. There is provided a method and an apparatus for producing a semiconductor device, which is capable of making a satisfactory joint without causing catching of a resin of an adhesive film between bumps and electrode pads. | 02-19-2015 |
| 20150147846 | NO FLOW UNDERFILL OR WAFER LEVEL UNDERFILL AND SOLDER COLUMNS - A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another | 05-28-2015 |
| 20150294962 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure. | 10-15-2015 |
| 20150303167 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump. | 10-22-2015 |
| 20150340339 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In One method for manufacturing a semiconductor device, a conductive bump is formed on the surface of a semiconductor wafer so as to create a first bump opening area, and a dummy bump is formed on the surface of the semiconductor wafer so as to form a second bump opening area. In such a case, the dummy bump is formed such that the total of the first bump opening area and the second bump opening area is a value corresponding to the opening area of a conductive bump of a semiconductor wafer having only the conductive bump, whereby the semiconductor device is manufactured. | 11-26-2015 |
| 20150348804 | Method for Manufacturing Semiconductor Device and Manufacturing Apparatus of Semiconductor Device - A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a first substrate provided with an organic resin film over a transistor including an oxide semiconductor in a reduced pressure atmosphere; handling of the first substrate is performed in an atmosphere containing moisture as little as possible in an inert gas (e.g., nitrogen) atmosphere with a dew point of lower than or equal to −60° C., preferably with a dew point of lower than or equal to −75° C. without exposing the first substrate after the heat treatment to the air; and then, the first substrate is bonded to a second substrate that serves as an opposite substrate. | 12-03-2015 |
| 20150380346 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface. | 12-31-2015 |
| 20150380394 | SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME - A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode. | 12-31-2015 |
| 20150380395 | FLIP-CHIP ASSEMBLY PROCESS COMPRISING PRE-COATING INTERCONNECT ELEMENTS - A method of assembling a first and a second electronic components includes forming connection elements on an assembly surface of the first component and forming connection elements on an assembly surface of the second component. The method also includes depositing a liquid layer of electrically-insulating curable material on the assembly surface of the first and/or of the second component and arranging the first and second components on each other to place the connection elements of the second component in front of the connection elements of the first component. The method further includes applying a force along a predetermined direction and the first and/or the second components to create electric interconnects each formed of a connection element of the first component and of a connection element of the second component and curing the curable material. | 12-31-2015 |
| 20160013172 | RDL-FIRST PACKAGING PROCESS | 01-14-2016 |
| 20160049389 | 3DIC Package and Methods of Forming the Same - A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein. | 02-18-2016 |
| 20160064347 | Bump on Pad (BOP) Bonding Structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 03-03-2016 |
| 20160064352 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin. | 03-03-2016 |
| 20160083537 | RESIN COMPOSITION, RESIN SHEET, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - Provided is a resin sheet, wherein in a stress measurement in which a dynamic shear strain is applied in a direction parallel to a surface, the difference between a loss tangent as measured when a strain amplitude is 10% of the sheet thickness and a loss tangent as measured when the amplitude is 0.1% is equal to or greater than 1 at a temperature of 80° C. and a frequency of 0.5 Hz. The resin sheet of the present invention can provide a semiconductor device with excellent connection reliability, wherein air bubbles and cracks are less likely to occur in the resin sheet. In the resin composition of the present invention, aggregates are less likely to occur during storage. The resin sheet obtained by forming the resin composition into a sheet has good flatness. The hardened material thereof can provide a circuit board or a semiconductor device with high connection reliability. | 03-24-2016 |
| 20160141264 | FLIP-CHIP BONDER WITH INDUCTION COILS - A method and apparatus for flip chip bonding using conductive and inductive heating to heat a plurality of solder bumps located between a chip carrier and a chip. | 05-19-2016 |
| 20160148920 | STACKED MICROELECTRONIC DICE EMBEDDED IN A MICROELECTRONIC SUBSTRATE - Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material. | 05-26-2016 |
| 20160155720 | Method and Apparatus for Chip-To-Wafer Integration | 06-02-2016 |
| 20160155732 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIRST PORTION OF A SURFACE OF THE SEMICONDUCTOR SUBSTRATE IS RECESSED RELATIVE TO A SECOND PORTION OF THE SURFACE OF THE SEMICONDUCTOR SUBSTRATE TO FORM A RECESSED REGION IN THE SEMICONDUCTOR SUBSTRATE | 06-02-2016 |
| 20160172349 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES | 06-16-2016 |
| 20160181157 | Through Silicon Via Structure and Method | 06-23-2016 |
| 20160181220 | Dummy Flip Chip Bumps for Reducing Stress | 06-23-2016 |
| 20160190090 | Bump-on-Trace Interconnect - Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. | 06-30-2016 |
| 20160190104 | METHODS OF FORMING 3-D INTEGRATED SEMICONDUCTOR DEVICES HAVING INTERMEDIATE HEAT SPREADING CAPABILITIES - In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system. | 06-30-2016 |
| 20160204093 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE | 07-14-2016 |
| 20180025955 | SEMICONDUCTOR DEVICE AND METHOD | 01-25-2018 |
| 20180026015 | INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS | 01-25-2018 |
