| Entries |
| Document | Title | Date |
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| 20080225574 | MEMORY CELL WITH INDEPENDENT-GATE CONTROLLED ACCESS DEVICES AND MEMORY USING THE CELL - A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON.” | 09-18-2008 |
| 20080232157 | RANDOM ACCESS MEMORIES WITH AN INCREASED STABILITY OF THE MOS MEMORY CELL - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM and NVM devices. | 09-25-2008 |
| 20080266937 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto. | 10-30-2008 |
| 20080278993 | Static random acess memory device - Additional transistors P | 11-13-2008 |
| 20080298117 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a current path switching circuit that supplies said current from a power supply by switching between current paths according to whether a normal operation mode or a read mode is input externally, wherein said power supply is turned off and then turned on again in said normal operation mode, and in this state, data corresponding to the relationship between the magnitudes of the resistances of said first variable resistor element and said second variable resistor element is read in said read mode. | 12-04-2008 |
| 20080298118 | Asymmetrical SRAM cell with 4 double-gate transistors - The random access memory cell of SRAM type comprises an access transistor provided with a gate electrode connected to a word line. The access transistor is connected between a bit line and a gate electrode of a first load transistor itself connected to a gate electrode of a driver transistor and to a first source/drain electrode of a second load transistor. The first load transistor and the driver transistor, in series, form an inverter at the supply voltage terminals. At least the transistors not comprised in the inverter comprise two electrically independent gate electrodes. The second gate electrode of the access transistor is connected to the first gate electrode of the second load transistor and the second gate electrode of the latter is connected to the supply voltage. | 12-04-2008 |
| 20080304313 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a cell array having a plurality of SRAM cells arranged in a bit line direction and a word line direction orthogonal to said bit line direction in a matrix; and a peripheral circuit arranged adjacent to the cell array in the bit line direction. The cell array includes first P-well regions and first N-well regions shaped in stripes extending in the bit line direction and arranged alternately in the word line direction. The SRAM cell is formed point-symmetrically in the first P-well region and the first N-well regions located on both sides thereof. The peripheral circuit includes second P-well regions and second N-well regions extending in the bit line direction and arranged alternately in the word line direction. | 12-11-2008 |
| 20080310212 | SRAM WITH ASYMMETRICAL PASS GATES - An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate. | 12-18-2008 |
| 20090027946 | METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) - A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO. | 01-29-2009 |
| 20090027947 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced. | 01-29-2009 |
| 20090067221 | HIGH DENSITY 45NM SRAM USING SMALL-SIGNAL NON-STROBED REGENERATIVE SENSING - A memory device includes a plurality of cells comprising CMOS structures. A non-strobed regenerative sense-amplifier (NSR-SA) is coupled to the cells and employs offset compensation and avoids strobe timing uncertainty to increase read-access speeds. | 03-12-2009 |
| 20090067222 | SEMICONDUCTOR MEMORY DEVICE - SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor. | 03-12-2009 |
| 20090067223 | COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters. | 03-12-2009 |
| 20090086528 | BACK GATED SRAM CELL - Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation. | 04-02-2009 |
| 20090086529 | SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semiconductor storage device according to one aspect of the present invention includes a third transistor having one of a source and a drain connected to a first bit line and switching supply of a ground voltage performed on the first bit line in accordance with a value held in a memory cell according to selection and non-selection of the memory cell, and a fixed voltage keeping circuit keeping a potential of the other of the source and the drain of the third transistor to a fixed potential in a memory cell non-selected state in a six-transistor SRAM. | 04-02-2009 |
| 20090097302 | SEMICONDUCTOR DEVICE - A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current. | 04-16-2009 |
| 20090129142 | SEMICONDUCTOR MEMORY - A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized. | 05-21-2009 |
| 20090135643 | SEU HARDENING CIRCUIT AND METHOD - An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a second pMOS gate terminal of a second pMOS transistor of the pair of pMOS transistors, and tying at least a first pre-designated body terminal of at least one transistor selected from the group including essentially of a pair of pMOS transistors and a pair of nMOS transistors to at least a second pre-designated terminal of at least one pre-designated transistor selected from the group including essentially of the pair of pMOS transistors and the pair of nMOS transistors. | 05-28-2009 |
| 20090141539 | RADIATION TOLERANT SRAM BIT - In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters. | 06-04-2009 |
| 20090147561 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any one of the pair of bit lines. A write circuit is arranged, separately from the read circuit, at the other side of the memory cell array. The write circuit provides written data to the pair of bit lines to write data to the SRAM cells. | 06-11-2009 |
| 20090168499 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell. | 07-02-2009 |
| 20090168500 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines, | 07-02-2009 |
| 20090201719 | Method and System for Semiconductor Memory - Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells. | 08-13-2009 |
| 20090207650 | SYSTEM AND METHOD FOR INTEGRATING DYNAMIC LEAKAGE REDUCTION WITH WRITE-ASSISTED SRAM ARCHITECTURE - A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction. | 08-20-2009 |
| 20090244956 | Semiconductor memory device - In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node. | 10-01-2009 |
| 20090279348 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a first drive transistor controlled by the second cell node, and a second drive transistor controlled by the first cell node. The read word line and the first read bit line are connected with each other via the first drive transistor. The read word line and the second read bit line are connected with each other via the second drive transistor. | 11-12-2009 |
| 20090285011 | STATIC RANDOM ACCESS MEMORY - A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground. | 11-19-2009 |
| 20090310398 | LOW POWER, SMALL SIZE SRAM ARCHITECTURE - A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl) | 12-17-2009 |
| 20090323401 | 8T LOW LEAKAGE SRAM CELL - This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line. | 12-31-2009 |
| 20100027321 | Non-Volatile Single-Event Upset Tolerant Latch Circuit - A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information. | 02-04-2010 |
| 20100027322 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR - In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor. | 02-04-2010 |
| 20100034013 | OPTICAL REFRESHING OF LOADLESS FOR TRANSISTOR SRAM CELLS - Loadless 4 transistor SRAM cell operation can be substantially improved yielding area saving and more stable operation by use of optical-light load. Parasitic photocurrents in PMOS anodes-substrate junctions act as load currents. Light can be introduced by either ambient light through transparent window on top of the chip or by cheap LED diode attached to chip surface. | 02-11-2010 |
| 20100039853 | Design Structure, Structure and Method of Using Asymmetric Junction Engineered SRAM Pass Gates - A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; applying a voltage through asymmetric pull-up pFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; and applying a voltage through asymmetrical pass gates which provide low leakage SOI logic. | 02-18-2010 |
| 20100039854 | Structure, Structure and Method of Using Asymmetric Junction Engineered SRAM Pass Gates - A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The structure includes an SRAM cell having asymmetric junction-engineered SRAM pass gates with a high leakage junction and a low leakage junction. The asymmetric junction-engineered SRAM pass gates are connected between an internal node and a bit-line node. The high leakage junction is from a body to the internal node and the low leakage junction is from the body to the bit-line node. | 02-18-2010 |
| 20100046280 | SRAM Yield Enhancement by Read Margin Improvement - A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line. | 02-25-2010 |
| 20100046281 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells | 02-25-2010 |
| 20100080045 | ROBUST 8T SRAM CELL - This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line. | 04-01-2010 |
| 20100080046 | SEMICONDUCTOR DEVICE - A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current. | 04-01-2010 |
| 20100097844 | Write-Assist SRAM Cell - An integrated circuit structure includes a word-line; a column select line; and a latch. The latch includes a first storage node and a second storage node complementary to each other; and an operation voltage node. A control circuit is coupled between the operation voltage node and the latch. The control circuit includes a first input coupled to the word-line; and a second input coupled to the column selection line. The control circuit is configured to interconnect the operation voltage node and the latch when both the word-line and the column select line are selected, and disconnect the operation voltage node and the latch when at least one of the word-line and the column select line is not selected. | 04-22-2010 |
| 20100124100 | DEVICE FOR CONTROLLING THE ACTIVITY OF MODULES OF AN ARRAY OF MEMORY MODULES - A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function. | 05-20-2010 |
| 20100157661 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate connected to the input terminal of any one of the first inverter and the second inverter, and a first read transfer transistor connected to a first read bit line through the first read driver transistor, and including a gate connected to a read word line, the first read transfer transistor shared by at least two of the memory cells in the memory cell array. | 06-24-2010 |
| 20100165707 | Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors - An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate. | 07-01-2010 |
| 20100165708 | MEMORY CONTROLLER AND DECODER - A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced. | 07-01-2010 |
| 20100165709 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-01-2010 |
| 20100177556 | ASYMMETRIC STATIC RANDOM ACCESS MEMORY - An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter. | 07-15-2010 |
| 20100182823 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 07-22-2010 |
| 20100188888 | Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator - A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell. | 07-29-2010 |
| 20100188889 | BACK GATED SRAM CELL - Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation. | 07-29-2010 |
| 20100195374 | Eight Transistor Soft Error Robust Storage Cell - A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell. | 08-05-2010 |
| 20100195375 | FULL CMOS SRAM - A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors. | 08-05-2010 |
| 20100214824 | Converting SRAM cells to ROM Cells - A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value. | 08-26-2010 |
| 20100238714 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 09-23-2010 |
| 20100238715 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 09-23-2010 |
| 20100238716 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 09-23-2010 |
| 20100246243 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a plurality of bit lines each connected to respective one of the memory cells, and a row selection circuit that, in a read operation, drives the word line to a set potential at a drive speed slower than a discharge speed of the bit line exhibited when the word line is raised roughly vertically to VDD. | 09-30-2010 |
| 20100271865 | Semiconductor Memory and Program - A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which | 10-28-2010 |
| 20100277970 | Static random accee memory device - Additional transistors P | 11-04-2010 |
| 20100290269 | STATIC RANDOM ACCESS MEMORY - Included are a memory cell, a first metal interconnection, a variable capacitance circuit and a connection switch. The memory cell includes cross-coupled first and second inverters which are connected to a power supply node. The first metal interconnection is connected to the power supply node. The variable capacitance circuit includes: second and third metal interconnections electrically connected to a connection node; and a controller capable of controlling electrical connection between the third metal interconnection and the connection node. The connection switch is connected between the first metal interconnection and the connection node of the variable capacitance circuit. The connection switch is configured to electrically connect the first metal interconnection and the connection node in a write operation of the memory cell. | 11-18-2010 |
| 20100296334 | 6T SRAM Cell with Single Sided Write - An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased. | 11-25-2010 |
| 20100296335 | Asymmetric SRAM Cell with Split Transistors on the Strong Side - An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. A process of operating an integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary PMOS driver or NMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. | 11-25-2010 |
| 20100296336 | 8T SRAM Cell with Two Single Sided Ports - A dual port SRAM cell includes an auxiliary driver transistor on each data node. The SRAM cell is capable of single sided write to each data node. The auxiliary driver transistors in addressed cells may be biased independently of half-addressed cells. During write and read operations, the auxiliary driver transistors may be floated or biased. Auxiliary driver transistors in half-addressed SRAM cells may be biased. During standby modes, the auxiliary driver transistors may be floated. During sleep modes, the auxiliary driver transistors may be biased at reduced voltages. The auxiliary driver transistors in each cell may be independent or may have a common source node within each cell. Additional single sided write ports and read buffers may be added. A process of operating an integrated circuit that includes performing a single-sided write bit-side low, a single-sided write bit-side high, and a read bit-side operation. | 11-25-2010 |
| 20100296337 | 8T SRAM Cell with Four Load Transistors - An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of operating an integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The process includes biasing the auxiliary load transistors in addressed SRAM cells independently of half-addressed cells. | 11-25-2010 |
| 20100315861 | SRAM CELL AND SRAM DEVICE - In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control gates of the second to the fifth four-terminal double-gate FETs are arranged on the sides facing each other and are commonly connected to a first bias line. Threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line. A word line, the first bias line and the second bias line are arranged orthogonally to the direction of arrangement of the first to the fourth semiconductor thin plates. | 12-16-2010 |
| 20100315862 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 12-16-2010 |
| 20100328990 | SRAM DEVICE - An SRAM device comprising a memory cell, the memory cell comprising two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, and
| 12-30-2010 |
| 20100328991 | SEMICONDUCTOR MEMORY DEVICE - A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses. | 12-30-2010 |
| 20110019464 | Smart Well Assisted SRAM Read and Write - An integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. An integrated circuit containing an array of SRAM cells with PMOS drivers and passgates, and a p-well bias control circuit which biases p-wells in each SRAM column independently. A process of operating an integrated circuit containing an array of SRAM cells with NMOS drivers and passgates, and an n-well bias control circuit which biases n-wells in each SRAM column independently. | 01-27-2011 |
| 20110026313 | TRANSISTOR-BASED MEMORY CELL AND RELATED OPERATING METHODS - A loadless static random access memory cell is provided. The memory cell includes four transistors. The first transistor has a gate terminal corresponding to a word line of the memory cell, a source/drain terminal corresponding to a first bit line of the memory cell, and a drain/source terminal corresponding to a first storage node of the memory cell. The second transistor has a gate terminal corresponding to the word line, a source/drain terminal corresponding to a second bit line of the memory cell, and a drain/source terminal corresponding to a second storage node of the memory cell. The third transistor has a gate terminal coupled to the second storage node, a drain terminal coupled to the first storage node, a source terminal corresponding to a reference voltage, and a body terminal directly connected to the third gate terminal. The fourth transistor has a gate terminal coupled to the first storage node, a drain terminal coupled to the second storage node, a source terminal corresponding to the reference voltage, and a body terminal directly connected to the fourth gate terminal. | 02-03-2011 |
| 20110026314 | Static Memory Device with Five Transistors and Operating Method - At the bottom of a column (COLi) of memory cells (CEL) of the SRAM type with five portless transistors, there is placed an additional cell (CLS), with a structure identical to the cells (CEL), which makes it possible to write and read a datum in a memory cell (CEL) of the column without using a read amplifier. | 02-03-2011 |
| 20110026315 | Single-Event Upset Immune Static Random Access Memory Cell Circuit, System, And Method - A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell. | 02-03-2011 |
| 20110032751 | SEMICONDUCTOR DEVICE - The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells. | 02-10-2011 |
| 20110063895 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM - A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line. | 03-17-2011 |
| 20110063896 | Semiconductor memory device - A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array. | 03-17-2011 |
| 20110085371 | APPARATUS OF LOW POWER DUAL WORD LINE SIX-TRANSISTOR SRAMS - A six-transistor SRAM cell with dual word line and dual bit line is provided. Each word line is used to separately control an access transistor of the SRAM cell. A six-transistor SRAM cell with dual word line and a single bit line is also provided. The dual word line SRAM cells reduce word line and bit line switching power, and thus reduces the overall power consumption. | 04-14-2011 |
| 20110085372 | NON-VOLATILE SRAM CELL THAT INCORPORATES PHASE-CHANGE MEMORY INTO A CMOS PROCESS - A SRAM cell having two cross-coupled inverters formed by CMOS technology and first and second chalcogenic elements integrated with the SRAM cell to add nonvolatile properties to the storage cell. The PCM resistors are programmed to the SET state and the RESET state, and upon power-up the SRAM cell takes on the data contained in the PCM cells. | 04-14-2011 |
| 20110103137 | SOURCE CONTROLLED SRAM - Disclosed is a cmos sram cell including two cross-coupled inverters, each having a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of said pmos transistors, and a third signal line connected to the source of the other of said pmos transistors. The third signal line may be orthogonal to the first and second signal lines. Also disclosed is a cmos sram cell including two cross-coupled inverters, a pair of bitlines for writing data to the cell, and at least one further bitline for reading data from the cell. | 05-05-2011 |
| 20110157963 | SRAM WORD-LINE COUPLING NOISE RESTRICTION - A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows. Each SRAM cell has a first word-line conductor and a second word-line conductor. The first word-line conductor is connected to a first coupling noise restriction circuit. The first coupling noise restriction circuit comprises an inverter and a NMOSFET. The inverter has another NMOSFET and a PMOSFET. | 06-30-2011 |
| 20110157964 | Memory Cell Using Leakage Current Storage Mechanism - A memory cell comprises a storage element including a transistor and an inverter. The inverter has an input coupled to a first source/drain of the transistor at a first node and has an output coupled to a gate of the transistor at a second node. The transistor has a second source/drain coupled to a voltage supply of the memory circuit. The memory cell further includes a switching element coupled to the storage element at the first node and being operative to selectively access the storage element as a function of a control signal supplied to a control input of the switching element. The storage element is operative to store at least first and second data states. The first data state is retained in the storage element by maintaining the first node at a first voltage level by leakage current and by maintaining the second node at a second voltage level by active current. The second data state is retained in the storage element by maintaining the first node at the second voltage level and the second node at the first voltage level by respective active currents. | 06-30-2011 |
| 20110157965 | SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device having an SRAM. | 06-30-2011 |
| 20110170337 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor. | 07-14-2011 |
| 20110182112 | 10T SRAM Cell with Near Dual Port Functionality - An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation. | 07-28-2011 |
| 20110199817 | ROBUST LOCAL BIT SELECT CIRCUITRY TO OVERCOME TIMING MISMATCH - An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time. | 08-18-2011 |
| 20110211386 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 09-01-2011 |
| 20110222332 | Fully Balanced Dual-Port Memory Cell - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU | 09-15-2011 |
| 20110235406 | Low-Power 5T SRAM with Improved Stability and Reduced Bitcell Size - A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation. | 09-29-2011 |
| 20110235407 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor memory device including a substrate, wherein the substrate includes first, second and third well regions, the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second type conductor. The semiconductor memory device includes first and second pull-up devices disposed in a line in the first well region and sharing a power supply voltage terminal, a first pull-down device disposed in the second well region, wherein the first pull-down device is adjacent to the first pull-up device, a second pull-down device disposed in the third well region, wherein the second pull-down device is adjacent to the second pull-up device, a first access device disposed in the second well region, wherein the first access device is adjacent to the second pull-up device, and a second access device disposed in the third well region, wherein the second access device is adjacent to the first pull-up device. | 09-29-2011 |
| 20110249489 | Nanowire Circuits in Matched Devices - An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire. | 10-13-2011 |
| 20110299325 | SRAM Devices And Methods Of Manufacturing The Same - Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels. | 12-08-2011 |
| 20110299326 | TFET BASED 4T MEMORY DEVICES - A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction. | 12-08-2011 |
| 20110299327 | FOUR-TRANSISTOR AND FIVE-TRANSISTOR BJT-CMOS ASYMMETRIC SRAM CELLS - A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half. | 12-08-2011 |
| 20110305073 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell. | 12-15-2011 |
| 20110317476 | Bit-by-Bit Write Assist for Solid-State Memory - A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power supply node and ground. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter that assists its change of state in a write operation. In other embodiments, a single power switch transistor gated by either a word line or a column select signal may be used. | 12-29-2011 |
| 20110317477 | CELL STRUCTURE FOR DUAL-PORT SRAM - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12. | 12-29-2011 |
| 20110317478 | Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability - An improved method for performing a write through operation during a write operation of a SRAM cell ( | 12-29-2011 |
| 20120002460 | DYNAMICALLY CONFIGURABLE SRAM CELL FOR LOW VOLTAGE OPERATION - An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively. The memory device may further include biasing means for modifying a value of a threshold voltage of at least one of the main transistors to a first threshold voltage value or to a second threshold voltage value and for modifying a threshold voltage value of at least one of the complementary transistors to the second threshold voltage value or to the first threshold voltage value during a write operation of the first logic value or of the second logic value, respectively, in the memory cell. | 01-05-2012 |
| 20120014173 | Disturb-Free Static Random Access Memory Cell - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 01-19-2012 |
| 20120026782 | SEMICONDUCTOR MEMORY DEVICE - In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout. | 02-02-2012 |
| 20120057399 | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF - The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | 03-08-2012 |
| 20120063212 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities. | 03-15-2012 |
| 20120063213 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element | 03-15-2012 |
| 20120069637 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - An object is to provide a semiconductor memory device which holds data of an SRAM or a flip-flop circuit and holds data in the SRAM while electric power is not supplied from a reader or electric power is not enough, without changing a battery for driving a power supply corresponding to deterioration of the battery with time, and a semiconductor device provided with the semiconductor memory device. An SRAM cell, a decoder connected to the SRAM cell through a word line, a read/write circuit connected to the SRAM cell through the data line, and a power storage unit connected to the SRAM cell are provided. The power storage unit is charged when data is written to or read from the SRAM cell through the data line. | 03-22-2012 |
| 20120081949 | Active Bit Line Droop for Read Assist - A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved. | 04-05-2012 |
| 20120113709 | Semiconductor Integrated Circuit Device with Reduced Leakage Current - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 05-10-2012 |
| 20120120717 | SRAM CELL - The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor. | 05-17-2012 |
| 20120127784 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is a positive integer) number of auxiliary dummy bit lines are provided. A switching element connects at least one of the n number of auxiliary dummy bit lines to the main dummy bit line. | 05-24-2012 |
| 20120140552 | WRITE ASSIST STATIC RANDOM ACCESS MEMORY CELL - Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a first switch controlled by a write operation signal, connected between a supply voltage and a first pull-up transistor of the latch and a third switch controlled the write operation signal, connected between the second node and a ground. The SRAM cell further includes a second switch controlled by the write operation signal, connected between the supply voltage and a second pull-up transistor and a fourth switch controlled by the write operation signal, connected between the second node and the ground. The write operation signals are generated by a first complex gate and a second complex gate. | 06-07-2012 |
| 20120147662 | Semiconductor Integrated Circuit and Manufacturing Method Thereof - High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor. | 06-14-2012 |
| 20120155152 | STATIC RANDOM ACCESS MEMORY - In a random access memory, one of a first conductivity type well constituting a first bit in one column group and another first conductivity type well constituting a second bit selected simultaneously to the first bit in an adjacent column group, is isolated from a common well of the first conductivity type by providing a deep well of a second conductivity type, such that the area of the deep well of the second conductivity type does not exceed the area of one column group. | 06-21-2012 |
| 20120163068 | 10T SRAM Cell with Near Dual Port Functionality - An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation. | 06-28-2012 |
| 20120182793 | ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL - A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric. | 07-19-2012 |
| 20120195111 | In-Line Register File Bitcell - An SRAM bitcell architecture is described having a dedicated read port (N | 08-02-2012 |
| 20120224414 | Solid-State Memory Cell with Improved Read Stability - A solid-state memory in which stability assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an isolation gate connected between one of the storage nodes and the input of the opposite inverter. The isolation gate may be realized by complementary | 09-06-2012 |
| 20120224415 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter. | 09-06-2012 |
| 20120257442 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line. | 10-11-2012 |
| 20120257443 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE CURRENT - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 10-11-2012 |
| 20120281458 | ULTRA LOW POWER SRAM CELL CIRCUIT WITH A SUPPLY FEEDBACK LOOP FOR NEAR AND SUB THRESHOLD OPERATION - An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention. | 11-08-2012 |
| 20120281459 | ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED FOR MINIMAL LEAKAGE OPERATION - A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether. | 11-08-2012 |
| 20120307550 | Asymmetric Static Random Access Memory Cell with Dual Stress Liner - A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner. | 12-06-2012 |
| 20120307551 | SEMICONDUCTOR DEVICE - The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has : a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has : replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells. | 12-06-2012 |
| 20120314485 | COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A LOW-VOLTAGE CMOS PLATFORM - An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element. | 12-13-2012 |
| 20120314486 | Semiconductor Memory Device for Reducing Charge/Discharge Power of Write Bitlines - It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines. | 12-13-2012 |
| 20120327704 | SEMICONDUCTOR MEMORIES - A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch. | 12-27-2012 |
| 20120327705 | Data-Aware SRAM Systems and Methods Forming Same - Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively. | 12-27-2012 |
| 20130003446 | Method for Extending Word-Line Pulses - An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current. | 01-03-2013 |
| 20130010531 | MEMORY CIRCUIT AND WORD LINE CONTROL CIRCUIT - The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node. | 01-10-2013 |
| 20130021840 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film. | 01-24-2013 |
| 20130064007 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 03-14-2013 |
| 20130083592 | SEMICONDUCTOR DEVICE WITH COMPLEMENTARY GLOBAL BIT LINES, OPERATING METHOD, AND MEMORY SYSTEM - A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal. | 04-04-2013 |
| 20130088913 | CIRCUIT AND METHOD OF WORD LINE SUPPRESSION - A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage. | 04-11-2013 |
| 20130107610 | SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL | 05-02-2013 |
| 20130141963 | Methods and Apparatus for FinFET SRAM Cells - Methods and apparatus for providing finFET SRAM cells. An SRAM cell structure is provided including a central N-well region and a first and a second P-well region on opposing sides of the central N-well region, having an area ratio of the N-well region to the P-well regions between 80-120%, the SRAM cell structure further includes at least one p-type transistor formed in the N-well region and having a gate electrode comprising a gate and a gate dielectric over a p-type transistor active area in the N-well region; and at least one n-type transistor formed in each of the first and second P-well regions and each n-type transistor having a gate electrode comprising a gate and a gate dielectric over an n-type transistor active area in the respective P-well region. Methods for operating the SRAM cell structures are disclosed. | 06-06-2013 |
| 20130163312 | SRAM TIMING TRACKING CIRCUIT - A static random access memory (SRAM) test apparatus includes an array of SRAM test cells. The test cells are configured according to a layout with NMOS and PMOS transistors coupleable as inverters and responsive to a first passing gate transistor. At least one of the NMOS and PMOS transistors of a test cell at a predetermined location in the array is coupled to a fixed voltage to force a logic state of an associated inverter. A switching signal coupled to the associated inverter through a second passing gate transistor produces a detectable test current through one of the NMOS and PMOS transistors of the associated inverter of said test cell and through one of the NMOS and PMOS transistors of an associated inverter of an adjacent series-connected test cell. | 06-27-2013 |
| 20130170288 | DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO NOISE DURING SAME ROW ACCESS - A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row). | 07-04-2013 |
| 20130170289 | LOW VOLTAGE WRITE TIME ENHANCED SRAM CELL AND CIRCUIT EXTENSIONS - A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode. | 07-04-2013 |
| 20130182494 | SKEWED SRAM CELL - A memory cell including a cross-coupled latch with corresponding storage nodes, and further including first and second write pass gate transistors and first and second read pass gate transistors. The write pass gate transistors are controlled by a write word line and the read pass transistors are controlled by a read word line. Each read and write pass gate transistor is coupled between a storage node and either a bit line or a complementary bit line. The write pass gate transistors are implemented at a first strength level and the read pass gate transistors are implemented at a second strength level which is less than the first strength level. In this manner, the read and write margins are independently configurable without negatively impacting each other. | 07-18-2013 |
| 20130182495 | Efficient Static Random-Access Memory Layout - A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions. | 07-18-2013 |
| 20130229860 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE CURRENT - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 09-05-2013 |
| 20130235652 | STRUCTURE AND METHOD FOR A SRAM CIRCUIT - The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack. | 09-12-2013 |
| 20130250660 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 09-26-2013 |
| 20130265819 | EIGHT TRANSISTOR SOFT ERROR ROBUST STORAGE CELL - A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell. | 10-10-2013 |
| 20130272057 | GLOBAL BIT SELECT CIRCUIT WITH WRITE AROUND CAPABILITY - A global to local bit line interface circuit for domino static random access memory (SRAM) devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines. | 10-17-2013 |
| 20130272058 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 10-17-2013 |
| 20130279242 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 10-24-2013 |
| 20130286719 | SEMICONDUCTOR MEMORY WITH SIMILAR RAM AND ROM CELLS - A semiconductor memory includes an array of volatile memory cells, wherein one of the volatile memory cells has transistors connected in a first memory cell circuit, and at least one non-volatile memory cell having transistors connected in a second memory cell circuit, wherein the transistors in the first memory cell circuit are at least one more than the transistors in the second memory cell circuit. | 10-31-2013 |
| 20130286720 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS THEREOF - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element. | 10-31-2013 |
| 20130294149 | REDUCING POWER IN SRAM USING SUPPLY VOLTAGE CONTROL - An embodiment of the invention provides a method for decreasing power in a static random access memory (SRAM). A first voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are column addressed during a read cycle. A second voltage is applied between latch sourcing and latch sinking supply lines for columns of memory cells that are not column addressed during a read cycle. Because the second voltage is less than the first voltage, power in the SRAM is reduced. In this embodiment, a memory cell in the SRAM includes at least one read buffer and a latch connected between the latch sourcing and latch sinking supply lines. | 11-07-2013 |
| 20130314977 | MEMORY CIRCUIT PROPERLY WORKABLE UNDER LOW WORKING VOLTAGE - A memory circuit properly workable under low working voltage includes a plurality of write word lines, a plurality of write bit lines, a plurality of read/write word lines, a plurality of read/write bit lines, a plurality of read/write inverted word lines, a plurality of virtual voltage source circuits, a plurality of virtual ground circuits, and a plurality of asymmetrical RAM cells constituting a cell array. The asymmetrical RAM cells are formed of seven transistors, five of which are NMOS transistors and two of which are PMOS transistors. The virtual voltage power source circuit and the virtual ground circuit can reinforce the write-in and read abilities under low working voltage to make the write-in and read actions more stable, decrease leakage current, and lower power consumption. | 11-28-2013 |
| 20140003135 | SRAM BITCELL IMPLEMENTED IN DOUBLE GATE TECHNOLOGY | 01-02-2014 |
| 20140003136 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS | 01-02-2014 |
| 20140016402 | SRAM BIT CELL WITH REDUCED BIT LINE PRE-CHARGE VOLTAGE - An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations. | 01-16-2014 |
| 20140016403 | SEMICONDUCTOR MEMORY DEVICE - In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area. | 01-16-2014 |
| 20140029333 | FIVE TRANSISTOR SRAM CELL - A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state. | 01-30-2014 |
| 20140036580 | MEMORY CIRCUIT - A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA. | 02-06-2014 |
| 20140036581 | SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY - A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor. | 02-06-2014 |
| 20140050018 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell provided with a pair of storage nodes which store data in a complementary manner, a pair of bit lines that are driven in a complementary manner based on data written to the memory cell, a word line that selects a row of the memory cell, and a word line potential fixing circuit that fixes a potential of the word line so that the row of the memory cell is not selected when a power supply of the memory cell rises. | 02-20-2014 |
| 20140063920 | Static random access memory that initializes to pre-determined state - A static random access memory (SRAM) is provided for establishing an initialization state. The SRAM connects to a plurality of signal lines including a bit line and an inverse bit line. The SRAM includes first and second inverters, a voltage potential and a ground. The first inverter includes a first n-type metal oxide semiconductor (MOS) transistor having a first n-type threshold voltage and a first p-type MOS transistor having a first p-type threshold voltage. The second inverter includes a second n-type MOS transistor having a second n-type threshold voltage and a second p-type MOS transistor having a second p-type threshold voltage. The first transistors connect respectively first n-type and first p-type drains together at a first junction that connects to the bit line. The second transistors connect respectively a second n-type and second p-type drains together at a second junction that connects to the inverse bit line. The voltage potential connects to corresponding first and second p-type sources of the first and second p-type MOS transistors, and the ground potential connects to corresponding first and second n-type sources of the first and second n-type MOS transistors. The SRAM initializes the bit line to either logical high or low in response to differences in threshold voltages between either or both of the first and second n-type MOS transistors or the first and second p-type MOS transistors. | 03-06-2014 |
| 20140071737 | LOCAL WRITE AND READ ASSIST CIRCUITRY FOR MEMORY DEVICE - A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines. | 03-13-2014 |
| 20140085967 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 03-27-2014 |
| 20140092676 | Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 04-03-2014 |
| 20140098598 | MEMORY CELL ARRAY LATCHUP PREVENTION - A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus. | 04-10-2014 |
| 20140104936 | LATCH-BASED MEMORY ARRAY - The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input. | 04-17-2014 |
| 20140119104 | Data-Aware SRAM Systems and Methods Forming Same - Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively. | 05-01-2014 |
| 20140133219 | Power Line Lowering for Write Assisted Control Scheme - Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate. | 05-15-2014 |
| 20140153322 | SRAM Cell Comprising FinFETs - A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals. | 06-05-2014 |
| 20140153323 | Methods for Operating SRAM Cells - A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other. | 06-05-2014 |
| 20140169077 | OPERATION AWARE AUTO-FEEDBACK SRAM - A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell. | 06-19-2014 |
| 20140204659 | CAPACITIVE COUPLED SENSE AMPLIFIER BIASED AT MAXIMUM GAIN POINT - A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle. | 07-24-2014 |
| 20140204660 | MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEEDBACK LATCH - In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a SRAM reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch. The dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle. | 07-24-2014 |
| 20140211548 | LOW POWER STATIC RANDOM ACCESS MEMORY - A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state. | 07-31-2014 |
| 20140219011 | SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING HIERARCHICAL AND/OR OTHER FEATURES - A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. | 08-07-2014 |
| 20140254249 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 09-11-2014 |
| 20140269026 | TRACKING CIRCUIT - A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal. | 09-18-2014 |
| 20140269027 | AMPLIFIER - A circuit comprises a first data line, a second data line, a charging circuit, a first circuit, a second circuit, a first switching circuit, and a second switching circuit. The charging circuit and the first circuit are each coupled with the first data and the second data line. The first switching circuit is coupled between the first data line and a first node of the second circuit. The second switching circuit is coupled between the second data line and a second node of the second circuit. The data on the first node or the second node represents data in a single-ended circuit. Data on both the first node and the second node represent data in a differential circuit. | 09-18-2014 |
| 20140293682 | MEMORY BITCELL CLUSTERS EMPLOYING LOCALIZED GENERATION OF COMPLEMENTARY BITLINES TO REDUCE MEMORY AREA, AND RELATED SYSTEMS AND METHODS - Embodiments disclosed include memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area. The memory bitcell clusters disclosed may be static random access memory (SRAM) used as central processing unit (CPU) register files. The memory bitcell clusters disclosed include a plurality of memory bitcells that share a common bitline. To reduce area required to provide complementary bitlines for the memory bitcells, the memory bitcell clusters include a localized inverter circuit. The localized inverter circuit is configured to invert a common bitline localized to the memory bitcells to provide a complementary bitline for the memory bitcells in the memory bitcell cluster. Because the inverter circuit is localized to the memory bitcells, a track in a semiconductor die for the complementary bitline does not extend beyond the memory bitcell cluster, minimizing the complexity of the memory bitcell cluster by reducing a number of bitline tracks used by half. | 10-02-2014 |
| 20140307503 | EIGHT TRANSISTOR SOFT ERROR ROBUST STORAGE CELL - A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell. | 10-16-2014 |
| 20140313819 | SYSTEM ON CHIP INCLUDING DUAL POWER RAIL AND VOLTAGE SUPPLY METHOD THEREOF - A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell. | 10-23-2014 |
| 20140328115 | POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 11-06-2014 |
| 20140347916 | EIGHT TRANSISTOR (8T) WRITE ASSIST STATIC RANDOM ACCESS MEMORY (SRAM) CELL - Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch. | 11-27-2014 |
| 20140347917 | STATIC RANDOM ACCESS MEMORY STRUCTURES - A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate. | 11-27-2014 |
| 20140362639 | Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 12-11-2014 |
| 20140376305 | CIRCUIT FOR ENHANCING ROBUSTNESS OF SUB-THRESHOLD SRAM MEMORY CELL - The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes. The circuit improves the noise margin of sub-threshold SRAM memory cells and effectively improves the process robustness of sub-threshold SRAM memory cells. | 12-25-2014 |
| 20150009749 | MEMORY CELL ARRAY - A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array. | 01-08-2015 |
| 20150009750 | DEVICE INCLUDING A DUAL PORT STATIC RANDOM ACCESS MEMORY CELL AND METHOD FOR THE FORMATION THEREOF - A device includes a substrate and a dual port static random access memory cell. The substrate includes an N-well region, a first P-well region and a second P-well region. The first and second P-well regions are arranged on opposite sides of the N-well region and spaced apart along a width direction. The static random access memory cell includes first and second pull-up transistors that are provided in the N-well region, a first pair of pull-down transistors and a first pair of access transistors provided in the first P-well region, and a second pair of pull-down transistors and a second pair of access transistors provided in the second P-well region. Each of the first pair and the second pair of pull-down transistors includes a first pull-down transistor and a second pull-down transistor. Active regions of the first pull-down transistor and the second pull-down transistor are spaced apart along the width direction. | 01-08-2015 |
| 20150009751 | METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS - Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase. | 01-08-2015 |
| 20150016183 | SENSE AMPLIFIER WITH TRANSISTOR THRESHOLD COMPENSATION - One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier. | 01-15-2015 |
| 20150023091 | Semiconductor Device Having Timing Control For Read-Write Memory Access Operations - A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device | 01-22-2015 |
| 20150055402 | NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE - Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer. | 02-26-2015 |
| 20150078069 | INTEGRATED CMOS CIRCUIT HAVING FIRST AND SECOND CIRCUIT PARTS - An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus. | 03-19-2015 |
| 20150085567 | THREE-DIMENSIONAL TWO-PORT BIT CELL - A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer. | 03-26-2015 |
| 20150085568 | READ/WRITE ASSIST FOR MEMORIES - An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations. | 03-26-2015 |
| 20150103585 | High stability static random access memory cell - A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly. | 04-16-2015 |
| 20150117094 | MEMORY DEVICE AND A METHOD OF OPERATING THE SAME - A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level. | 04-30-2015 |
| 20150131368 | IMPLEMENTING SENSE AMPLIFIER FOR SENSING LOCAL WRITE DRIVER WITH BOOTSTRAP WRITE ASSIST FOR SRAM ARRAYS - A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability. | 05-14-2015 |
| 20150146479 | SRAM WRITE-ASSISTED OPERATION WITH VDD-TO-VCS LEVEL SHIFTING - An electronic circuit and a method for driving data writes to an SRAM bit cell in an electronic circuit. The electronic circuit translates a first write signal in a lower voltage domain to a second write signal in a higher voltage domain. Based, at least in part, on the second write signal, the electronic circuit controls a discharge of a voltage of a data write line to a ground voltage level. The electronic circuit provides a negative voltage boost to the data write line after the voltage of the data write line has been discharged to reach or exceed a threshold value relative to the ground voltage level. | 05-28-2015 |
| 20150146480 | NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE - Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer. | 05-28-2015 |
| 20150310908 | MEMORY ARRAY - A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line. | 10-29-2015 |
| 20150348615 | Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified. | 12-03-2015 |
| 20150348616 | TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION - A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal. | 12-03-2015 |
| 20150357009 | HIGH-DENSITY LATCH ARRAYS - A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file. | 12-10-2015 |
| 20150357026 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE CURRENT - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 12-10-2015 |
| 20150357030 | Methods and Apparatus for Designing and Constructing Dual Write Memory Circuits with Voltage Assist - Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the V | 12-10-2015 |
| 20150364183 | METHOD AND APPARATUS FOR BIT-LINE SENSING GATES ON AN SRAM CELL - A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (SRAM) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor. | 12-17-2015 |
| 20150364184 | STATIC RANDOM ACCESS MEMORY AND RIVING METHOD THEREOF - A static random access memory comprises a pre-charge unit that supplies a pre-charge voltage to first and second bit lines connected to a bit cell; a capacitor, of which one or the other terminal is selectively connected to a ground terminal; a clamping unit that selectively connects the bit lines with the capacitor to adjust a voltage level of the bit lines; and a mux unit that is included in a unit memory cell including the bit cell, the pre-charge unit, the capacitor and the clamping unit, and activates the bit lines of the unit memory cell in response to reception of a selection signal; wherein the clamping unit connects the first and second bit lines with the capacitor in response to a charge sharing control signal, to induce charge sharing between the first and second bit lines and the capacitor. | 12-17-2015 |
| 20150371702 | STATIC RANDOM ACCESS MEMORY AND METHOD OF USING THE SAME - A static random access memory (SRAM) including a bit cell, wherein the bit cell includes at least two p-type pass gates. The SRAM further includes a bit line connected to the bit cell, and a bit line bar connected to the bit cell. The SRAM further includes a pre-discharge circuit connected to the bit line and to the bit line bar, wherein the pre-discharge circuit includes at least two n-type transistors. The SRAM further includes cross-coupled transistors connected to the bit line and to the bit line bar, wherein each transistor of the cross-coupled transistors is an n-type transistor. The SRAM further includes a write multiplexer connected to the bit line and to the bit line bar, wherein the write multiplexer includes two p-type transistors. | 12-24-2015 |
| 20150380076 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 12-31-2015 |
| 20150380078 | MEMORY CHIP AND LAYOUT DESIGN FOR MANUFACTURING SAME - A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell is different from the second half-cell. | 12-31-2015 |
| 20150380079 | LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY - A low power sense amplifier for an SRAM is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement. A first pull down transistor driven by the bit line complement is coupled to the first pass gate transistor, and a second pull down transistor driven by the bit line true is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pass gate transistor with the first pull down transistor and a data line complement is coupled to a node coupling the second pass gate transistor with the second pull down transistor. A current cut-off device cuts off parasitic current from flowing through the first pass gate transistor and the first pull down transistor and through the second pass gate transistor and the second pull down transistor. | 12-31-2015 |
| 20160005458 | Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features - A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. | 01-07-2016 |
| 20160012881 | MEMORY CIRCUIT FOR PRE-CHARGING AND WRITE DRIVING | 01-14-2016 |
| 20160042785 | MEMORY DEVICE INCLUDING REFERENCE VOLTAGE GENERATOR - A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other. | 02-11-2016 |
| 20160049189 | METHOD OF MINIMIZING THE OPERATING VOLTAGE OF AN SRAM CELL - An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively. | 02-18-2016 |
| 20160064068 | SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE - A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor. | 03-03-2016 |
| 20160064069 | LOW VOLTAGE SRAM - In some embodiments, an SRAM includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The SRAM also includes a memory controller configured to detect a temperature of the SRAM and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells. | 03-03-2016 |
| 20160071574 | METHOD AND CIRCUITS FOR LOW LATENCY INITIALIZATION OF STATIC RANDOM ACCESS MEMORY - A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously. | 03-10-2016 |
| 20160078926 | DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) - In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit. | 03-17-2016 |
| 20160093367 | Cross-Coupled Thyristor SRAM Circuits and Methods of Operation - A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby. | 03-31-2016 |
| 20160093368 | Six-Transistor SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
| 20160093369 | Write Assist SRAM Circuits and Methods of Operation - A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. | 03-31-2016 |
| 20160111143 | STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME - A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM. | 04-21-2016 |
| 20160118106 | SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells. | 04-28-2016 |
| 20160125933 | CIRCUIT-LEVEL ABSTRACTION OF MULTIGATE DEVICES USING TWO-DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN - A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell. | 05-05-2016 |
| 20160148676 | METHOD OF USING A STATIC RANDOM ACCESS MEMORY - A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell. | 05-26-2016 |
| 20160172022 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM | 06-16-2016 |
| 20160180908 | UNIPOLAR-SWITCHING PERPENDICULAR MRAM AND METHOD FOR USING SAME | 06-23-2016 |
| 20160180923 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE | 06-23-2016 |
| 20160182023 | APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS | 06-23-2016 |
| 20160196867 | STATIC MEMORY CELL WITH TFET STORAGE ELEMENTS | 07-07-2016 |
| 20160203855 | MEMORY DEVICE, RELATED METHOD, AND RELATED ELECTRONIC DEVICE | 07-14-2016 |
| 20160203857 | TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT | 07-14-2016 |
| 20160379706 | DUAL VOLTAGE ASYMMETRIC MEMORY CELL - Memory with asymmetric power delivery for keeper cells in the memory are provided. In some embodiments, first and second power delivery circuits use separate first and second independently regulated power supplies. The first supply may be a supply nominally used for the memory structure, while the second supply may be lower than the first supply. In some embodiments, during a write operation, the first (higher) supply is used for one of the logic elements in a keeper cell, while the second (lower) supply is used for the other keeper logic element. | 12-29-2016 |
| 20190147942 | DUAL RAIL SRAM DEVICE | 05-16-2019 |
