| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327530000 |
With specific source of supply or bias voltage
| 1743 |
| 327551000 |
Unwanted signal suppression
| 348 |
| 327564000 |
Integrated structure
| 198 |
| 327525000 |
Fusible link or intentional destruct circuit
| 126 |
| 327574000 |
Utilizing a three or more electrode solid-state device
| 93 |
| 327560000 |
Nonlinear amplifying circuit
| 26 |
| 327594000 |
With particular coupling or decoupling
| 16 |
| 327527000 |
Superconductive (e.g., cryogenic, etc.) device
| 16 |
| 327526000 |
Redundant
| 13 |
| 327583000 |
Utilizing two electrode solid-state device
| 13 |
| 327595000 |
With particular connecting | 3 |
| 20110227641 | EFFICIENT ELECTRICAL HIBERNATE ENTRY AND RECOVERY - Systems and methods for operating of one or more devices before, during, and/or after a power-save mode are provided. The system may include a transmitter device that configures the differential signal lines to low-impedance and a predetermined low-voltage during the power-save mode (such as connecting the differential signal lines to ground). The system may also include a receiver device that senses a wake-up signal, determines the type of wake-up signal, and wakes-up according to the type of wake-up signal. | 09-22-2011 |
| 20120229203 | CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT - A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated. | 09-13-2012 |
| 20140062587 | SEMICONDUCTOR DEVICE HAVING STACKED CHIPS - According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip. | 03-06-2014 |
| 327596000 |
Including oscillatory or shock-excited circuit | 3 |
| 20090033411 | Oscillation Maintentance Circuit For Half Duplex Transponder - An oscillation maintenance circuit for a half-duplex transponder that has an LC resonant circuit, a storage capacitor and a rectifier connected to charge the storage capacitor with a rectified oscillation signal, having an end-of-burst detector providing an end-of-burst signal when the amplitude of the oscillation signal has dropped below a predetermined threshold. A clock regenerator provides a clock signal derived from the oscillation signal. Switching means controlled by the clock signal in the presence of the end-of-burst signal connect the storage capacitor with LC resonant circuit through at least one current limiting resistor during part of the period of the clock signal, in such a manner that energy is fed into the LC resonant circuit. | 02-05-2009 |
| 20100194471 | PERIODIC TIMING JIPERIODIC TIMING JITTER REDUCTION IN OSCILLATORY SYSTEMS - A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable. | 08-05-2010 |
| 20110074499 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal. | 03-31-2011 |
| 327590000 |
With particular feedback | 3 |
| 20090278594 | FRAME-BASED LEVEL FEEDBACK CALIBRATION SYSTEM FOR SAMPLE-BASED PREDICTIVE CLIPPING - A feedback calibration system and a method for controlling an electronic signal are disclosed. The feedback calibration system includes an input controller adapted to modify an input signal in response to a control signal and generate a modified input signal, a signal processing block including a signal analyzer, wherein the signal processing block is adapted to process the modified input signal to generate an output signal and the signal analyzer is adapted to detect an undesirable condition of the output signal and transmit a detection signal corresponding to the undesirable condition, a transfer function estimator adapted to model and transmit a transfer function estimate of the signal processing block in real-time in response to the detection signal, and a programmable device adapted to transmit the control signal to the input controller for modifying the input signal, wherein the control signal is based upon the transfer function estimate. | 11-12-2009 |
| 20110133829 | FEEDBACK CIRCUIT WITH FEEDBACK IMPEDANCE MODULATION FOR IMPROVING POWER SAVING - A feedback circuit with feedback impedance modulation according to the present invention comprises a compare circuit, a counter and a switching resistor circuit. The compare circuit receives a feedback signal of a power converter to compare the feedback signal with a threshold signal for generating a control signal. The feedback signal is correlated to a load condition of the power converter. The counter is coupled to the compare circuit and generates a modulation signal in response to the control signal. The switching resistor circuit is coupled to the counter and a feedback loop of the power converter for modulating a feedback impedance of the power converter in response to the modulation signal. The feedback impedance is directly modulated from a lower resistance to a higher resistance when the load condition is reduced from a half/full-load to a no/light-load. The feedback impedance is gradually modulated from a higher resistance to a lower resistance when the load condition is increased from the no/light-load to the half/full-load. | 06-09-2011 |
| 20120081177 | Signal Transmission Arrangement with a Transformer and Signal Transmission Method - A circuit arrangement with a transmission arrangement is disclosed including a transformer. | 04-05-2012 |
| 327589000 |
With bootstrap circuit | 3 |
| 20080258808 | CIRCUIT TO OPTIMIZE CHARGING OF BOOTSTRAP CAPACITOR WITH BOOTSTRAP DIODE EMULATOR - A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit responsive to the voltage at the switched node and turning ON the first switch when the voltage at the switched node is LOW, whereby charging of the bootstrap capacitor is optimized when the phase sense comparator circuit is enabled, the phase sense comparator circuit turning OFF or keeping OFF the first switch when the first control voltage goes to a level to turn ON the high-side switch or remains at such level or the bootstrap capacitor supply voltage goes high or remains high such that it is a fixed amount above the low-side driver supply voltage; further wherein the phase sense comparator circuit turns the first switch ON when: the second control voltage is at a level adapted to turn ON the low-side switch and the bootstrap capacitor supply voltage is low such that it is below the fixed amount above the low side driver supply voltage; or the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the second control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage goes below the fixed amount above the low-side driver supply voltage; or the first and second control voltages are both at a level such that the high-side and low-side switches are OFF after the first control voltage transitions from an ON state to an OFF state and the bootstrap capacitor supply voltage goes below the fixed amount above the low-side driver supply voltage. | 10-23-2008 |
| 20090309650 | Booster circuit - A booster circuit includes a first capacitance device and a switch which makes a first node and a one end of the first capacitance device conductive or non-conductive in response to a first control signal. The booster circuit applies a voltage, which is applied to the first node, to the one end of the first capacitance device and charges the first capacitance device according to the voltage applied to the first node and a potential of the one end of the first capacitance device is boosted in response to a second control signal thereafter, where the second control signal is applied to an other end of the charged first capacitance device. | 12-17-2009 |
| 20090309651 | BOOSTER CIRCUIT - A booster circuit includes a first booster unit configured to boost a power supply voltage to a predetermined voltage value, a transfer gate transistor transferring the voltage received from the first booster unit to an output terminal, a switching transistor connected between an input terminal receiving the voltage from the first booster unit and a gate electrode of the transfer gate transistor, and a second booster unit configured to boost a voltage applied to a gate electrode of the switching transistor. The second booster unit includes an NMOS booster transistor. A drain electrode of the booster transistor is connected to the output terminal, a source terminal of the booster transistor is connected to a terminal to which a boosted voltage is to be applied, and a gate electrode of the booster transistor is connected to a booster capacitor. | 12-17-2009 |
| 327588000 |
With bridge circuit | 2 |
| 20120326776 | BATTERY POLARITY CONTROL SYSTEM - An input power circuit for a battery-powered device, such as a toy or consumer electronic device, includes a polarity correction circuit portion. The device includes a first input terminal and a second input terminal, a first output terminal and a second output terminal, and a diode with a forward voltage drop of about 0.5 volts or less. In embodiments, the polarity correction circuit portion is configured to provide a positive voltage polarity at the first output terminal and a negative voltage polarity at the second output terminal for any polarity of power at the first input terminal and the second input terminal. The polarity correction circuit portion can include a diode bridge, and the diode may include a Schottky diode or a germanium diode. | 12-27-2012 |
| 20140125406 | SWITCHING SYSTEM AND METHOD FOR CONTROL THEREOF - The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch. | 05-08-2014 |
| 327568000 |
Negative resistance type | 1 |
| 20140247090 | RESONANT IMPEDANCE SENSING BASED ON CONTROLLED NEGATIVE IMPEDANCE - Resonant impedance sensing with a resonant sensor (such as LC) is based on generating a controlled negative impedance to maintain steady-state oscillation in response to changes in resonance state caused by interaction with a target. Resonant impedance sensing can include: (a) generating a controlled negative impedance at the sensor; (b) controlling the negative impedance based on a detected resonance state to substantially cancel the sensor resonant impedance, such that the sensor resonance state corresponds to steady-state oscillation, where the negative impedance is controlled by a negative impedance control loop that includes the sensor resonator as a loop filter; and (c) providing sensor response data based on the controlled negative impedance, such that the sensor response data represents a response of the sensor to the target. Thus, the response of the sensor to the target corresponds to the negative impedance required for steady-state oscillation. | 09-04-2014 |
| 327567000 |
Thin film | 1 |
| 20120098593 | METHOD OF TRIMMING A THIN FILM RESISTOR, AND AN INTEGRATED CIRCUIT INCLUDING TRIMMABLE THIN FILM RESISTORS - Apparatus and methods of trimming resistors are disclosed. In one embodiment, a method of controlling the PCR of a thin film resistor is provided. The method includes applying a first current to a resistor so as to alter a property of the resistor, and measuring the property of the resistor. Applying the first current and measuring the property of the resistor can be repeated until the PCR of the resistor is within an acceptable tolerance of a desired value for the property of the resistor. | 04-26-2012 |
| 327592000 |
With oscillation prevention | 1 |
| 20090261898 | Systems and Methods for Oscillation Suppression in Switching Circuits - A switching circuit configured to reduce the effects of signal oscillation on the operation of the switching circuit is provided. The switching circuit may include signal oscillation and detection circuitry that suppresses control signals during a detected oscillation, allowing stored energy to naturally decay in the switching circuit and thereby prevent unwanted extension of the oscillation that may be caused by the repeated switching of a semiconductor element coupled between the input and output of the switching circuit. | 10-22-2009 |
| 327593000 |
With distributed parameter circuit | 1 |
| 20080309402 | EXTINCTION OF PLASMA ARCS - A circuit configuration reduces electrical energy stored in a lead inductance formed by a plurality of leads that connect a power supply unit with a load. The circuit configuration includes a switching device in operative connection with at least one of the leads for enabling or interrupting power to the load. The circuit configuration also includes a first electrical nonlinear device arranged in parallel with the switching device; an energy storing device arranged in parallel with the switching device and in series with the first electrical nonlinear device; and a pre-charging circuit in operative connection with the energy storing device for charging the energy storing device to a pre-determined voltage level while power to the load is enabled. | 12-18-2008 |
| Entries |
| Document | Title | Date |
|---|
| 20080303583 | Electronics module, method for the manufacture thereof and applications - This publication concerns electronics modules comprising at least one first material zone formed of first material which can be structurally transformed by means of electric interaction in order to increase its conductivity at least locally, the first material having a first transformation threshold, and at least one second material zone in the vicinity of the first material zone. According to the invention, the second material zone is formed from second material, which can also be structurally transformed in order to increase its conductivity, the second material having a second transformation threshold, which is lower than the transformation threshold of the first material zone. With the aid of the invention, post-processing electrical programmability and non-volatility of printable memories can be achieved. | 12-11-2008 |
| 20090051410 | Integrated powered device (PD) and physical layer (PHY) chip - An integrated physical layer (PHY) and powered device (PD) chip for use in a Power over Ethernet (PoE) system is provided. Embodiments reduce circuit size and cost and enable improved and novel PoE applications. Embodiments include one or more of a PHY circuit, a PD controller circuit, a DC-DC converter circuit, and an enterprise Internet Protocol (IP) circuit, integrated within a single integrated circuit (IC) chip. Embodiments are implemented using a floating ground design. Embodiments can be implemented using a mixed-voltage or a “voltage island” design or using a multi-die scheme. | 02-26-2009 |
| 20090184749 | HIGH-RESOLUTION DIGITALLY CONTROLLED TUNING CIRCUIT ELEMENTS - A tuning circuit element for a tuning circuit. The tuning circuit element may include sub-elements for generating circuit values depending on logical values of digital control input signals. The tuning circuit element may be implemented with varactors, current sources, and other components or circuits. The tuning circuit element may be configured to have fine tuning resolution that is not necessarily limited by minimum feature size of a given fabrication process technology. | 07-23-2009 |
| 20090201074 | Method and Circuit for Implementing Efuse Sense Amplifier Verification - A method and circuit for implementing Efuse sense amplifier verification, and a design structure on which the subject circuit resides are provided. A first predefined resistor value is sensed relative to a reference resistor. A second predefined resistor value is sensed relative to a reference resistor. Responsive to identifying a respective sense amplifier output resulting from the sensing steps of an unblown eFuse and a blown eFuse, valid operation of the sense amplifier is identified. | 08-13-2009 |
| 20090237143 | CAPACITANCE MULTIPLIER CIRCUIT - A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (i | 09-24-2009 |
| 20090267681 | Integrated Circuit and Method of Configuring an Integrated Circuit - An integrated circuit comprises an output terminal to be coupled to a non-linear circuit element, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the non-linear circuit element, a measuring circuit coupled to the output terminal, the measuring circuit being configured to sense on the output terminal a signal value outside an operating regime of the non-linear circuit element, and a control circuit coupled to the measuring circuit, the control circuit being configured to configure at least one function of the integrated circuit on the basis of the signal value sensed by the measuring circuit. | 10-29-2009 |
| 20090289694 | Current-Sensing Apparatus and Method for Current Sensing - At least one embodiment of the invention specifies a current-sensing apparatus and/or a method for its operation which is based on the current sensor provided being a GMR sensor in the form of a gradient sensor and on the gradient sensor, or a component which includes this gradient sensor, itself including a conductor section of a compensating circuit. As such, the current in the measurement circuit can be compensated for by a current in the compensating circuit and the compensating current can be evaluated as a measure of the electrical variable to be detected for the measurement circuit. | 11-26-2009 |
| 20090295461 | DEVICE CONFIGURATION - A process and apparatus for configuring one or more integrated circuits within a device in a manufacturing process is described. In an exemplary process, a device is manufactured by assembling a chip onto a board such as a printed circuit substrate and the chip is fused from power routed across the board to the chip. The power source for the fusing can be generated from the internal power supply on the board or received on a test point on the board itself or a connection interface (e.g. a USB interface) coupled to the board. In an exemplary apparatus, a device comprises a chip with a plurality of fuses that are used to configure the device and a board coupled to the chip, with the board capable of routing power from the board to the chip and the power is used to blow one or more of the plurality of fuses. | 12-03-2009 |
| 20100001786 | CLOCK GENERATION FOR MEMORY ACCESS WITHOUT A LOCAL OSCILLATOR - A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator. | 01-07-2010 |
| 20100090749 | MULTI-FUNCTION CHIP - A multi-function chip including a circuit and at least one control circuit is provided. The circuit having multiple functions includes an interconnection. The interconnection has at least one resistance-variable segment. The control circuit is electronically connected to the resistance-variable segment. One of the functions is carried out by adjusting the resistance of the resistance-variable segment with the control circuit. | 04-15-2010 |
| 20100201433 | Low Leakage Sampling Switch - An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/drain path of a first transistor drives a sampling capacitor. The second terminal of the source/drain channel of each subsequent transistor is connected to a backgate of a previous transistor. The backgate of the last transistor is connected to a supply voltage level. The second terminals of the subsequent transistors may be connected to corresponding buffer capacitors. The backgate of the last transistor may be supplied with the input during sampling and the supply voltage level at other times. | 08-12-2010 |
| 20100231288 | LOCAL INTERCONNECT NETWORK RECEIVER - The present invention relates to a LIN receiver having sleep/wake-up functionality, which has an input (LINI) to a LIN bus (LIN), an output (RXDO), terminals for at least one supply voltage (BVDD), and transistors (M | 09-16-2010 |
| 20100289555 | CAPACITANCE INTERFACE CIRCUIT - A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased. | 11-18-2010 |
| 20100308895 | INPUT VECTOR SELECTION FOR REDUCING CURRENT LEAKAGE IN INTEGRATED CIRCUITS - Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed. | 12-09-2010 |
| 20110032024 | Integrated Circuit and Related Method for Determining Operation Modes - An integrated circuit and a related method for determining an operation mode are disclosed. The exemplified integrated circuit includes a controller, a multi-function pin, and a mode determination circuit. The controller controls a power switch and is being set to operate in one of the operation modes including a first operation mode and a second operation mode. The multi-function pin is connected to an external resistor. The mode determination circuit detects a signal from the multi-function pin. The signal represents the resistance of the external resistor. If the resistance is within a first range, the controller is operated in the first operation mode. If the resistance is within a second range, the controller is operated in the second operation mode. | 02-10-2011 |
| 20110043275 | SYSTEM AND METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT IN DIFFERENT OPERATIONAL MODES - A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register. | 02-24-2011 |
| 20110102064 | Electronic Age Detection Circuit - An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit. | 05-05-2011 |
| 20110102065 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal. | 05-05-2011 |
| 20110102066 | SEMICONDUCTOR APPARATUS AND CHIP SELECTION METHOD THEREOF - A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips. | 05-05-2011 |
| 20110128067 | TRIMMING OF OPERATIVE PARAMETERS IN ELECTRONIC DEVICES BASED ON CORRECTIONS MAPPINGS - An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions to select one of the trimming actions providing a target value of the reference parameter, and means for forcing the application of the selected trimming action for the reference parameter. For each non-reference parameter different from the at least one reference parameter, the electronic device includes means for selecting one of the trimming actions for the non-reference parameter corresponding to the selected trimming action for the at least one reference parameter according to a predetermined mapping of each group of multiple corrections of the at least one reference parameter on a single correction of the non-reference parameter, and means for forcing the application of the selected trimming action for each non-reference parameter. | 06-02-2011 |
| 20110241760 | CONTROL CIRCUIT, CONTROL DEVICE, CONTROL METHOD, AND IMAGE FORMING APPARATUS - A control circuit comprising an input-output unit that is connected to a signal line, which is connected to an external apparatus, and which is connected to a resistor that is one of a pull-up resistor and a pull-down resistor; a switching unit that switches a mode of the input-output unit to one of an input mode and an output mode, wherein the output mode includes an on-voltage output mode and an off-voltage output mode; an acquisition unit that acquires information regarding whether the resistor connected to the signal line is the pull-up resistor or the pull-down resistor, when the input-output unit is in the input mode; and a control unit that controls the input-output unit to switch to one of the on-voltage output mode and the off-voltage output mode based on the acquisition information acquired by the acquisition unit, when the input-output unit is in the output mode. | 10-06-2011 |
| 20110248774 | ELECTRONIC DEVICE WITH A CARRIER CURRENT - A device comprising both a box containing an electronic central unit, and power supply module connected to the central unit. The device also includes an external power supply block connected to the module by an electric cable and provided with both a connection member for connection to a power supply network delivering AC power and a data signal superposed thereon. A converter is provided for converting the AC power. The box includes a carrier current data transmission module, the converter being connected to the connection member and to the electric cable via a first diverter member that extracts and diverts the data signal relative to the converter. The module is connected to the electric cable by a second diverter member for separating the converted power supply current and the data signal and for bringing the power supply current to the power supply module and the data signal to the transmission module. | 10-13-2011 |
| 20110316612 | SEMICONDUCTOR CARRIER WITH VERTICAL POWER FET MODULE - A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET. | 12-29-2011 |
| 20120001679 | HIGH-PRECISION RESISTOR AND TRIMMING METHOD THEREOF - An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion. | 01-05-2012 |
| 20120019309 | AUDIO JACK DETECTION AND CONFIGURATION - This document discusses, among other things, an audio jack detection circuit configured to be coupled to an audio jack receptacle of an external device. The audio jack detection circuit configured to receive to receive audio jack receptacle information, to disable an oscillator when the audio jack receptacle information indicates that the audio jack receptacle is empty, and to enable the oscillator when the audio jack receptacle information indicates that the audio jack receptacle includes an audio jack. | 01-26-2012 |
| 20120025898 | Circuit Device - A circuit device includes an option pad, a first power source pad, and a first ground pad, wherein the option pad, the first power source pad, and the first ground pad are formed over various portions of a top surface of the circuit device, and a function of the circuit device is determined by coupling the option pad with one of the first power source pad and the first ground pad through a wire bond. | 02-02-2012 |
| 20120105134 | Method and Device for Sharing Pin and Functional Device Using the Same - A pin sharing method for controlling a plurality of functions of a chip via a versatile pin of the chip is disclosed. The pin sharing method includes dividing a voltage range of the versatile pin into a plurality of sections according to the plurality of functions, and assigning the plurality of sections to correspond to a plurality of modes of the plurality of functions. | 05-03-2012 |
| 20120105135 | INTEGRATED CIRCUIT CAPACITOR - An electrical circuit for emulating a capacitance, comprises a physical capacitor which is charged by charge flow from the input of the electrical circuit. An amplifier amplifies the voltage at the input of the electrical circuit such that the physical capacitor is charged with a larger change in voltage than the change in voltage at the input. This implements an effective multiplication of capacitance. A reset system resets the physical capacitor without drawing charge from the input of the electrical circuit. This extends the voltages which can be provided to the input. | 05-03-2012 |
| 20120133423 | SEMICONDUCTOR APPARATUS, SEMICONDUCTOR SYSTEM, AND METHOD FOR OUTPUTTING INTERNAL INFORMATION THEREOF - A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals. | 05-31-2012 |
| 20120161854 | DATA INPUT/OUTPUT DEVICE, INFORMATION PROCESSING DEVICE, AND DATA INPUT/OUTPUT METHOD - A data input/output device includes a buffer that accumulates data, and a data receiver that receives data input in synchronization with a first clock in accordance with a second clock whose generation source is different from a generation source of the first clock. The data input/output device further includes a data input part that accumulates data received by the data receiver in the buffer, and a data output part that sequentially outputs data accumulated in the buffer at an output interval depending on the amount of data accumulated in the buffer in such a manner that a predetermined data amount is the unit of the output. | 06-28-2012 |
| 20120326768 | Hybrid Impedance Compensation in a Buffer Circuit - A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions. | 12-27-2012 |
| 20120326769 | ARCHITECTURE AND METHOD FOR SUPPORTING ZIF OR LIF/IF SYSTEMS - Architecture for supporting ZIF or LIF/IF systems includes 4N pins, 2N ADCs, a determination unit and a processing unit, N being a positive integer. The 2N ADCs include a y-th ADC for converting a differential analog signal received by a (2y−1)-th pin and a 2y-th pin into a y-th digital signal, y being positive integers ranging from 1 to 2N. The determination unit determines whether the digital signals are ZIF signals, LIF signals or IF signals. The processing unit performs an ZIF system processing on the ZIF signals, performs a LIF system processing on the LIF signals, and performs an IF system processing on the IF signals. | 12-27-2012 |
| 20130002342 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes first and second chips sharing first and second data channels. The first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation. | 01-03-2013 |
| 20130038380 | IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK - A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack. | 02-14-2013 |
| 20130214849 | TERMINAL DEVICE AND METHOD FOR REALIZING ANALOGUE CIRCUIT IN TERMINAL DEVICE - Disclosed are a terminal device and a method for realizing an analogue circuit in the terminal device. The terminal device includes control device and programmable analogue circuit device. The control device includes: acquisition module, configured to acquire the configuration data information corresponding to the function index and the parameter index of a target analogue circuit, wherein the configuration data information is configured to indicate the on/off state of an interconnection switch between CABs; downloading module, configured to download the configuration data information to the programmable analogue circuit device; and restart module, configured to restart the programmable analogue circuit device. The programmable analogue circuit device includes: a configurable analogue array module, configured to configure the parameters and/or the connection relationship of the CABs by using the configuration data information. The disclosure enhances the fault tolerance of the system, and improves the resource utilization rate. | 08-22-2013 |
| 20130285736 | Multi-Value Logic Signaling in Multi-Functional Circuits - An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to he operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit. | 10-31-2013 |
| 20130307611 | MULTI-CHIP PACKAGE AND OPERATING METHOD THEREOF - A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one. | 11-21-2013 |
| 20130342264 | ELECTRICALLY TRIMMABLE RESISTOR DEVICE AND TRIMMING METHOD THEREOF - An integrated circuit has a circuit part and a trimmable resistor, the resistance whereof may be modified by Joule effect. The trimmable resistor has first and second connection terminals coupled to the circuit part, and an intermediate terminal that divides the trimmable resistor into two portions. The first and the second connection terminals and the intermediate terminal are coupled to respective pads configured to receive electrical quantities designed to cause, in use, a respective trimming current flow in each portion. In this way, a substantially zero voltage drop is maintained between the first and second connection terminals while current is flowing in the resistor to change an electrical characteristic of the resistor, such as resistance or thermal coefficient. | 12-26-2013 |
| 20140015598 | SEMICONDUCTOR DEVICE PACKAGES INCLUDING THERMALLY INSULATING MATERIALS AND METHODS OF MAKING AND USING SUCH SEMICONDUCTOR PACKAGES - Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material. | 01-16-2014 |
| 20140028380 | PREVENTING INTERFERENCE BETWEEN MICROCONTROLLER COMPONENTS - A microcontroller includes first and second modules. The first module can operate in a mode that causes interference with operation of the second module. A control circuit on the first module and a control circuit on the second module coordinate operation of the first and second modules to prevent the interference from causing the second module to function incorrectly. | 01-30-2014 |
| 20140097886 | SYSTEMS, METHODS, AND APPARATUS FOR CONTROLLING POWER SEMICONDUCTOR DEVICES - Systems, methods, and apparatus for controlling power semiconductor devices are described. According to one embodiment of the disclosure, there is disclosed a system. The system may include at least one power source for selectively providing power to one or more power semiconductor devices controlled by a gate driver. The gate driver may include at least one controller coupled to at least one power semiconductor device interface via a first channel and a second channel configured to provide galvanic isolation of information communicated between the controller and the at least one power semiconductor device interface. | 04-10-2014 |
| 20140184314 | SEMICONDUCTOR DEVICE - A coulomb counter is provided. In the coulomb counter, a current generated on charge or discharge of a secondary battery is converted into a voltage by a resistor, and the voltage is amplified by an amplifier circuit. The voltage amplified by the amplifier circuit is converted into a current by a voltage-current converter circuit, and the current is input to a cumulative addition circuit. The cumulative addition circuit charges a capacitor with the current input from the voltage-current converter circuit and generates a signal corresponding to a voltage generated across the capacitor. One terminal of the capacitor is connected to an output of the voltage-current converter circuit through a switch, and the other terminal of the capacitor is supplied with a constant potential. By on/off of the switch, supply of electric charge to the capacitor and storage of the electric charge can be controlled. | 07-03-2014 |
| 20140191796 | SEMICONDUCTOR DEVICE AND COMMAND CONTROL METHOD FOR THE SAME - According to an aspect of the present invention, in a semiconductor device, a plurality of commands for specifying a circuit configuration of an analog front-end unit are transmitted from a processing unit to the analog front-end unit, an analysis is performed on the plurality of commands received by the analog front-end unit, and when a circuit configuration of the analog front-end unit which is to be updated and is determined according to the plurality of commands includes a forbidden condition that has been previously set, updating processing of the circuit configuration according to the plurality of commands is stopped. | 07-10-2014 |
| 20160018807 | SENSOR INTERFACE WITH VARIABLE CONTROL COEFFICIENTS - The present disclosure is directed towards a sensor interface module that delivers a supply voltage to a plurality of sensors, and which exchanges data signals between the plurality of sensors and a control unit (e.g., an ECU). The sensor interface often employs a single-bit comparator (or a coarse analog to digital converter (ADC), e.g., a 2-bit or 3-bit ADC) to track signals to be exchanged between the sensors and controller over the sensor interface. Compared to power hungry ADC with more bits (e.g., 32 bit ADC), the single-bit comparator/coarse ADC limits hardware complexity and power consumption. In addition, in some embodiments the sensor interface module can include an estimator and assist comparators to speed up the tracking ability of the sensor interface module. In this way, techniques provided herein facilitate reliable, low-power communication between a control unit (e.g., an ECU) and its corresponding sensors. | 01-21-2016 |
