| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327278000 | Having specific active circuit element or structure (e.g., complementary transistors, etc.) | 33 |
| 20080197905 | FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS - A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer. | 08-21-2008 |
| 20090243689 | DELAY LINE CIRCUIT - Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals. | 10-01-2009 |
| 20090309644 | METHOD AND APPARATUS TO LIMIT CIRCUIT DELAY DEPENDENCE ON VOLTAGE - The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant. | 12-17-2009 |
| 20100117705 | Semiconductor integrated circuit device having plural delay paths and controller capable of Blocking signal transmission in delay path - A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path. | 05-13-2010 |
| 20110001537 | DELAY LINE - A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation width and a number of second delay blocks having a delay amount with a second variation width in response to a second delay control code, wherein the delay amount with the first variation width and the delay amount with the second variation width are determined by the delay amount adjusting unit and the first and second variation widths correspond to a level change of a power supply. | 01-06-2011 |
| 20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
| 20120068753 | ANALOG DELAY LINES AND ADAPTIVE BIASING - Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line. | 03-22-2012 |
| 20130314140 | ANALOG DELAY LINES AND ADAPTIVE BIASING - Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line. | 11-28-2013 |
| 20140077857 | CONFIGURABLE DELAY CIRCUIT - One embodiment sets forth a technique for delaying signals by varying amounts. A configurable delay circuit includes fixed and tri-state inverters. Pullup and pulldown transistors within one or more tri-state inverters may be activated to reduce the delay introduced by fixed inverters. The pullup and pulldown transistors within one or more tri-state inverters may be separately activated to independently adjust the rising delay and the falling delay incurred by the input signal. | 03-20-2014 |
| 20140167829 | DELAY METHOD, CIRCUIT AND INTEGRATED CIRCUIT - This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay. | 06-19-2014 |
| 20140300398 | PROGRAMMABLE DELAY CIRCUIT - A delay circuit includes at least one main inverter configured to receive an input signal and output a delayed output signal and at least one switchable inverter connected in parallel with the main inverter circuit. The switchable inverter is configured to decrease a delay between the input signal and the delayed output signal based on the switchable inverter being turned on. | 10-09-2014 |
| 20150349764 | Flip-Flop Having Integrated Selectable Hold Delay - A circuit includes a flip-flop and a delay circuit integrated with the flip-flop, the delay circuit including at least one delay element, the flip-flop and delay circuit having a predefined architecture such that a delay provided by the delay circuit may have a selectable value while the flip-flop remains within the predefined architecture. | 12-03-2015 |
| 327279000 | With counter | 2 |
| 20140312952 | ANALOG DELAY LINES AND ADAPTIVE BIASING - Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line. | 10-23-2014 |
| 20140320189 | PROGRAMMABLE BUS SIGNAL HOLD TIME WITHOUT SYSTEM CLOCK - A circuit is disclosed that provides a programmable hold time for a bus signal without running a system clock and without a frequency requirement between the system clock and a bus clock. | 10-30-2014 |
| 327280000 | Differential amplifier | 3 |
| 20080272818 | VOLTAGE-CONTROLLED OSCILLATOR GENERATING OUTPUT SIGNAL FINELY TUNABLE IN WIDE FREQUENCY RANGE AND VARIABLE DELAY CIRCUITS INCLUDED THEREIN - A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other. | 11-06-2008 |
| 20100019819 | Delay Circuit - Constant delay circuit includes signal input end, delay signal output end, RC delay circuit, and a comparator. The signal input end receives an input signal. The delay signal output end outputs the delay input signal, which the delay period is predetermined. The RC delay circuit is coupled to the signal input end for receiving the input signal and generating a voltage. The comparator includes a first input end, a second input end, and an output end. The first end of the comparator is coupled to the RC delay circuit for receiving the voltage. The second end of the comparator receives a reference voltage. The output end of the comparator is coupled to the delay signal output end of the long delay circuit. The comparator compares the reference voltage and the voltage, and accordingly generates a result as the delay signal. | 01-28-2010 |
| 20150028930 | Variable Delay Element - A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor. | 01-29-2015 |
| 327281000 | Field-effect transistor | 16 |
| 20090033397 | Delay time adjusting method of semiconductor integrated circuit - The delay time variation of transistors caused by the manufacturing variation is desired to be adjusted. A relation table storing a relation between sizes and voltage values (supply voltages and bias voltages) is provided. Macros each of which includes a transistor and a setting voltage generation circuit for applying a setting voltage to the transistor are formed on a chip. A process data indicating a size of the transistor is generated. The voltage value corresponding to the size of the transistor indicated by the process data in the relation table is selected as an optimum voltage value (supply voltage Vdd, bias voltage Bias) for each of the macros. The setting voltage of each of the macros is set to the optimum voltage value. The delay time can be adjusted without requiring a detection circuit for detecting the delay time. | 02-05-2009 |
| 20090039939 | VARIABLE DELAY CIRCUIT, TESTING APPARATUS, AND ELECTRONIC DEVICE - Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal. | 02-12-2009 |
| 20090167399 | SIGNAL DELAY CIRCUIT - A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal. | 07-02-2009 |
| 20100164586 | PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS - A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output. | 07-01-2010 |
| 20110267126 | DELAY CIRCUIT OF SEMICONDUCTOR DEVICE - A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage. | 11-03-2011 |
| 20110291731 | Integrated circuit with timing adjustment mechanism - An integrated circuit | 12-01-2011 |
| 20120249206 | VARIBLE DELAY CIRCUIT - A variable delay circuit includes delay units connected in series. Each delay unit includes first to third logic gates. The first logic gates are connected in series so that the output of the previous stage is input to one of inputs of the subsequent stage and first control data is input to the other of the inputs. In each stage, one of inputs of the second logic gate is connected to the one of the inputs of the first logic gate and second control data is input to the other of the inputs. The third logic gates are connected in series, the output of the second logic gate is input to third logic gate, and the delay time of a path from one of the inputs to the output and the delay time of a path from the other of the inputs to the output are substantially the same. | 10-04-2012 |
| 20130043923 | UNIFORM-FOOTPRINT PROGRAMMABLE MULTI-STAGE DELAY CELL - Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages. | 02-21-2013 |
| 20130321054 | UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL - Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell. | 12-05-2013 |
| 20140320190 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 10-30-2014 |
| 20150303908 | CLOCK SIGNAL CONTROLLER - The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals. | 10-22-2015 |
| 20160028386 | DELAY CIRCUIT - A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current. | 01-28-2016 |
| 20160056805 | DELAY APPARATUS - The delay apparatus according to an embodiment includes a logic circuit that is connected between a first potential line and a first node and is driven by a driving current supplied from the first potential line. The delay apparatus includes a driving current adjusting circuit that is connected in a current path through which the driving current flows between the first node and a second potential line and adjusts the driving current of the logic circuit. The delay apparatus includes a supplying circuit that supplies a voltage or current to the first node. The delay apparatus includes a measuring circuit that measures the voltage or current at the first node. The delay apparatus includes a controlling circuit that controls the voltage or current output from the supplying circuit based on the measured voltage or measured current at the first node measured by the measuring circuit. | 02-25-2016 |
| 20160118968 | CIRCUIT AND METHOD OF OPERATING CIRCUIT - A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal. | 04-28-2016 |
| 20160118969 | DELAY ADJUSTING APPARATUS AND OPERATING APPARATUS INCLUDING THE SAME - A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal. | 04-28-2016 |
| 20160380624 | DELAY CELL IN A STANDARD CELL LIBRARY - A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal. | 12-29-2016 |
