| Entries |
| Document | Title | Date |
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| 20080204100 | Logic circuit - For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit. | 08-28-2008 |
| 20080211558 | Structure for Radiation Hardened Programmable Phase Frequency Divider Circuit - A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. | 09-04-2008 |
| 20080218234 | LOW POWER FLIP-FLOP CIRCUIT - A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal. | 09-11-2008 |
| 20080258789 | Flip-flop and semiconductor integrated circuit - A flip-flop is disclosed which includes: a clock supply circuit configured to output or fix a clock signal alternating between two predetermined states in accordance with a sleep signal; a first holding circuit configured to fetch or hold an input signal in accordance with a state the clock signal indicates; a second holding circuit configured to fetch or hold a first signal output by the first holding circuit in accordance with a state the clock signal indicates; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit or to supply an external signal as the input signal in accordance with the hold signal; and a power supply control circuit configured to supply or not to supply power to the first holding circuit and the input switching circuit in accordance with a power supply control signal. | 10-23-2008 |
| 20080265962 | SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD - A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal. | 10-30-2008 |
| 20080297219 | EQUAL DELAY FLIP-FLOP BASED ON LOCALIZED FEEDBACK PATHS - Equal delay flip-flop systems and complementary input complementary output equal delay flip-flop circuits are disclosed. In one embodiment, an equal delay flip-flop system includes a first delay flip-flop for processing a first input, including a first tri-state input driver for driving the first input, a first master latch for sampling and/or forwarding the first input, a first transmission gate for relaying the first input forwarded by the first master latch, and a first slave latch for storing and/or forwarding the first input. The equal delay flip-flop system further includes a second delay flip-flop for processing a second input, including a second tri-state input driver for driving the second input, a second master latch for sampling and/or forwarding the second input, a second transmission gate for relaying the second input forwarded by the second master latch, and a second slave latch for storing and/or forwarding the second input. | 12-04-2008 |
| 20080315932 | PULSED STATE RETENTION POWER GATING FLIP-FLOP - A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal. | 12-25-2008 |
| 20090039936 | Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit - Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A flip-flop circuit may include a precharge transistor configured to precharge an internal node to a first power supply voltage in response to a clock signal, a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node, and a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage. The pipeline circuit may include a pulse generating circuit, a first flip-flop group, a combination logic circuit, and a second flip-flop group. A method for operating a flip-flop circuit may include precharging an internal node to a first power supply voltage in response to a clock signal, pulling down a voltage of the internal node, pulling down the voltage to a second power supply voltage in response to a first pulse signal, and pulling up a voltage of an output node to the first power supply voltage. | 02-12-2009 |
| 20090058484 | Slave latch controlled retention flop with lower leakage and higher performance - In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input. | 03-05-2009 |
| 20090066385 | LATCH DEVICE HAVING LOW-POWER DATA RETENTION - A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit. | 03-12-2009 |
| 20090066386 | MTCMOS FLIP-FLOP WITH RETENTION FUNCTION - There is provided a MTCMOS flip-flop configured to operate at high speed and to reduce leakage current while realizing a retention function in a sleep mode. The MTCMOS flip-flop may include a signal generator adapted to output an internal clock signal or a sleep mode control signal based on changes in a retention signal and an external clock signal, a master latch adapted to latch an input signal and to output a master latch output signal based on the internal clock signal, and a slave latch connected to an actual ground and adapted to latch the master latch signal, to output a slave latch output signal under control of the internal clock signal, and to maintain the latched signal under control of the sleep mode control signal in the sleep mode. | 03-12-2009 |
| 20090085626 | Semiconductor integrated circuit and method for controlling semiconductor integrated circuit - When a master circuit is in an inactive state, a slave circuit assigned to the master circuit is not used. Accordingly, the use efficiency of system recourses is decreased. To solve the above problem, a semiconductor integrated circuit reassigns a M2 region of a slave circuit, previously assigned to a first master circuit, to a second master circuit. That is to say, the M2 region of the slave circuit previously assigned to the first master circuit is reassigned to the second master circuit based on the operational status of the first master circuit. This improves the use efficiency of system resources of the semiconductor integrated circuit. | 04-02-2009 |
| 20090102531 | Semiconductor Integrated Circuit - [Problems] To provide a semiconductor integrated circuit by which what has been referred to as two-pattern test is made possible without greatly increasing an occupying area. | 04-23-2009 |
| 20090108896 | Semiconductor Integrated Circuit Apparatus - It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to operate based on a rising edge or a falling edge of a first clock signal; a decision circuit configured to compare an input of the flip-flop with an output thereof and output a request signal when the input of the flip-flop is different from the output thereof; and a control circuit configured to receive a second clock signal from outside and generate the first clock signal and a confirmation signal. When the request signal is sent from the decision circuit after the flip-flop has been activated, the control circuit inverts the first clock signal, sends the confirmation to the decision circuit, and makes the decision circuit cancel the request signal. | 04-30-2009 |
| 20090128210 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC CIRCUIT - An electric circuit has a first differential circuit for transmitting input data to a first node, a second differential circuit for holding the first node data, a first clock transmission circuit for flowing a first current in accordance with a clock signal, and a first transformer circuit for transformer-coupling the first differential circuit with the first clock transmission circuit, and the second differential circuit with the first clock transmission circuit. | 05-21-2009 |
| 20090189664 | STATE RETAINING POWER GATED LATCH AND METHOD THEREFOR - A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current. | 07-30-2009 |
| 20090201063 | DYNAMIC SEMICONDUCTOR DEVICE - A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased. | 08-13-2009 |
| 20090231008 | FLIP-FLOP CIRCUIT THAT LATCHES INPUTTED DATA - A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude. | 09-17-2009 |
| 20090251185 | DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS - A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal. | 10-08-2009 |
| 20090256608 | Low leakage data retention flip flop - A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current. | 10-15-2009 |
| 20090267671 | OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT - Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions. | 10-29-2009 |
| 20090267672 | SERIAL PERIPHERAL INTERFACE (SPI) CIRCUIT AND DISPLAY USING THE SAME - A serial peripheral interface (SPI) circuit and a display using the same are provided. The SPI circuit includes a mater device and a slave device. A serial data input pin and a serial data output pin of the slave device are both electrically connected to a data input/output pin of the master device. When a read instruction is sent from the master device to the slave device, the master device is set in a read status, and the slave device outputs data to the master device via the serial data output pin in response to the read instruction. When a write instruction is sent from the master device to the slave device, the master device is set in a write status, and writes data to the slave device via the serial data input pin thereof in response to the write instruction. | 10-29-2009 |
| 20090309640 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING A MASTER-SLAVE FLIP-FLOP - A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and a second clock signal with a timing so that logic of data retained in a first data retaining terminal becomes identical to logic of data retained in a third data retaining terminal, and then turns on a first switching circuit to connect between the first data retaining terminal and the first data retaining terminal. | 12-17-2009 |
| 20090315603 | DETECTION OF A DISTURBANCE IN THE STATE OF AN ELECTRONIC CIRCUIT FLIP-FLOP - A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of the first flip-flops in the group are, independently from their functional purpose, combined to provide a signal and its inverse, triggering two second flip-flops having data inputs forced to a same state, the respective outputs of the second flip-flops being combined to provide the result of the detection; and a pulse signal comprising a pulse at least for each triggering edge of one of the first flip-flops in the group initializes the second flip-flops. | 12-24-2009 |
| 20100001774 | Data retention flip flop for low power applications - A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated. | 01-07-2010 |
| 20100007396 | COMPOUND LOGIC FLIP-FLOP HAVING A PLURALITY OF INPUT STAGES - A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function. | 01-14-2010 |
| 20100019815 | Circuits and Methods Employing a Local Power Block for Leakage Reduction - A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion. | 01-28-2010 |
| 20100026358 | PROTECTION AGAINST FAULT INJECTIONS OF AN ELECTRONIC CIRCUIT WITH FLIP-FLOPS - A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance. | 02-04-2010 |
| 20100102867 | SENSE AMPLIFIER BASED FLIP-FLOP - A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes. | 04-29-2010 |
| 20100141322 | Non-Volatile State Retention Latch - Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit can be maintained even while power is removed from the electronic device. | 06-10-2010 |
| 20100156494 | LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF OPERATING A DFF - A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path. | 06-24-2010 |
| 20100176859 | Self-Protecting Core System - The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct. | 07-15-2010 |
| 20100259309 | STATE-RETENTIVE MASTER-SLAVE FLIP FLOP TO REDUCE STANDBY LEAKAGE CURRENT - A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation. Similarly, a separate always-on power supply powers the slave flip flop and standby mode control circuit during active mode and standby mode operation to enable state retention. | 10-14-2010 |
| 20100264972 | FAST FLIP-FLOP STRUCTURE WITH REDUCED SET-UP TIME - A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch. | 10-21-2010 |
| 20100301914 | LATCH WITH CLOCKED DEVICES - A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node. | 12-02-2010 |
| 20100308881 | SEMICONDUCTOR DEVICE - A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line. | 12-09-2010 |
| 20110001535 | SEQUENTIAL CIRCUIT WITH DYNAMIC PULSE WIDTH CONTROL - A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit. | 01-06-2011 |
| 20110025393 | Leakage Power Optimized Structure - A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND gate, and a first NAND gate output for providing the first output signal. The second NAND gate includes the second A input for receiving the second input signal, a second B input connected to the first NAND gate output, a second leakage current control input connected to the first A input of the first NAND gate, and the second NAND gate output for providing the second output signal. The leakage current through the first NAND gate is substantially reduced based on application of the second input signal to the first leakage current control input. Similarly, the leakage current through the second NAND gate is substantially reduced based on application of the first input signal to the second leakage current control input. This circuit may comprise a set-reset latch in an output stage of an edge-triggered sequential switching device, such as a D flip-flop or a JK master-slave flip-flop. | 02-03-2011 |
| 20110025394 | LOW LATENCY SYNCHRONIZER CIRCUIT - A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal. | 02-03-2011 |
| 20110148496 | LEAKAGE CURRENT REDUCTION IN A SEQUENTIAL CIRCUIT - A system and device for reducing leakage current in a sequential circuit is disclosed. In one embodiment, a system for reducing leakage current in a sequential circuit includes a combinational logic circuit, one or more reset flip-flops coupled to the combinational logic circuit, and one or more set-reset flip-flops coupled to the combinational logic circuit. The system further includes a control module coupled to the reset flip-flops and to the set flip-flops and configured to reset the reset flip-flops and to set the set-reset flip-flops when a standby mode of the sequential circuit is triggered. | 06-23-2011 |
| 20110187430 | Multi-Chip Module with Master-Slave Analog Signal Transmission Function - The present invention discloses a multi-chip module with master-slave analog signal transmission function. The multi-chip module comprises: a master chip having a first setting input pin for receiving an analog setting signal to generate an analog setting in the master chip, and the master chip duplicating the analog setting to output a first analog output; and a first slave chip for receiving the first analog output from the master chip to generate an internal setting of the first slave chip. | 08-04-2011 |
| 20110234283 | Scan/Scan Enable D Flip-Flop - In accordance with an embodiment, an integrated circuit comprises a master-slave flip-flop, a selection logic circuit, and a pass structure. The selection logic circuit is configured to selectively enable or disable one or more clock signals. The pass structure is configured to pass a data signal to the master-slave flip-flop in response to a selected clock signal being enabled. | 09-29-2011 |
| 20110241744 | LATCH-BASED IMPLEMENTATION OF A REGISTER FILE FOR A MULTI-THREADED PROCESSOR - A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided. | 10-06-2011 |
| 20110248759 | RETENTION FLIP-FLOP - A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal. | 10-13-2011 |
| 20110260764 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE RECORDING MEDIUM - A method for designing a semiconductor integrated circuit according to an embodiment includes: placing standard flip-flop circuits and low power-consumption flip-flop circuits; grouping the placed flip-flop circuits into clusters by using an evaluation function having indices including cell types; assigning a first clock buffer to each cluster formed only by standard flip-flop circuits; assigning a second clock buffer to each cluster including low power-consumption flip-flop circuits, the second clock buffer having a larger size than the first clock buffer; and performing clock wiring. | 10-27-2011 |
| 20110260765 | PHASE INTERLEAVING CONTROL METHOD FOR A MULTI-CHANNEL REGULATOR SYSTEM - A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner. | 10-27-2011 |
| 20110298516 | Clock state independent retention master-slave flip-flop - A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path | 12-08-2011 |
| 20110298517 | Master-slave flip-flop circuit - A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal. | 12-08-2011 |
| 20120068749 | MASTER-SLAVE FLIP-FLOP WITH TIMING ERROR CORRECTION - A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal. | 03-22-2012 |
| 20120146697 | SCANNABLE FLIP-FLOP WITH HOLD TIME IMPROVEMENTS - Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer. | 06-14-2012 |
| 20120154008 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a master chip, first to n | 06-21-2012 |
| 20120169392 | MIN-TIME HARDENDED PULSE FLOP - A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit. | 07-05-2012 |
| 20120182055 | FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC. | 07-19-2012 |
| 20120182056 | LOW ENERGY FLIP-FLOPS - Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes. | 07-19-2012 |
| 20120229187 | Storage circuitry and method with increased resilience to single event upsets - Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs. | 09-13-2012 |
| 20120249204 | FLIP-FLOP CIRCUIT, SCAN TEST CIRCUIT, AND METHOD OF CONTROLLING SCAN TEST CIRCUIT - Provided is a flip-flop circuit which a small-sized test circuit with hold free and can perform test in an actual operating frequency. A Pos-type F/F includes a master latch (Low level latch) that selectively receives data or scan test data in synchronization with a rising edge of a clock signal, and a slave latch (High level latch) that receives the data from the master latch. In a scan shift operation, the master latch captures scan data signal input SIN in a Low period of a scan shift clock signal SCLK | 10-04-2012 |
| 20120280736 | CIRCUIT AND METHOD FOR REDUCING THE PROPAGATION OF SINGLE EVENT TRANSIENT EFFECTS - Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages. | 11-08-2012 |
| 20130021076 | DEVICE WITH A DATA RETENTION MODE AND A DATA PROCESSING MODE - A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal. | 01-24-2013 |
| 20130033295 | CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS - Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal. | 02-07-2013 |
| 20130043921 | GLITCH HARDENED FLOP REPEATER - A repeater circuit is disclosed. The circuit includes an input stage configured to receive an input signal and a clock signal. An output stage is configured to drive an output signal on an output node to a first state responsive to a first transition of the input signal on the input node concurrent with a first phase of the clock signal. The input stage is configured to activate a first driver circuit of the output stage responsive to a first transition of the input signal. A reverse stage is configured to assert a first inhibit signal at a delay time subsequent to activation of the first driver circuit, which is configured to be deactivated responsive to assertion of the first inhibit signal. Assertion of the first inhibit signal is prevented responsive to a second transition of the input data signal occurring before the delay time has elapsed. | 02-21-2013 |
| 20130082757 | FLIP-FLOP CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A flip-flop circuit (FF | 04-04-2013 |
| 20130147534 | MASTER SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION - In a master-slave D flip-flop, the master latch has first and second three-state stages and a feedback stage for positive feedback from the data outputs of the first and second three-state stages to the data input of the second three-state stage. The slave latch has third and fourth three-state stages and a feedback stage for positive feedback from the data outputs of the third and fourth three-state stages to the data input of the fourth three-state stage. Clock signals are applied from a clock signal source to the clock inputs of a clock switch element in one of the three-state stages whose clock signal is shared with another of the three-state stages, reducing the number of clock switches and clock switch power consumption. Data inverters also may be shared between a three-state stage of the master latch and a three-state stage of the slave latch. | 06-13-2013 |
| 20130154708 | CONFIGURABLE FLIP-FLOP - A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal. | 06-20-2013 |
| 20130314138 | STATE RETENTION SUPPLY VOLTAGE DISTRIBUTION USING CLOCK NETWORK SHIELDING - An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding. | 11-28-2013 |
| 20130335128 | SEQUENTIAL LATCHING DEVICE WITH ELEMENTS TO INCREASE HOLD TIMES ON THE DIAGNOSTIC DATA PATH - A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode. | 12-19-2013 |
| 20130335129 | Current Mode Logic Latch - A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor. | 12-19-2013 |
| 20140002161 | CIRCUIT ARRANGEMENT, A RETENTION FLIP-FLOP, AND METHODS FOR OPERATING A CIRCUIT ARRANGEMENT AND A RETENTION FLIP-FLOP | 01-02-2014 |
| 20140028362 | INPUT CIRCUIT - A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied. | 01-30-2014 |
| 20140077854 | SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN - This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture. | 03-20-2014 |
| 20140125392 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 05-08-2014 |
| 20140145772 | STORAGE CIRCUIT - In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal. | 05-29-2014 |
| 20140167828 | SMALL AREA LOW POWER DATA RETENTION FLOP - Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch. | 06-19-2014 |
| 20140176212 | SCAN FLIP-FLOP, METHOD OF OPERATING THE SAME, AND DEVICE INCLUDING THE SCAN FLIP-FLOP - A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal. | 06-26-2014 |
| 20140218089 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 08-07-2014 |
| 20140232439 | NEGATIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH - In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D | 08-21-2014 |
| 20140253196 | FLIP-FLOPS IN A MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) AND RELATED METHODS - Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch. | 09-11-2014 |
| 20140266364 | SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE SAME - Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses. | 09-18-2014 |
| 20140368246 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock. | 12-18-2014 |
| 20150061740 | SCANNABLE FLOP WITH A SINGLE STORAGE ELEMENT - In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch. | 03-05-2015 |
| 20150061741 | MULTIPLEXER FLOP - In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch. | 03-05-2015 |
| 20150326213 | APPARATUSES AND METHODS FOR TIMING DOMAIN CROSSING - Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback. | 11-12-2015 |
| 20150349756 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock. | 12-03-2015 |
| 20150365082 | TUNABLE CLOCK SYSTEM - A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-fop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented. | 12-17-2015 |
| 20160043706 | LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK - A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system. | 02-11-2016 |
| 20160065180 | SAMPLING CIRCUIT AND MASTER-SLAVE FLIP-FLOP - A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs. | 03-03-2016 |
| 20160072483 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device including: a plurality of function block units each including a plurality of latch circuits; a current prediction unit that predicts a variation amount of current consumed by each of the function block units; an operation control unit that, if any of the variation amounts predicted by the current prediction unit exceeds a threshold value, operates the latch circuits included in a predetermined number of target function block units for a predetermined period, the predetermined number of target function block units being chosen from function block units not operating among the plurality of function block units; and a restore control unit that, after the predetermined period passes, restores information held by the latch circuits included in the predetermined number of target function block units, to information held by the latch circuits before the operation for the predetermined period. | 03-10-2016 |
| 20160072484 | LOW SWING FLIP-FLOP WITH REDUCED LEAKAGE SLAVE LATCH - A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage. | 03-10-2016 |
