| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 327199000 |
Circuit having only two stable states (i.e., bistable)
| 410 |
| 327198000 |
Initializing, resetting, or protecting a steady state condition
| 67 |
| 327187000 |
External effect device (e.g., light, heat, magnetic, or mechanical force sensitive devices, etc.) | 5 |
| 20120218018 | CIRCUIT AND METHOD FOR PROCESSING SIGNALS GENERATED BY A PLURALITY OF SENSORS - An electronic circuit includes a plurality of sensing elements configured to generate a plurality of sensing element signals. The electronic circuit also includes a control signal generator configured to generate a plurality of control signals. The electronic circuit also includes a combining circuit. The combining circuit includes a plurality of switching circuits. Each switching circuit is configured to generate a respective switching circuit output signal being representative of either a non-inverted or an inverted respective one of the plurality of sensing element signals depending upon the first state or the second state of a respective one of the plurality of control signals. The combining circuit also includes a summing circuit coupled to receive the switching circuit output and configured to generate a summed output signal corresponding to a sum of the switching circuit output signals. | 08-30-2012 |
| 20130241614 | TWO LEAD ELECTRONIC SWITCH SYSTEM ADAPTED TO REPLACE A MECHANICAL SWITCH SYSTEM - Systems and methods for a two lead electronic switch adapted to replace a mechanical switch are provided. In one embodiment, a method comprises, in an electronic switch having a sensor, an electronic circuit, a first terminal and a second terminal, receiving, by the electronic circuit, from the sensor, a sensed voltage proportional to an amount sensed by the sensor; operating the electronic circuit in a first state when the sensed voltage is greater than or equal to a threshold voltage associated with a threshold pressure sensed by the sensor; operating the electronic circuit in a second state when the sensed voltage is less than the threshold voltage associated with the threshold pressure sensed by the sensor; receiving, across the first terminal and the second terminal, an input voltage used to provide power for the electronic switch; and wherein the first terminal and the second terminal are also used to couple the electronic switch to a device. | 09-19-2013 |
| 20150145575 | SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS - Aspects described herein are related to spintronic logic gates employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a spintronic logic gate is disclosed that includes a charge current generation circuit and a GSHE MTJ element. The charge current generation circuit is configured to generate a charge current representing an input bit set. The input bit set may include one or more input bit states for a logical operation. The GSHE MTJ element is configured to set a logical output bit state for the logical operation, and has a threshold current level. The GSHE MTJ element is configured to generate a GSHE spin current in response to the charge current and perform the logical operation on the input bit set by setting the logical output bit state based on whether the GSHE spin current exceeds the threshold current level. | 05-28-2015 |
| 20150145576 | SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS - Aspects described herein are related to pipeline circuits employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a pipeline circuit is disclosed. The pipeline circuit includes a first pipeline stage and a second pipeline stage. The first pipeline stage is configured to store a first bit set and to generate a first charge current representing the first bit set. The second pipeline stage includes a first GSHE MTJ element. The first GSHE MTJ element is configured to set a first bit state for the first logical operation, and has a first threshold current level. The first GSHE MTJ element is configured to generate a first GSHE spin current in response to the first charge current. In this manner, the first GSHE MTJ element is also configured to perform the first logical operation on the first bit set. | 05-28-2015 |
| 20150311309 | Ferroelectric Devices including a Layer having Two or More Stable Configurations - Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile). | 10-29-2015 |
| 327197000 |
Convertible circuit (e.g., bistable to monostable, D-type to T-type, etc.) | 3 |
| 20130106481 | RECONFIGURABLE MULTIVIBRATOR ELEMENT BASED ON CHAOS CONTROL | 05-02-2013 |
| 20140062560 | RECONFIGURABLE FLIP-FLOP | 03-06-2014 |
| 20150091625 | HIGH SPEED, LOW POWER, ISOLATED BUFFER - Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal. | 04-02-2015 |
| 327194000 |
Zener or capacitive diode | 2 |
| 20120154007 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE - A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor. | 06-21-2012 |
| 20130207704 | CIRCUIT AND METHOD FOR IMPROVING NOISE IMMUNITY OF A SINGLE-END LEVEL SHIFTER IN A FLOATING GATE DRIVER - A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity. | 08-15-2013 |
| 327227000 |
Monostable | 1 |
| 20110018602 | EDGE-SENSITIVE FEEDBACK-CONTROLLED PULSE GENERATOR - Edge-sensitive Feedback-controlled pulse generator. A circuit includes a pulse generating circuit responsive to a desired transition in an input signal to initiate an output pulse. The circuit also includes a delay circuit responsive to the output pulse to generate a feedback signal. Further, the circuit includes a first latch that renders the pulse generating circuit unresponsive to any change in the input signal until the feedback signal has been generated, a switch responsive to the feedback signal to complete the output pulse, a second latch responsive to a change in the input signal after the feedback signal has been generated to render the pulse generating circuit responsive to a subsequent occurrence of the desired transition in the input signal to initiate the output pulse again, and a third latch responsive to the change in the input signal after the feedback signal has been generated. | 01-27-2011 |
| 327192000 |
Negative resistance transistor (e.g., unijunction, etc.) | 1 |
| 20130106480 | METAL-INSULATOR TRANSITION LATCH | 05-02-2013 |
| Entries |
| Document | Title | Date |
|---|
| 20100289549 | ANALOG SCAN CIRCUIT, ANALOG FLIP-FLOP, AND DATA PROCESSING APPARATUS - Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN | 11-18-2010 |
| 20110133803 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 06-09-2011 |
| 20130120045 | CENTRALIZED POWER GATING CONTROL FOR PARTITIONED POWER GATES - Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC. | 05-16-2013 |
| 20130154706 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 06-20-2013 |
