| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326095000 | Field-effect transistor | 43 |
| 20080204081 | Clock gated circuit - A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time. | 08-28-2008 |
| 20090108874 | Limited Switch Dynamic Logic Cell Based Register - A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal. | 04-30-2009 |
| 20090108875 | Structure for a Limited Switch Dynamic Logic Cell Based Register - A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal. | 04-30-2009 |
| 20090267649 | Clock Gating System and Method - A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal. | 10-29-2009 |
| 20100156466 | Implementing Power Savings in HSS Clock-Gating Circuit - A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the C2 clocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a C2 clock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the C2 clocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation. | 06-24-2010 |
| 20110018584 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal. | 01-27-2011 |
| 20110169528 | CLOCK BUFFER CIRCUIT - A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. The leakage current prevention circuit includes a first PMOS transistor, which is connected between the source of a PMOS transistor of the first CMOS transistor and a power supply line, and a second PMOS transistor, which is connected between the source of a PMOS transistor of the second CMOS transistor and the power supply line. The first and second PMOS transistors are deactivated in response to an enable signal generated when a circuit block does not require the clock signal. The first and the second PMOS transistors have predefined widths and lengths such that the addition of these transistors in series with the CMOS transistors does not increase the propagation delay of the clock buffer circuit. Deactivating the first and second PMOS transistors disconnects the CMOS transistors from the power supply line, which prevents current leakage. | 07-14-2011 |
| 20110215837 | CLOCK GENERATOR CIRCUITS FOR GENERATING CLOCK SIGNALS - The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V | 09-08-2011 |
| 20120119784 | DIGITAL LOGIC CIRCUIT WITH DYNAMIC LOGIC GATE - A digital logic gate suitable for a high-speed operation of a central processing unit. The digital logic gate comprises the first dynamic logic gate configured to logically gate a plurality of first input data in response to the first clock signal, a second dynamic logic gate configured to logically gate a gating output of the first dynamic logic gate and a plurality of second input data, and a latching device configured to latch a gating output of the second dynamic logic gate. The digital logic circuit need not adopt a keeper circuit, and thus a gate delay is reduced and the digital logic circuit performs a high-speed gating operation with robust characteristic against a current leakage or an input noise. | 05-17-2012 |
| 20120249181 | LATCH CIRCUIT AND CLOCK CONTROL CIRCUIT - A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit. | 10-04-2012 |
| 20130307585 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal. | 11-21-2013 |
| 20140292371 | MULTI-THRESHOLD DUAL-SPACER DUAL-RAIL DELAY-INSENSITIVE LOGIC (MTD3L) CIRCUIT DESIGN - A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD | 10-02-2014 |
| 20140292372 | LOW POWER CLOCK GATING CIRCUIT - A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate. | 10-02-2014 |
| 20150084673 | MARGIN IMPROVEMENT FOR CONFIGURABLE LOCAL CLOCK BUFFER - A timing margin circuit of a local clock buffer circuit may include an inverter logic gate having an inverter input and an inverter output, whereby the inverter input receives an input clock signal. A NAND logic gate includes a first NAND input coupled to the inverter output, a second NAND input, and a NAND output. The circuit also includes a logic device having a first logic device input that is coupled to the inverter output, a second logic device input that receives a mode selection signal, and a logic device output that couples to the second NAND input, whereby the NAND logic gate generates a first time delayed input clock signal and a second time delayed input clock signal, such that the first and the second time delayed input clock signal control a falling edge transition of a local clock signal derived from the input clock signal. | 03-26-2015 |
| 20150097595 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 | 04-09-2015 |
| 326096000 | Two or more clocks (e.g., phase clocking, etc.) | 10 |
| 20090256593 | PROGRAMMABLE SAMPLE CLOCK FOR EMPIRICAL SETUP TIME SELECTION - A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon. | 10-15-2009 |
| 20100060321 | Clock control of state storage circuitry - State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry | 03-11-2010 |
| 20100109708 | LOGIC CIRCUIT - An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor | 05-06-2010 |
| 20100156467 | CONTROL SYSTEM FOR DIFFERENT COLORS OF LIGHT EMITTING DIODES - A control system includes a clock unit for providing a first clock signal, and a second clock signal having a frequency lower than that of the first clock signal. Three control units are coupled respectively to three light emitting diodes (LED) emitting respectively three different colors. Each control unit is operable based on the clock signals and a corresponding set of first and second reference values to output a driving pulse signal to a corresponding LED such that the corresponding LED is driven by the driving pulse signal to emit light during a corresponding one of first, second and third time periods of a control cycle of the control system. | 06-24-2010 |
| 20110156754 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing. | 06-30-2011 |
| 20130038350 | SINGLE-TO-DIFFERENTIAL CONVERSION CIRCUIT AND METHOD - A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node. | 02-14-2013 |
| 326097000 | MOSFET | 4 |
| 20080238484 | LOCAL CLOCK BUFFER (LCB) WITH ASYMMETRIC INDUCTIVE PEAKING - A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (V | 10-02-2008 |
| 20110260754 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area. | 10-27-2011 |
| 20130234759 | CLOCK-DELAYED DOMINO LOGIC CIRCUIT - A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node. | 09-12-2013 |
| 20140292373 | TERNARY T ARITHMETIC CIRCUIT - A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a fifth NMOS. The logic 2 gate circuit includes: a fourth PMOS, a fifth PMOS, a sixth NMOS, a seventh NMOS, and an eighth NMOS. The logic 1 gate circuit includes: a sixth PMOS, a seventh PMOS, a ninth NMOS, a tenth NMOS, an eleventh NMOS, and a twelfth NMOS. | 10-02-2014 |
| 326098000 | MOSFET | 18 |
| 20080238485 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell. | 10-02-2008 |
| 20080258771 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate. | 10-23-2008 |
| 20080258772 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location. | 10-23-2008 |
| 20090167358 | FULLY INTERRUPTIBLE DOMINO LATCH - A domino latch is provided that comprises a forward path circuit and a feedback path circuit. The feedback path includes a plurality of keeper transistors, an inverter, and at least one interrupt transistor to cut off the feedback path circuit and prevent signal contention on the output node between the feedback path circuit and the forward path circuit. | 07-02-2009 |
| 20090206881 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate. | 08-20-2009 |
| 20090230994 | DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT - A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed. | 09-17-2009 |
| 20100073029 | Complementary Energy Path Adiabatic Logic - A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode. | 03-25-2010 |
| 20100073030 | Adaptive Keeper Circuit to Control Domino Logic Dynamic Circuits Using Rate Sensing Technique - The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M | 03-25-2010 |
| 20100315126 | DYNAMIC CIRCUIT WITH SLOW MUX INPUT - A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signal and to output a pulse signal, and a multiplexing logic circuit to receive the selection signal and the pulse signal from the control circuit, to receive at least one second, static input signal, and to output a signal corresponding to one of the first input signal and the second, static input signal based on the state of the selection signal. | 12-16-2010 |
| 20110032000 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. | 02-10-2011 |
| 20110102018 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x10 | 05-05-2011 |
| 20120139584 | DOMINO LOGIC CIRCUITS AND PIPELINED DOMINO LOGIC CIRCUITS - A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node. | 06-07-2012 |
| 20120299622 | Internal Clock Gating Apparatus - An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively. | 11-29-2012 |
| 20130147518 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10 | 06-13-2013 |
| 20130257480 | CLOCK-DELAYED DOMINO LOGIC CIRCUIT AND DEVICES INCLUDING THE SAME - A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal. | 10-03-2013 |
| 20140070847 | CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT EMPLOYING THE SAME - A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit. | 03-13-2014 |
| 20140292374 | METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT - A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently. | 10-02-2014 |
| 20150070050 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages. | 03-12-2015 |
