| Entries |
| Document | Title | Date |
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| 20080204080 | Mobile circuit robust against input voltage change - An inverting flip-flop (F/F) circuit type monostable-bistable transition logic element (MOBILE) circuit that uses resonant tunneling diodes (RTDs) and can prevent a malfunction caused by low peak-to-valley current ratio (PVCR) characteristics of the RTD includes an input data conversion circuit and an inverting F/F circuit. The input data conversion circuit receives input data and converts a logic level of the input data according to a logic level of output data of the MOBILE circuit. The inverting F/F circuit inverts a logic level of data output from the input data conversion circuit and outputs the output data. Accordingly, even when a logic level of input data changes from LOW to HIGH, the logic level of output data can be maintained HIGH in the inverting F/F type MOBILE circuit constructed using silicon semiconductor based RTDs with a small PVCR. Therefore, it is possible to enhance the performance of the inverting F/F circuit type MOBILE circuit. | 08-28-2008 |
| 20080211543 | 4-Level Logic Decoder - The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding circuit comprising comparison circuitries for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit, which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL. | 09-04-2008 |
| 20080224734 | Multi-terminal chalcogenide logic circuits - Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith. | 09-18-2008 |
| 20080238483 | Reduced-Delay Clocked Logic - Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle. | 10-02-2008 |
| 20080272807 | Thin film logic device and system - Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices do, in a manner that does not provide a direct conduction path between a system supply and a system return. Complementary logic circuits may employ three-terminal threshold switches as switching elements. | 11-06-2008 |
| 20080284469 | REDUCED POWER CONSUMPTION LIMITED-SWITCH DYNAMIC LOGIC (LSDL) CIRCUIT - An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers. | 11-20-2008 |
| 20080303552 | Clock Distribution Network Architecture for Resonant-Clocked Systems - Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry. | 12-11-2008 |
| 20080309373 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes a clock signal supply control circuit that controls a timing when a master clock signal output from an oscillation circuit is supplied to an internal circuit of the integrated circuit device. The clock signal supply control circuit stops supplying the master clock signal to an internal circuit until a count circuit counts clock pulses of the master clock signal up to a predetermined number. The count circuit performs the count operation asynchronously with the master clock signal. The integrated circuit device may include a divided clock signal supply circuit that supplies a divided clock signal obtained by dividing the frequency of a clock signal output from the clock signal supply control circuit to the internal circuit. A clock signal divider circuit generates the divided clock signal asynchronously with the master clock signal. | 12-18-2008 |
| 20080315919 | LOGIC STATE CATCHING CIRCUITS - A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element. | 12-25-2008 |
| 20090002032 | DATA SYNCHRONIZER - A data synchronizer is to avoid the pulse width constraint on the data while synchronizing the data between two devices operating at different clock rates. The data synchronizer may comprise one or more storage units such as the flip-flops and a clock gating logic associated with each storage unit. The clock gating logic may generate a control signal which may either allow or stall the clock reaching the storage units. The control signal may be generated by comparing the input and the output to the storage units. | 01-01-2009 |
| 20090015294 | LEAKAGE DEPENDENT ONLINE PROCESS VARIATION TOLERANT TECHNIQUE FOR INTERNAL STATIC STORAGE NODE - A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to compensate for a wide range of leakage corners where the internal storage is located. The adaptive keeper circuit not only increases the robustness of the storage node against leakage caused by process variation but also improves the overall performance of the static storage device connected to the node. | 01-15-2009 |
| 20090027085 | RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS - A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs). | 01-29-2009 |
| 20090045847 | GENERIC FLEXIBLE TIMER DESIGN - One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits. | 02-19-2009 |
| 20090066369 | CLOCK GUIDED LOGIC WITH REDUCED SWITCHING - Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path. | 03-12-2009 |
| 20090108873 | Quantum-dot cellular automata methods and devices - A Quantum-dot Cellular Automata (QCA) device having normal QCA cells laid out in a planar structure such that there are a set of input lines, that may be columns, and a set of orthogonal, output lines, that may be rows. The device has clocking regions that control the flow of binary signals through the device. The input columns are driven by a separate input signal, and all the cells of each column align to match their input signal. These input columns then serve as drivers for output rows that act as serial shift registers under the control of clock signals applied to sub-sections of the rows. In this way, a copy of the contents of each of the input signals propagates along each of the output rows to an output cell. The output cells of each output row may be assigned their own, latching clock signal. | 04-30-2009 |
| 20090121744 | Glitch Free 2-Way Clock Switch - The present invention switches between a first clock signal (CLK | 05-14-2009 |
| 20090134912 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 05-28-2009 |
| 20090153194 | CLOCK CIRCUITRY - A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal. | 06-18-2009 |
| 20090189641 | INTEGRATED CIRCUIT DEVICE AND LAYOUT DESIGN METHOD THEREFOR - An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree structure and that distributes a common signal that is input to the starting point of said tree structure to each of the multiple first circuit elements through the same number of levels of drive circuits. At least some of the drive circuits of the tree structure are arranged one each in each of multiple second areas into which the first area is divided to include approximately the same number of the first circuit elements, and the common signal is supplied to the first circuit elements included in the second area where they are arranged. | 07-30-2009 |
| 20090206880 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S | 08-20-2009 |
| 20090243657 | METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE - Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time. | 10-01-2009 |
| 20090302892 | Method and Apparatus for Selecting an Operating Mode Based on a Determination of the Availability of Internal Clock Signals - A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 12-10-2009 |
| 20100001762 | DOMAIN CROSSING CIRCUIT AND METHOD - A domain crossing circuit for reducing current consumption includes an internal counter to count an internal clock in response to the release of a reset signal, outputting an internal code, a replica delay unit to delay the reset signal as much as a timing difference between the internal clock and an external clock, outputting a delayed reset signal, an external counter to count the external clock in response to the release of the delayed reset signal outputted from the replica delay unit, outputting an external code, and an internal signal generation unit to convert an external signal to an internal signal using the internal code and the external code. | 01-07-2010 |
| 20100026345 | CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER - An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains. | 02-04-2010 |
| 20100045344 | DUAL RAIL DOMINO CIRCUIT, DOMINO CIRCUIT, AND LOGIC CIRCUIT - In a dual rail domino circuit | 02-25-2010 |
| 20100079168 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD - A semiconductor integrated circuit has a scan chain with a scan clock signal line for clocking scan flip-flops and a scan test signal line for transferring scanning data into and out of the scan flip-flops. Part of the scan test signal line is routed adjacently parallel to the scan clock signal line to shield the scan clock signal line from electrical noise during normal operation, when the scan test signal line is held at a fixed potential. Separate shield lines are used to shield parts of the scan clock signal line not shielded by the scan test signal line. Use of a combination of shield lines and the scan test signal line to shield the scan clock signal line saves space and conserves routing resources. | 04-01-2010 |
| 20100109707 | LOW POWER, SELF-GATED, PULSE TRIGGERED CLOCK GATING CELL - A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell. | 05-06-2010 |
| 20100117683 | HARDWARE SYNTHESIS FROM MULTICYCLE RULES - Enabling scheduling of single cycle as well as scheduling multi-cycle rules in a synchronous digital system whose behavior is governed by an asynchronous system specification (e.g., a TRS) provides a way to allow complex actions at state transitions of the asynchronous system without requiring that the complex actions be synthesized in logic that must be performed in a single clock cycle. For example, a relatively infrequent action may include a critical timing path that determines the maximum clock frequency of the system. By allowing that infrequent action to take multiple clock cycles, even if that action takes more absolute time, other actions may take less absolute time by virtue of being able to operate the synchronous system at a higher clock rate. The overall system may then operate more quickly (e.g., as measured by the average number of rules applied per unit of absolute time). | 05-13-2010 |
| 20100123480 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND APPARATUS FOR DESIGNING SAME - A semiconductor device that includes multiple logic circuit cells having respective logic circuits formed therein and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects. | 05-20-2010 |
| 20100134148 | Detecting transitions in circuits during periodic detection windows - Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal. | 06-03-2010 |
| 20100156465 | APPARATUS AND METHOD FOR USE WITH QUADRATURE SIGNALS - Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals. | 06-24-2010 |
| 20100182045 | LOW-JITTER HIGH-FREQUENCY CLOCK CHANNEL - According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters. | 07-22-2010 |
| 20100182046 | SEMICONDUCTOR DEVICE - The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit. | 07-22-2010 |
| 20100194434 | SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING - Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit. | 08-05-2010 |
| 20100194435 | CLOCK GUIDED LOGIC WITH REDUCED SWITCHING - Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path. | 08-05-2010 |
| 20100207662 | Semiconductor integrated circuit - An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target. | 08-19-2010 |
| 20100213981 | DOMINO LOGIC BLOCK HAVING DATA HOLDING FUNCTION AND DOMINO LOGIC INCLUDING THE DOMINO LOGIC BLOCK - The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to an enable signal and a clock signal. The feedback signal is an output signal of a previous cycle of a clock signal. When an enable signal is a first level, the domino logic maintains an output signal of a previous cycle instead of an input signal. According to the present general inventive concept, the domino logic having a data hold function can be embodied. | 08-26-2010 |
| 20100213982 | METHOD AND SYSTEM FOR DISTRIBUTING CLOCK SIGNALS ON NON MANHATTAN SEMICONDUCTOR INTEGRATED CIRCUITS - The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network. | 08-26-2010 |
| 20100225353 | METHODS AND SYSTEMS FOR REDUCING CLOCK SKEW IN A GATED CLOCK TREE - Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements. | 09-09-2010 |
| 20100244901 | CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - A clock switching circuit includes: a selector that selects one of a plurality of clocks based on a select signal and outputs the clock selected as a selected clock; a mask circuit that masks the selected clock based on a mask signal and outputs the selected clock masked as an output clock; and a mask signal generation circuit that generates the mask signal and the select signal, the mask signal generation circuit switches a signal level of the select signal after causing the mask signal to be active, and causes the mask signal to be inactive on condition that a change is detected in the signal level of the selected clock after the signal level of the select signal has been switched. | 09-30-2010 |
| 20100289528 | POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS - In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein. | 11-18-2010 |
| 20100295578 | Clock Tree Distributing Method - A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-dimensional interface arrangement to a one-dimensional interface arrangement according to the conversion rate, forming a one-dimensional clock tree according to the one-dimensional interface arrangement, generating the clock tree corresponding to the two-dimensional interface arrangement by converting the one-dimensional clock tree according to the conversion rate | 11-25-2010 |
| 20100315125 | DYNAMIC DOMINO CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A dynamic domino circuit includes a clock generator and a domino circuit. The clock generator generates a pulse signal and a plurality of internal clock signals based on a global clock signal. Phases of the plurality of internal clock signals are sequentially delayed. The domino circuit sequentially performs a plurality of logic operations based on a plurality of input signals, the pulse signal and the plurality of internal clock signals and generates an output signal in synchronization with the pulse signal. The dynamic domino circuit may provide an effective interface with static logics. | 12-16-2010 |
| 20100321065 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INSULATED GATE FIELD EFFECT TRANSISTORS - A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state. | 12-23-2010 |
| 20100321066 | DIGITAL NOISE FILTER - A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal. | 12-23-2010 |
| 20110001514 | COMMAND CONTROL CIRCUIT FOR SEMICONDUCTOR INTEGRATED DEVICE - A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches. | 01-06-2011 |
| 20110025377 | Circuit Arrangement and Method for Evaluating a Data Signal - A circuit arrangement ( | 02-03-2011 |
| 20110043251 | Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs - An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive. | 02-24-2011 |
| 20110062991 | ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS - A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output. | 03-17-2011 |
| 20110089974 | ROBUST TIME BORROWING PULSE LATCHES - Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths. | 04-21-2011 |
| 20110115524 | Logic Cell Having Reduced Spurious Toggling - A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state. | 05-19-2011 |
| 20110210761 | Resonant Clock And Interconnect Architecture For Digital Devices With Multiple Clock Networks - A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs). | 09-01-2011 |
| 20110221473 | SOFT ERROR DETECTION FOR LATCHES - A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and to the observing circuit. For the latch, the clocking defines a window in time during which the latch is prevented from receiving data, and in a synchronized manner the clocking is enabling a response in the observing circuit. The clocking is synchronized in such a manner that the circuit is enabled for its response only inside the window when the latch is prevented from receiving data. The system may also have additional circuits that are respectively coupled to latches, with each the additional circuit and its respective latch receiving the synchronized clocking Responses of a plurality of circuits may be coupled in a configuration corresponding to a logical OR. | 09-15-2011 |
| 20110291703 | Method and Apparatus to Sterialize Parallel Data Input Values - A method and apparatus to serialize parallel data input values is disclosed. In a particular embodiment, a method of serializing parallel data input values includes receiving multiple data input values in parallel at an input tier of a selection circuit, where the input tier includes multiple combinatorial gate multiplexers. The method further includes selecting an output value at an output tier of the selection circuit, where the output tier includes at least one combinatorial gate multiplexer. | 12-01-2011 |
| 20110298495 | ONE PHASE LOGIC - Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. | 12-08-2011 |
| 20120032703 | PULSE-SHRINKING DELAY LINE BASED ON FEED FORWARD - A shrinking-pulse digital delay line ( | 02-09-2012 |
| 20120068736 | DESIGN APPARATUS, DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A design apparatus according to the present embodiment includes a scheduling section, a group ID assigning section, a transition violation detecting section and a state inserting section. The scheduling section generates a plurality of states that transition based on a clock according to a control data flow graph generated from a behavioral description and common resource schedule information. The group ID assigning section assigns group IDs to the plurality of states under a predetermined condition. The transition violation detecting section detects whether or not there is any transition violation among the plurality of states to which the group IDs are assigned. The state inserting section adds, when a transition violation is detected by the transition violation detecting section, a new state between states from which the transition violation has been detected. | 03-22-2012 |
| 20120112791 | ROBUST TIME BORROWING PULSE LATCHES - Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths. | 05-10-2012 |
| 20120112792 | ONE PHASE LOGIC - Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed. | 05-10-2012 |
| 20120169373 | GLITCH FREE CLOCK SWITCHING CIRCUIT - A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output. | 07-05-2012 |
| 20120176157 | Clock-Tree Transformation in High-Speed ASIC Implementation - A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs. | 07-12-2012 |
| 20120223741 | POWER REDUCING LOGIC AND NON-DESTRUCTIVE LATCH CIRCUITS AND APPLICATIONS - In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein. | 09-06-2012 |
| 20120223742 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A DIGITAL CIRCUIT BY CONTROLLING THE CLOCK - A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use. | 09-06-2012 |
| 20120268168 | CLOCK GATING CELL CIRCUIT - A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output. | 10-25-2012 |
| 20120280714 | CLOCK SYNCHRONIZATION - In an example embodiment, a method for synchronizing clocks between a plurality of clocked devices where one of the plurality of clocked devices is not directly synchronized with another of the plurality of clocked devices. Clock offset and a clock drift between a first clock associated with a first device and a second clock associated with a second is directly determined based on signals exchanged between the first and second devices. Clock offset and clock drift between the second clock and a third clock associated with a third device is directly determined based on signals exchanged between the second and third devices. A clock offset and clock drift between the first clock and third clock is determined based on a difference between the clock offset and drift between the first and second clocks and the clock offset and drift between the second and third clocks. | 11-08-2012 |
| 20120286824 | Supplying a clock signal and a gated clock signal to synchronous elements - A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The clock gating circuitry unit receives a clock signal, a clock enable signal having either an enable value indicating the plurality of synchronous elements to are currently functional and are to be clocked, or a disable value indicating the plurality of synchronous elements are currently not required and are not to be clocked, and a power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down, or a functional mode value indicating the plurality of synchronous elements are to be powered. The clock gating unit has logic circuitry that is configured in response to the clock enable signal having the enable value and to the low power mode signal having the functional mode value to output the clock signal and in response to at least one of the clock enable signal having the disable value and the low power mode signal having the low power value to output the predetermined gated value. | 11-15-2012 |
| 20120293205 | INTEGRATED CIRCUIT DEVICE AND METHOD OF USING COMBINATORIAL LOGIC IN A DATA PROCESSING CIRCUIT - An integrated circuit device comprising one or more data processing circuits is provided, where each data processing circuit has an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and a second set of data signals and provides the first set of data signals to an input of the combinatorial logic stage during a first portion of a period of the clock signal, and provides the second set of data signals to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the combinatorial logic stage at least a first result signal as a function of the first set of data signals during a first portion of a subsequent period of the clock signal and receive from the output at least a second result signal as a function of the second set of data signals during a second portion of the subsequent period. | 11-22-2012 |
| 20120319731 | INTEGRATED CIRCUIT DEVICE COMPRISING CLOCK GATING CIRCUITRY, ELECTRONIC DEVICE AND METHOD FOR DYNAMICALLY CONFIGURING CLOCK GATING - An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled. | 12-20-2012 |
| 20130021064 | PREVENTING A-B-A RACE IN A LATCH-BASED DEVICE - A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled. | 01-24-2013 |
| 20130038349 | TIME-TO DIGITAL CONVERTER AND DIGITAL-CONTROLLED CLOCK GENERATOR AND ALL-DIGITAL CLOCK GENERATOR - An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier. | 02-14-2013 |
| 20130043904 | INTEGRATED CIRCUIT DEVICE, SYNCHRONISATION MODULE, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device includes at least a functional module arranged to receive a reference clock signal; a gating component configurable to perform gating of the reference clock signal; and a synchronisation module. The synchronisation module includes a trigger component arranged to receive a request for the functional module, the request being asynchronous with the reference clock signal, and to set an enable signal for the functional module in response to receiving the request therefor; and a synchronisation component arranged to receive the enable signal, and in response to the enable signal being set to: configure the gating component to un-gate the reference clock signal; and synchronize an initial clock cycle of the reference clock signal received by the functional module following the reference clock signal being un-gated. | 02-21-2013 |
| 20130043905 | GLITCH FREE CLOCK SWITCHING CIRCUIT - A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output. | 02-21-2013 |
| 20130076396 | METHOD, SYSTEM AND DEVICE FOR REMOVING MEDIA ACCESS CONTROL ADDRESSES - Embodiments of the present invention disclose a method and device for selecting a sampling clock signal. The method includes: obtaining, by a logic chip, a data edge of a data signal and a clock edge of a clock signal, selecting a sampling edge according to the data edge and the clock edge, and sending a selecting signal corresponding to the sampling edge to a selector; and selecting, by the selector, a sampling clock signal according to the selecting signal. The technical solutions provided by the embodiments of the present invention can solve problems of poor system maintainability and high cost of operation and maintenance because a receiver device needs to select a sampling clock signal through manual configuration in the synchronous serial-port communication in the prior art. | 03-28-2013 |
| 20130082738 | DOUBLE DATA RATE CLOCK GATING - Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking. | 04-04-2013 |
| 20130106464 | Integrated Circuit Including Pulse Control Logic Having Shared Gating Control | 05-02-2013 |
| 20130120024 | WAVE DYNAMIC DIFFERENTIAL LOGIC - Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a WDDL stage, etc. In one embodiment, a Divided Wave Dynamic Differential Logic (DWDDL) is provided wherein a WDDL circuit is conveniently implemented as dual logic trees. | 05-16-2013 |
| 20130141138 | SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING - Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit. | 06-06-2013 |
| 20130162295 | CLOCK GENERATOR INTERMITTENTLY GENERATING SYNCHRONOUS CLOCK - A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal. | 06-27-2013 |
| 20130169313 | HIGH-SPEED FREQUENCY DIVIDER ARCHITECTURE - A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-back circuit is clocked on a rising clock edge of an input clock signal, while the second shift register loop-back signal is clocked on a negative edge of the input clock signal. The outputs of the first and second loop-back shift registers are ORed to provide a 50% duty cycle output clock signal. | 07-04-2013 |
| 20130176055 | Clock-Tree Transformation in High-Speed ASIC Implementation - A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs. | 07-11-2013 |
| 20130181742 | METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES - A method includes applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple selection elements. The tree structure includes a data input tier and a data output tier. | 07-18-2013 |
| 20130214816 | SINGLE CLOCK DISTRIBUTION NETWORK FOR MULTI-PHASE CLOCK INTEGRATED CIRCUITS - A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level. | 08-22-2013 |
| 20130241597 | INTEGRATED CIRCUIT WITH TIMING AWARE CLOCK-TREE AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT - An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements. | 09-19-2013 |
| 20130249596 | INACTIVITY TRIGGERED SELF CLOCKING LOGIC FAMILY - Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure. | 09-26-2013 |
| 20130257479 | PREVENTING A-B-A RACE IN A LATCH-BASED DEVICE - A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled. | 10-03-2013 |
| 20130314126 | Non-Overlapping Clock Generator Circuit and Method - A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals. | 11-28-2013 |
| 20130328592 | TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC - A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal. | 12-12-2013 |
| 20130328593 | TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC - A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal. | 12-12-2013 |
| 20140002136 | On-Chip Probe Circuit for Detecting Faults in an FPGA | 01-02-2014 |
| 20140015567 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A DIGITAL CIRCUIT BY CONTROLLING THE CLOCK - A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use. | 01-16-2014 |
| 20140049288 | HUM GENERATION CIRCUITRY - Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised of a plurality of null convention logic (NCL) gates organized into rings. Each ring shares at least one NCL gate with an adjacent ring. The rings are configured in such a way that each ring in the mesh operates synchronously with the other rings in the mesh. | 02-20-2014 |
| 20140049289 | TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC - A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal. | 02-20-2014 |
| 20140125381 | VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION - An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions. | 05-08-2014 |
| 20140132305 | CLOCK NETWORK ARCHITECTURE - An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional. | 05-15-2014 |
| 20140152344 | IN SITU PULSE-BASED DELAY VARIATION MONITOR PREDICTING TIMING ERROR CAUSED BY PROCESS AND ENVIRONMENTAL VARIATION - An in situ pulse-based delay variation monitor that predicts timing errors caused by process and environmental variations is revealed. The monitor includes a sequential storage device having a mater storage device and a slave storage device, a transition detector that is electrically connected to a node set on an electrical connection pathway from a master storage device to the slave storage device, and a warning signal generator electrically connected to the transition detector. The transition detector receives output of the master storage device to form a warning area by delay buffer, and generates a pulse width output correspondingly according to transition of the data input. Thus the warning signal generator generates a warning signal according to logic action at the pulse width and the clock input when the data input reaches the warning area. Thereby timing errors caused by static process variations and dynamic environmental variations are predicted. | 06-05-2014 |
| 20140176190 | COARSE GATING OF CLOCK TREE ELEMENTS - Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a dock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit. | 06-26-2014 |
| 20140184271 | LOW CLOCK-POWER INTEGRATED CLOCK GATING CELL - In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the enable signal. The latch includes a tri-state inverter. A NAND gate is coupled to the latch and the NAND gate is configured to generate an inverted clock signal in response to the latch output and a clock input. | 07-03-2014 |
| 20140203841 | Systems And Methods For Reduced Coupling Between Digital Signal Lines - Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations. | 07-24-2014 |
| 20140210518 | Resonant Inductor Coupling Clock Distribution - The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal. | 07-31-2014 |
| 20140232431 | Clock Gater with Independently Programmable Delay - An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit. | 08-21-2014 |
| 20140253175 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC TWO-PHASE CLOCKING - A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches. | 09-11-2014 |
| 20140266303 | PIPELINING OF CLOCK GUIDED LOGIC USING LATCHES - This application discloses the technique to pipeline the Clock Guided Logic. Latch based storage elements are used in CGL based design such that when first stage CGL elements are in precharge phase the second stage CGL elements are in evaluate phase and vice-versa resulting into higher design throughput. | 09-18-2014 |
| 20140292370 | SYNCHRONOUS INPUT SIGNAL CAPTURE SYSTEM - A synchronous digital signal capture system includes a first flip-flop and a synchronization module. The first flip-flop receives a logic control signal and a first clock signal having a first frequency. The first flip-flop is configured to output a synchronized data signal based on the logic control, and generate a synchronous reset signal that is a logic inverse of the synchronized data signal generated at the data output. The synchronization module receives a primary data signal and is configured to generate the logic control signal based on the primary input signal, a second clock signal, and the synchronous reset signal such that the first flip-flop generates the synchronized signal. | 10-02-2014 |
| 20140306735 | FLIP-FLOP WITH REDUCED RETENTION VOLTAGE - A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage. | 10-16-2014 |
| 20140306736 | STATE MACHINE CIRCUIT AND STATE ADJUSTING METHOD - A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal. | 10-16-2014 |
| 20140320170 | GLITCH FREE CLOCK MULTIPLEXER - Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior. | 10-30-2014 |
| 20150042382 | POWER DISTRIBUTION IN SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes a clock signal distribution network and a logic circuitry. The clock signal distribution network is configured to receive a first power. The logic circuitry is configured to receive a second power independent from the first power. | 02-12-2015 |
| 20150048864 | LOW CONSUMPTION LOGIC CIRCUIT WITH MECHANICAL SWITCHES - Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronisation input (Phi), with this circuit comprising:
| 02-19-2015 |
| 20150070049 | APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS - This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit. | 03-12-2015 |
| 20150295579 | System Reset Controller Replacing Individual Asynchronous Resets - An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses. | 10-15-2015 |
| 20150318857 | SYNCHRONISED LOGIC CIRCUIT - Consistent with an example embodiment, the disclosed includes a synchronised logic circuit comprising: an input module; an output module; a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules; a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation of the input and output modules; and an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit. | 11-05-2015 |
| 20150341032 | LOCALLY ASYNCHRONOUS LOGIC CIRCUIT AND METHOD THEREFOR - A locally asynchronous logic circuit includes an input latch; a synchronous-to-asynchronous control circuit having an input for receiving a first clock signal, a first output coupled to the latch enable input of the input latch, and a second output for providing a start signal; a predetermined number of stages coupled between the output of the input latch and an output of the locally asynchronous logic circuit, each stage having an asynchronous functional circuit and an associated completion circuit having an input for receiving a corresponding start signal and an output for providing a corresponding done signal; and an asynchronous-to-synchronous control circuit having a first input for receiving a done signal of a preceding stage, and an output for providing a valid signal. The asynchronous-to-synchronous control circuit activates said first valid signal to indicate said output of the locally asynchronous logic circuit is valid. | 11-26-2015 |
| 20150341033 | APPARATUS AND METHODS FOR LEAKAGE CURRENT REDUCTION IN INTEGRATED CIRCUITS - This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit. | 11-26-2015 |
| 20160049934 | ONE-SHOT CIRCUIT - A one-shot circuit that includes a fixed-voltage generating module, a clock-shifting module and a logic operation module is provided. The fixed-voltage generating module is operated according to a system voltage to generate a fixed voltage smaller than the system voltage and not varied accordingly. The clock-shifting module includes a delay circuit and at least one first inverter. The delay circuit receives and delays a clock signal to generate a first delayed clock signal. The first inverter is electrically connected to the delay circuit to be operated according to the fixed voltage to receive the first delayed clock signal and generate a second delayed clock signal that is delayed for a predetermined time period relative to the clock signal. The logic operation module receives the clock signal and the second delayed clock signal to perform a logic operation to generate a one-shot signal. | 02-18-2016 |
| 20160112035 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal. | 04-21-2016 |
| 20160164521 | SEMICONDUCTOR DEVICE - A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel. | 06-09-2016 |
