| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326094000 | Metastable state prevention | 10 |
| 20090121745 | DFLOP CIRCUIT FOR AN EXTERNALLY ASYNCHRONOUS-INTERNALLY CLOCKED SYSTEM - A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller. | 05-14-2009 |
| 20100194436 | VERIFICATION SUPPORT SYSTEM AND METHOD - A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic. | 08-05-2010 |
| 20110074466 | APPARATUS FOR METASTABILITY-HARDENED STORAGE CIRCUITS AND ASSOCIATED METHODS - A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs. | 03-31-2011 |
| 20110193593 | Apparatus for Metastability-Hardened Storage Circuits and Associated Methods - A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs. | 08-11-2011 |
| 20110199121 | SMART EDGE DETECTOR - In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D | 08-18-2011 |
| 20130015884 | SWITCHING CIRCUITS, LATCHES AND METHODS - Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level. | 01-17-2013 |
| 20140347099 | APPARATUSES, CIRCUITS, AND METHODS FOR REDUCING METASTABILITY IN DATA SYNCHRONIZATION - Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal. | 11-27-2014 |
| 20150015305 | DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY - Synchronisation circuitry | 01-15-2015 |
| 20150102838 | SEMICONDUCTOR DEVICE AND METHOD FOR DETECTING STATE OF INPUT SIGNAL OF SEMICONDUCTOR DEVICE - A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal. | 04-16-2015 |
| 20150326210 | TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE - An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred. | 11-12-2015 |
