| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326046000 | Sequential (i.e., finite state machine) or with flip-flop | 45 |
| 20080238479 | REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF - A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output. | 10-02-2008 |
| 20080238480 | REVERSIBLE SEQUENTIAL APPARATUSES - A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs. | 10-02-2008 |
| 20080258766 | Mixed Signal Integrated Circuit - This invention relates to mixed signal integrated circuits, that is, integrated circuits comprising both analogue and digital circuitry. More particularly, it concerns reduction of noise in such a device. When a digital circuit is included in the same integrated circuit device as an analogue circuit, the digital circuit may be an additional source of a considerable amount of noise. This results in cross-talk, electrical interference and signal distortion imposed on the analogue signals. The invention provides an integrated circuit comprising analogue circuitry ( | 10-23-2008 |
| 20080258767 | Computational nodes and computational-node networks that include dynamical-nanodevice connections - Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies. | 10-23-2008 |
| 20090039919 | DYNAMIC AND DIFFERENTIAL CMOS LOGIC WITH SIGNAL-INDEPENDENT POWER CONSUMPTION TO WITHSTAND DIFFERENTIAL POWER ANALYSIS - A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the input value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase. | 02-12-2009 |
| 20090051388 | Reducing leakage power in low power mode - Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal. | 02-26-2009 |
| 20090058463 | Sequential Circuit Element Including A Single Clocked Transistor - A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path. | 03-05-2009 |
| 20090115454 | Method and System for Reducing Power Consumption with Configurable Latches and Registers - Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation. | 05-07-2009 |
| 20090153189 | UNIVERSAL SERIAL BUS WAKEUP CIRCUIT - A circuit is attached in parallel to a universal serial bus interface of a data processing system. A capacitor in the circuit is charged by receiving power from a power pin of the universal serial bus interface while the data processing system is not in a reduced power state. A vibration sensor is unpowered while the data processing system is not in a reduced power state. The vibration sensor is disconnected from a data pin of the universal serial bus interface while the data processing system is not in a reduced power state. When the data processing system enters a reduced power state, the capacitor provides power to the vibration sensor. When a vibration is detected by the vibration sensor, a switch connects the vibration sensor to the data pin of the universal serial bus interface, providing a wake up signal to the data processing system. | 06-18-2009 |
| 20090167353 | State machines using resistivity-sensitive memories - State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array. | 07-02-2009 |
| 20090212818 | Integrated circuit design method for improved testability - An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type. In the flipflop-replaced netlist, the flipflop classified as the control type is replaced with a control flipflop which is configurable to toggle a data output thereof in synchronization with the clock signal by configuring a control input separately provided a data input thereof, and the flipflop classified as the hold type is replaced with a first hold flipflop which is configurable to hold data so that the data hold therein is unchanged. | 08-27-2009 |
| 20090267646 | Nano-Electron Fluidic Logic (NFL) Device - A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals at which the SPWs may be detected. A wave guiding structure such as a 2 DEG EF facilitates propagation of the SPW within the structure so as to scatter/steer the SPW in a direction different from a pre-scattering direction. A bias SPW is excited by an application of a control SPW with a momentum vector at an angle to the bias SPW and a control current with a wavevector which scatters the bias SPW in the direction of at least one output SPW, towards a drain terminal. The NFL device being rendered with device speed as a function of SPW propagation velocity. | 10-29-2009 |
| 20090322376 | SMI MEMORY READ DATA CAPTURE MARGIN CHARACTERIZATION CIRCUITS AND METHODS - The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system. | 12-31-2009 |
| 20100188118 | Semiconductor integrated circuit - Disclosed herein is a semiconductor integrated circuit including: a memory circuit section used for storing data; and a non-memory circuit section which is provided to serve as a section other than the memory circuit section and used for storing no data, wherein the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the non-memory circuit section is lower than the second-conduction-type impurity concentration of a second-conduction-type semiconductor area including a channel created for a first-conduction-type transistor employed in the memory circuit section. | 07-29-2010 |
| 20100289525 | LOGIC CIRCUIT - A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element ( | 11-18-2010 |
| 20100308864 | FLIP-FLOP CIRCUIT HAVING SCAN FUNCTION - A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal. | 12-09-2010 |
| 20110012641 | CELL ARRANGEMENT METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected. | 01-20-2011 |
| 20110062989 | State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories - State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array. | 03-17-2011 |
| 20110068824 | SHIFT REGISTER AND SEMICONDUCTOR DISPLAY DEVICE - The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled. | 03-24-2011 |
| 20110102017 | CONFIGURABLE TIME BORROWING FLIP-FLOPS - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 05-05-2011 |
| 20110133778 | NON-VOLATILE LOGIC CIRCUITS, INTEGRATED CIRCUITS INCLUDING THE NON-VOLATILE LOGIC CIRCUITS, AND METHODS OF OPERATING THE INTEGRATED CIRCUITS - Provided is a non-volatile logic circuit that includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells to be supplied first and second write voltages according to data of the pair of latch nodes when a write enable signal is activated such that a write operation is performed with respect to the pair of non-volatile memory cells. The first and second write voltages are different and logic values of data written to the respective non-volatile memory cells are different. | 06-09-2011 |
| 20110187410 | NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME - To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included. | 08-04-2011 |
| 20120007635 | SEMICONDUCTOR DEVICE - FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided. | 01-12-2012 |
| 20120068734 | Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques - Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool. | 03-22-2012 |
| 20120223739 | FLIP-FLOP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals. | 09-06-2012 |
| 20120223740 | RESET/LOAD AND SIGNAL DISTRIBUTION NETWORK - A tree-like signal distribution network comprises a plurality of branches extending from a plurality of branching points. The distribution network comprises a plurality of control blocks, each control block being situated at a branching point of the tree-like distribution network, wherein each of the plurality of control blocks is arranged such that it can distribute a signal received from the tree-like distribution network, a locally generated signal, and a combination of a signal received from the tree-like distribution network and a locally generated signal. | 09-06-2012 |
| 20120274356 | SIGNAL PROCESSING UNIT - A signal processing unit with reduced power consumption is provided. A transistor in which a channel is formed in an oxide semiconductor is used for a storage circuit included in the signal processing unit, so that data can be held (stored) even while supply of power is stopped. Non-destructive reading can be performed on the data stored in the storage circuit even when supply of power to the signal processing unit is stopped. | 11-01-2012 |
| 20120280713 | NONVOLATILE LATCH CIRCUIT AND NONVOLATILE FLIP-FLOP CIRCUIT - A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state. | 11-08-2012 |
| 20120306535 | STRUCTURES AND METHODS FOR DESIGN AUTOMATION OF RADIATION HARDENED TRIPLE MODE REDUNDANT DIGITAL CIRCUITS - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The | 12-06-2012 |
| 20130038348 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 02-14-2013 |
| 20130093463 | HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO - A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs. | 04-18-2013 |
| 20130181740 | MULTI-THRESHOLD SLEEP CONVENTION LOGIC WITHOUT NSLEEP - A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode. | 07-18-2013 |
| 20130234757 | Nonvolatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same - To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included. | 09-12-2013 |
| 20130293265 | SIGNAL TRANSFER CIRCUIT - A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal. | 11-07-2013 |
| 20140184268 | POWER CONSERVATION USING GRAY-CODED ADDRESS SEQUENCING - A multiplexer tree operable to control an output a sequence of data stored in a plurality of storage units in accordance with a non-linear address sequence that has less bit transition counts than a linear address sequence. The non-linear address sequence is provided to the selection inputs of the multiplexer tree and causes the levels having greater numbers of multiplexers to toggle less frequently than the levels having smaller numbers of multiplexers. The non-linear address sequence may comprise a Gray code sequence where every two adjacent addresses differ by a single bit. The non-linear address sequence may be optimized to minimize transistor switching in the multiplexer tree. | 07-03-2014 |
| 20140197864 | Non-Volatile Latch Structures with Small Area for FPGA - A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit. | 07-17-2014 |
| 20140347097 | SINGLE COMPONENT SLEEP-CONVENTION LOGIC (SCL) MODULES - A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing V | 11-27-2014 |
| 20150054547 | HARDWARE PREFIX REDUCTION CIRCUIT - A hardware prefix reduction circuit includes a plurality of levels. Each level includes an input conductor, an output conductor, and a plurality of nodes. Each node includes a buffer and a storage device that stores a digital logic level. One node further includes an inverter. Another node further includes an AND gate with two non-inverting inputs. Another node further includes an AND gate with an inverting input and a non-inverting input. One bit of an input value, such as an internet protocol address, is communicated on the input conductor. The first level of the prefix reduction circuit includes two nodes and each subsequent level includes twice as many nodes as is included in the preceding level. A digital logic level is individually programmed into each storage device. The digital logic levels stored in the storage devices determines the prefix reduction algorithm implemented by the hardware prefix reduction circuit. | 02-26-2015 |
| 20150091615 | Embedded Non-volatile Memory Circuit for Implementing Logic Functions Across Periods of Power Disruption - A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input. | 04-02-2015 |
| 20150370234 | DIGITAL TRIGGERING USING FINITE STATE MACHINES - An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, a multi-symbol FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an ordered sequence of digital values. The symbol generator generates one symbol corresponding to each of the digital values. The digital values have a greater number of possible values than the symbols. The controller causes the multi-symbol FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the sequence of digital values. A portion of the digital sequence is then displayed based on the location of the pattern in the sequence of symbols. | 12-24-2015 |
| 20160072480 | Systems and Methods for Setting Logic to a Desired Leakage State - Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage. | 03-10-2016 |
| 20160085223 | Digital Triggering Using Finite State Machines - An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, an FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an analog input signal. The symbols have a number of states that is less than or equal to 16. The controller causes the FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the analog signal. A portion of a digital sequence generated from the analog signal is then displayed based on the location of the pattern in the sequence of symbols. | 03-24-2016 |
| 20160179073 | Real Time Trigger Using A Finite State Machine Having A Counting State | 06-23-2016 |
| 20160188346 | METHODS AND SYSTEMS FOR DETECTION IN A STATE MACHINE - A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate. | 06-30-2016 |
| 20190146439 | REAL TIME TRIGGER USING A FINITE STATE MACHINE HAVING A COUNTING STATE | 05-16-2019 |
