| Entries |
| Document | Title | Date |
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| 20080231314 | Configurable IC Having A Routing Fabric With Storage Elements - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 09-25-2008 |
| 20080297194 | RECONFIGURABLE NETWORK COMPONENT LAYERS - A method for configuring an electronics device having reconfigurable network component layers is disclosed. The method selects a first group of pixels from at least one of the reconfigurable network component layers to form a network component on a substrate of the electronics device and activates the network component in at least one plane of the device substrate using a plurality of micro-electromechanical system (MEMS) switches adjacent to the first group of selected pixels. The method adjusts a first shape of the activated network component for the electronics device using the reconfigurable network component layers. | 12-04-2008 |
| 20090002020 | DYNAMICALLY TRACKING DATA VALUES IN A CONFIGURABLE IC - Some embodiments provide a method of dynamically tracking data values in a configurable integrated circuit (IC). The method, during a run time of the configurable IC, receives a request for a data value and dynamically configures the configurable IC to monitor the data value. | 01-01-2009 |
| 20090002021 | RESTRUCTURING DATA FROM A TRACE BUFFER OF A CONFIGURABLE IC - Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the traced buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays. | 01-01-2009 |
| 20090058459 | AUTO-TRIM CIRCUIT - An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits. | 03-05-2009 |
| 20090079466 | Soft-reconfigurable massively parallel architecture and programming system - The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof. | 03-26-2009 |
| 20090085605 | SYSTEM AND METHOD FOR PARALLEL BURNING USING MULTIPLEX TECHNOLOGY - A system and method for parallel burning using multiplex technology is used for burning chips of different bus types on the same transmission bus at the same time in parallel. A main control unit divides bandwidth of the transmission bus into different frequency bands, sends a control command including a command for sending data carrying bus signals of designated types, and controls data carrying the bus signals of the designated types to be transmitted in designated frequency bands of the transmission bus. Then, a sending unit sends the data carrying the bus signals of the designated types in the designated frequency band. Finally, receiving units receive the data transmitted in the designated frequency bands, and then output them to a plurality of burners such as to burn the data onto the chips of the designated bus types in parallel. | 04-02-2009 |
| 20090134908 | Multi-Functional Logic Gate Device and Programmable Integrated Circuit Device Using the Same - Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group. | 05-28-2009 |
| 20090251172 | SINGLE ELECTRON BASED FLEXIBLE MULTI-FUNCTIONAL LOGIC CIRCUIT AND THE TRANSISTOR THEREOF - The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs operations on multi-valued signals using Coulomb oscillation that is the unique characteristic of SET to enable conversion of a single logic circuit to four basic logic circuits of NAND, OR, NOR and AND gates and a device using the same. | 10-08-2009 |
| 20090273365 | DATA INPUT/OUTPUT MULTIPLEXER OF SEMICONDUCTOR DEVICE - There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line. | 11-05-2009 |
| 20090302886 | PROGRAMMABLE DEVICE - A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode. | 12-10-2009 |
| 20090309629 | PROGRAMMABLE CYCLE STATE MACHINE INTERFACE - A programmable cycle state machine interface to a microcontroller comprising a programmable cycle state machine, a first and second data bus, a first and second control output, and a control input for programming the cycle of the state machine. The programmable nature of the state machine allows for design and implementation changes without the need to redesign customized state machine logic on the microcontroller. | 12-17-2009 |
| 20100019797 | Mix Mode Driver For Traces Of Different Lengths - A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace. | 01-28-2010 |
| 20100026339 | ASICs Having More Features Than Generally Usable At One Time and Methods of Use - More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands. | 02-04-2010 |
| 20100127731 | Antifuse circuit of inverter type and method of programming the same - Example embodiments are directed to an antifuse circuit of an inverter type and a method of programming the same. The antifuse circuit has improved corrosion resistance, utilizes lesser chip area and can be programmed at a low voltage. The antifuse circuit includes a PMOS transistor with the gate coupled to a drive power voltage terminal and the source coupled to an anti-pad terminal. During programming the PMOS transistor is off and the source receives an alternating current. Programming the antifuse circuit involves trapping a plurality of electron in an STI region as a result of gate-induced drain leakage. The antifuse circuit also includes an NMOS transistor with the drain connected to the drain of the PMOS transistor, the source connected to ground and the gate connected to a program control signal. The antifuse circuit results in reliable fuse programming at a low voltage by using the PMOS transistor as an anti-fuse device. | 05-27-2010 |
| 20100213973 | Status holding circuit and status holding method - A status holding circuit includes status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a j | 08-26-2010 |
| 20100219858 | LOGIC BASED ON THE EVOLUTION OF NONLINEAR DYNAMICAL SYSTEMS - A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value. | 09-02-2010 |
| 20100244892 | ROM IMPLEMENTATION FOR ROM BASED LOGIC DESIGN - A logic device implementing configurations for ROM based logic uses arrays of memory cells to provide outputs based on inputs received at the logic device. The logic device stores values in the memory cells that are accessed when an input is received. The memory cells are transistors that provide values of ‘1’ or ‘0.’ Various configurations reduce the number of transistors while implementing the memory block by utilizing a single bitline or a dynamic precharge implementation. | 09-30-2010 |
| 20110031997 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse. | 02-10-2011 |
| 20110068823 | PROCESSOR PROGRAMMABLE PLD DEVICE - A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register. | 03-24-2011 |
| 20110089969 | IC WITH DESKEWING CIRCUITS - Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. | 04-21-2011 |
| 20110102014 | THREE DIMENSIONAL INTEGRATED CIRCUITS - A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers. | 05-05-2011 |
| 20110102015 | ELECTRONIC CIRCUIT DEVICE - In the electronic circuit device with stacked plural components of the same function, this invention enables to select an arbitrary component among plural components by a control element, without setting pre-determined identification information in each component. By installing a sequential logic circuit in each component, and changing a state of the sequential logic circuit by control data transmitted from the component stacked in a preceding stage or the control element, the state of the controlled component is set to a state that accepts a selection made by the control element. | 05-05-2011 |
| 20110148458 | MAGNETORESISTIVE ELEMENT, LOGIC GATE AND METHOD OF OPERATING LOGIC GATE - A logic gate | 06-23-2011 |
| 20110187407 | RADIO FREQUENCY-ENABLED ELECTROMIGRATION FUSE - Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist. | 08-04-2011 |
| 20110187408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another. | 08-04-2011 |
| 20110254585 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER BASED LOGIC DEVICES - A method and system for providing a logic device are described. The logic device includes a plurality of magnetic input/channel regions, at least one magnetic sensor region, and at least one sensor coupled with the at least one magnetic sensor region. Each of the magnetic input/channel regions is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that at least one domain wall resides in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to at least a portion of the magnetic input regions. | 10-20-2011 |
| 20120176153 | IN-CIRCUIT DATA COLLECTION USING CONFIGURABLE SELECTION NETWORKS - In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit. | 07-12-2012 |
| 20120176154 | ALL-SPIN LOGIC DEVICES - Illustrative embodiments of all-spin logic devices, circuits, and methods are disclosed. In one embodiment, an all-spin logic device may include a first nanomagnet, a second nanomagnet, and a spin-coherent channel extending between the first and second nanomagnets. The spin-coherent channel may be configured to conduct a spin current from the first nanomagnet to the second nanomagnet to determine a state of the second nanomagnet in response to a state of the first nanomagnet. | 07-12-2012 |
| 20120268162 | CONFIGURABLE LOGIC CELLS - An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems. | 10-25-2012 |
| 20120268163 | CONFIGURABLE LOGIC CELLS - A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control. | 10-25-2012 |
| 20120299620 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER BASED LOGIC DEVICES - A logic device is described. The logic device includes magnetic input/channel regions, magnetic sensor region(s), and sensor(s) coupled with the magnetic sensor region(s). Each magnetic input/channel region is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that domain wall(s) reside in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to the magnetic input region(s). The magnetic input/channel region(s) include Fe | 11-29-2012 |
| 20130002292 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE - A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register. | 01-03-2013 |
| 20130120021 | 3D IC STRUCTURE AND METHOD - An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus. | 05-16-2013 |
| 20130234756 | HYBRID IO CELL FOR WIREBOND AND C4 APPLICATIONS - A hybrid IO cell for use with controlled collapse chip connection, wirebond core limited, wirebond IO limited, and wirebond inline chip designs is provided. A method of designing the hybrid IO cell includes designating a technology, determining a minimum pad width of the technology, and determining a minimum pad spacing of the technology. The method also includes determining a width of the hybrid IO cell based on the minimum pad width and the minimum pad spacing, setting a length of the hybrid IO cell equal to the determined width, and storing a definition of the IO cell in a library stored on a computer useable storage medium. | 09-12-2013 |
| 20130293261 | SYSTEM ON CHIP AND CONTROL MODULE THEREFOR - A System on a Chip (SoC) has a first set of switches, each having first terminals for routing SoC signals and a second terminal, and a second set of switches. Each switch of the second set of switches has third terminals for routing signals with the first set of switches, and a fourth terminal. A SoC control module defines a switching configuration, and includes a first memory portion for storing a first switching protocol for the first set of switches. This defines, for a switch of the first set of switches, an electrical path between one of the first terminals and the second terminal. A second memory portion stores a second switching protocol for the second set of switches, and defines, for a switch of the second set of switches, an electrical path between one of the third terminals and the fourth terminal. | 11-07-2013 |
| 20140043061 | COMPUTING MULTI-MAGNET BASED DEVICES AND METHODS FOR SOLUTION OF OPTIMIZATION PROBLEMS - A computing multi-magnet device and method for solving complex computational problems is provided. Embodiments include a first magnet, a second magnet, and an interconnect between and interconnecting the first and second magnets, the interconnect configured to allow the first and second magnets to communicate via a voltage or current applied to the first and second magnet and conducted by the interconnect. The scalability of computing multi-magnet device provides solutions to algorithms that have exponentially increasing complexity. | 02-13-2014 |
| 20140062530 | SWITCHING MECHANISM OF MAGNETIC STORAGE CELL AND LOGIC UNIT USING CURRENT INDUCED DOMAIN WALL MOTIONS - A magnetic memory cell is provided that includes a free layer that is pinned on both of its sides to form one or more domain wall structures. The one or more domain wall structures define one or more logic states by controlling the motion of the one or more domain wall structures. | 03-06-2014 |
| 20140091834 | 3D IC STRUCTURE AND METHOD - An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus. | 04-03-2014 |
| 20140159770 | Nonvolatile Logic Circuit - One embodiment of a nonvolatile logic circuit includes a logic circuit comprising a first source terminal, a second source terminal, at least one input terminal, and an output terminal to temporarily store a logic state with a power dependent status, a high voltage source coupled to the first source terminal, a low voltage source coupled to the second source terminal, an intermediate voltage source comprising an electrical potential higher than that of the low voltage source but lower than that of the high voltage source, and a nonvolatile reversible resistance element coupled to the output terminal at a first end and to the intermediate voltage source at a second end. The nonvolatile reversible resistance element preserves the logic state of the logic circuit which is controlled by an input signal applied to the at least one input terminal. Other embodiment are described and shown. | 06-12-2014 |
| 20140176184 | Nonvolatile Logic Circuit Architecture & Method of Operation - Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc. | 06-26-2014 |
| 20140312930 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD FOR DRIVING THE SEMICONDUCTOR SYSTEM - A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (MRS) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals. | 10-23-2014 |
| 20140347094 | RECONFIGURABLE CIRCUIT BLOCK SUPPORTING DIFFERENT INTERCONNECTION CONFIGURATIONS FOR RATE-CONVERSION CIRCUIT AND PROCESSING CIRCUIT AND RELATED METHOD THEREOF - A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration. | 11-27-2014 |
| 20160020766 | NON-VOLATILE BOOLEAN LOGIC OPERATION CIRCUIT AND OPERATION METHOD THEREOF - A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M | 01-21-2016 |
| 20160043723 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. The semiconductor apparatus may include an enable signal generation block configured to generate an enable signal when a time corresponding to the select code passes, in response to the select signal. The semiconductor apparatus may include an operation signal output selection block configured to output the enable signal, as one of either a third operation signal or a fourth operation signal, in response to the is operation select signal. | 02-11-2016 |
