| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326044000 | Field effect transistor | 16 |
| 20080197879 | APPARATUS AND METHOD FOR A PROGRAMMABLE LOGIC DEVICE HAVING IMPROVED LOOK UP TABLES - A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2 | 08-21-2008 |
| 20090002025 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 01-01-2009 |
| 20090033361 | Switching circuits and methods for programmable logic devices - A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region. | 02-05-2009 |
| 20100156462 | PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR - A PLA contains an input plane ( | 06-24-2010 |
| 20110175646 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 07-21-2011 |
| 20120161813 | SWITCH APPARATUS FOR FIELD PROGRAMMABLE GATE ARRAY - A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration memory, and a voltage maintaining unit connected between the configuration memory and a gate of the pass transistor and configured to delay a drop of a gate voltage. | 06-28-2012 |
| 20120293203 | SEMICONDUCTOR DEVICE - A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor. | 11-22-2012 |
| 20130027081 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 01-31-2013 |
| 20130063179 | PROTECTING DATA FROM DECRYPTION FROM POWER SIGNATURE ANALYSIS IN SECURE APPLICATIONS - Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications. | 03-14-2013 |
| 20130241596 | PROGRAMMABLE LOGIC DEVICE - One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire. | 09-19-2013 |
| 20140285235 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device that includes a storage device having smaller area and lower power consumption is provided. The programmable logic device includes a logic block including a storage device. The storage device includes a plurality of groups each including at least a first switch, a transistor that is turned on or off in accordance with a signal including configuration data input to a gate of the transistor through the first switch, and a second switch controlling the electrical connection between a first wiring and a second wiring together with the transistor when the second switch is turned on or off in accordance with the potential of the first wiring. In the logic block, the relationship between the logic level of a signal input and the logic level of a signal output is determined in accordance with the potential of the second wiring. | 09-25-2014 |
| 20180026640 | SCALABLE INTEGRATED MOSFET (SIM) | 01-25-2018 |
| 20080197879 | APPARATUS AND METHOD FOR A PROGRAMMABLE LOGIC DEVICE HAVING IMPROVED LOOK UP TABLES - A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2 | 08-21-2008 |
| 20090002025 | MEMORY UTILIZING OXIDE NANOLAMINATES - Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers. | 01-01-2009 |
| 20090033361 | Switching circuits and methods for programmable logic devices - A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region. | 02-05-2009 |
| 20100156462 | PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR - A PLA contains an input plane ( | 06-24-2010 |
| 20110175646 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 07-21-2011 |
| 20120161813 | SWITCH APPARATUS FOR FIELD PROGRAMMABLE GATE ARRAY - A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration memory, and a voltage maintaining unit connected between the configuration memory and a gate of the pass transistor and configured to delay a drop of a gate voltage. | 06-28-2012 |
| 20120293203 | SEMICONDUCTOR DEVICE - A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor. | 11-22-2012 |
| 20130027081 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 01-31-2013 |
| 20130063179 | PROTECTING DATA FROM DECRYPTION FROM POWER SIGNATURE ANALYSIS IN SECURE APPLICATIONS - Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications. | 03-14-2013 |
| 20130241596 | PROGRAMMABLE LOGIC DEVICE - One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire. | 09-19-2013 |
| 20140285235 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device that includes a storage device having smaller area and lower power consumption is provided. The programmable logic device includes a logic block including a storage device. The storage device includes a plurality of groups each including at least a first switch, a transistor that is turned on or off in accordance with a signal including configuration data input to a gate of the transistor through the first switch, and a second switch controlling the electrical connection between a first wiring and a second wiring together with the transistor when the second switch is turned on or off in accordance with the potential of the first wiring. In the logic block, the relationship between the logic level of a signal input and the logic level of a signal output is determined in accordance with the potential of the second wiring. | 09-25-2014 |
| 20180026640 | SCALABLE INTEGRATED MOSFET (SIM) | 01-25-2018 |
| 326045000 | Complementary FET`s | 4 |
| 20090045840 | Method for Radiation Tolerance by Logic Book Folding - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells. | 02-19-2009 |
| 20090045841 | Method for Radiation Tolerance by Implant Well Notching - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book. | 02-19-2009 |
| 20120074984 | LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY - A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal. | 03-29-2012 |
| 20130293264 | FIELD PROGRAMMABLE ANALOG ARRAY - In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines. | 11-07-2013 |
| 20090045840 | Method for Radiation Tolerance by Logic Book Folding - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells. | 02-19-2009 |
| 20090045841 | Method for Radiation Tolerance by Implant Well Notching - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book. | 02-19-2009 |
| 20120074984 | LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY - A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal. | 03-29-2012 |
| 20130293264 | FIELD PROGRAMMABLE ANALOG ARRAY - In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines. | 11-07-2013 |
