Class / Patent application number | Description | Number of patent applications / Date published |
257394000 | With means to prevent parasitic conduction channels | 52 |
20080230851 | METAL OXIDE SEMICONDUCTOR (MOS) TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors. | 09-25-2008 |
20090032885 | Buried Isolation Layer - The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate, a P type contact region extending from the surface to the buried P type region, and an N type device region in the surface and above the buried P type region. The P type impurity of the buried P type region including an impurity of a lower coefficient of diffusion than the coefficient of diffusion of the impurities of the P type contact region. | 02-05-2009 |
20090218636 | INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS - An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening. | 09-03-2009 |
20090289311 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error - A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer. | 11-26-2009 |
20100032772 | Semiconductor device - A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a source region and a drain region of a reverse conductivity type arranged to sandwich a region immediately below a gate electrode, and an impurity diffusion region of the one conductivity type formed in the element forming region. The source region is separated from a region on a boundary side between the element isolation film and the element forming region in the region immediately below the gate electrode in the element forming region. In the impurity diffusion region, a portion adjacent to the region on the boundary side is arranged between the source region and the element isolation film, and is in contact with the source region and the region on the boundary side. The impurity diffusion region is not arranged between the drain region and the element isolation film. | 02-11-2010 |
20100038726 | RADIATION HARDENED DEVICE - A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance. | 02-18-2010 |
20100102398 | Material removing processes in device formation and the devices formed thereby - Devices having voids are producible by employing an electrochemical corrosion process. For example, an electrically conductive region is formed to have a surrounding chemically distinct region. Such formation is possible through conventional semiconductor processing techniques such as a copper damascene process. The surrounded conducting material is configured to be in electrical communication with a charge separation structure. The electrically conducting region is contacted with a fluid electrolyte and electromagnetic radiation is made to illuminate the charge separation region to induce separation of electrons and holes. The resulting separated charges are used to drive an electrochemical corrosion process at the conductive material/electrolyte interface resulting in the removal of at least a portion of the electrically conducting material. The induced corrosion leaves a void that is useful, for example, as a highly effective dielectric in integrated circuits, functions to allow component separation such as gear separation in microelectromechanical devices or produces long cavities useful for material separation analogous to the distillation columns used in liquid chromatography. | 04-29-2010 |
20110169101 | Fin Field Effect Transistor (FINFET) - A Fin FET whose fin ( | 07-14-2011 |
20120056274 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: transistor Tr | 03-08-2012 |
20130234258 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer. | 09-12-2013 |
20140159162 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140159163 | BULK FINFET WITH SUPER STEEP RETROGRADE WELL - A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor. | 06-12-2014 |
20140239411 | Through Vias and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region. | 08-28-2014 |
20140264627 | MULTI-GATE TRANSISTOR - Disclosed is a multi-gate transistor which includes a plurality of gates that is branched from one port, that is alternately formed to face each other, and in which currents flow in the adjacent gates in an opposite direction to each other; a source that is formed on one side or the other side of each of the plurality of gates; and a drain that is formed on the other side or the one side of each of the plurality of gates. | 09-18-2014 |
20140306293 | SEMICONDUCTOR MEMORY DEVICE INCLUDING GUARD BAND - The semiconductor memory device including a first sense amplifier region including first metal-oxide-semiconductor (MOS) transistors disposed in a well on a semiconductor substrate, a second sense amplifier region adjacent to the well and including second MOS transistors disposed on the semiconductor substrate, a guard band having a bar type structure and provided between the first MOS transistors in the well, and a guard ring partially or fully enclosing the second sense amplifier region in the semiconductor substrate may be provided. | 10-16-2014 |
20150102424 | Forming Conductive STI Liners for FinFETS - An integrated circuit device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions. | 04-16-2015 |
20150129978 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE - A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate. | 05-14-2015 |
20150372076 | Semiconductor Switching Device with Different Local Cell Geometry - A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. | 12-24-2015 |
20150380490 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A MISFET has a threshold voltage that is not undesirably increased due to channel narrowing of the MISFET, and the MISFET is reduced in size and increased in withstand voltage. An anti-inversion p-type channel stopper region provided below an element isolation trench has an end that projects toward a channel region below a gate oxide film, and terminates short of the channel region. That is, the end is offset from the end of the channel region (the end of the element isolation trench). This suppresses diffusion in a lateral direction (channel region direction) of an impurity in the p-type channel stopper region, and thus suppresses a decrease in carrier concentration at the end of the channel region. As a result, a local increase in threshold voltage is suppressed. | 12-31-2015 |
20190148375 | METAL GATE MODULATION TO IMPROVE KINK EFFECT | 05-16-2019 |
20190148507 | TRANSISTOR LAYOUT TO REDUCE KINK EFFECT | 05-16-2019 |
257395000 | Thick insulator portion | 29 |
20140191333 | METHOD OF PROTECTING AN INTERLAYER DIELECTRIC LAYER AND STRUCTURE FORMED THEREBY - This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures. | 07-10-2014 |
20150054088 | INTEGRATED DEVICE WITH RAISED LOCOS INSULATION REGIONS AND PROCESS FOR MANUFACTURING SUCH DEVICE - An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion. | 02-26-2015 |
257396000 | Recessed into semiconductor surface | 27 |
20080211037 | Semiconductor Device and Method of Forming Isolation Layer Thereof - A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming a spacer layer on side walls of the conductive layer; forming a trench on the semiconductor substrate between the spacer layer-covered side walls; removing the spacer layer to form a step on an upper edge of the trench; and forming a liner insulating layer on the trench. The method makes it possible to solve problems caused by impurities present in material with which the trench is gap-filled or present in etchants used in an etch-back process. | 09-04-2008 |
20080258237 | SEMICONDUCTOR DEVICE HAVING MULTI-CHANNEL AND METHOD OF FABRICATING THE SAME - An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region. | 10-23-2008 |
20080277740 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions. | 11-13-2008 |
20080315325 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate and being surrounded by the trenches; a gate electrode formed along a first direction on the element forming region via a gate insulating film, the gate electrode extending over the element insulating film filled the trenches extending along a second direction; a source/drain region having a second depth less than the first depth formed in the element forming region beside the gate electrode and having an exposed surface exposed to a trench sidewall; wherein the upper surface of the element isolation insulating film exclusive of a portion underlying the gate electrode is located at a third depth greater than the second depth and less than the first depth. | 12-25-2008 |
20090085128 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate including a plurality of device regions and a device isolation region defining the device regions, and a semiconductor element located in a major surface of the semiconductor substrate and formed in at least one of the device regions. The device isolation region has a DTI (deep trench isolation) structure and has a bottom exposed to a backside of the semiconductor substrate. | 04-02-2009 |
20090096037 | SEMICONDUCTOR DEVICE HAVING RECESSED FIELD REGION AND FABRICATION METHOD THEREOF - A semiconductor device including an active region formed on a semiconductor substrate, and a field region adjacent to the active region, which is able to increase a width of the active region through use of a field recess portion at one surface side of the field region. The field recess portion may be laterally adjacent to a portion of the active region, thereby resulting in an increase of a width of the active region. A gate insulating film and a gate electrode may be formed on the field region and the active region, the gate insulating film and the gate electrode being formed in the field recess portion. The width of the active region may be a channel width. | 04-16-2009 |
20090101991 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure. | 04-23-2009 |
20090315121 | STABLE STRESS DIELECTRIC LAYER - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric (PMD) layer is disposed over the substrate and the transistor. At least one of the isolation region or the PMD layer includes O | 12-24-2009 |
20090315122 | SEMICONDUCTOR DEVICE HAVING OHMIC RECESSED ELECTRODE - The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced. | 12-24-2009 |
20110233686 | INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING - An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. | 09-29-2011 |
20130037888 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug. | 02-14-2013 |
20150097248 | SHALLOW TRENCH ISOLATION - The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer. | 04-09-2015 |
257397000 | In vertical-walled groove | 15 |
20080217702 | Semiconductor device and method of fabricating isolation region - A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation region including a liner film formed so as to contact a lower surface and a lower side surface of an inner wall of a trench formed in the semiconductor substrate, a first insulating film formed so that at least a part of a side surface and a lower surface of the first insulating film contact the liner film within the trench, and a second insulating film formed so as to contact an upper side of the first insulating film and formed so as to contact an upper side surface of the inner wall of the trench, the second insulating film having a higher etching resistance than that of the first insulating film; and a plurality of semiconductor elements disposed on the semiconductor substrate so as to be isolated from one another by the isolation region. | 09-11-2008 |
20080217703 | HIGHLY SELECTIVE LINERS FOR SEMICONDUCTOR FABRICATION - A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein. | 09-11-2008 |
20080217704 | Semiconductor device - In a semiconductor device including multiple unit cells arranged in an array, transistors are affected by a stress from an STI at different degrees depending on the position in the array. As a result, a variation occurs in transistor characteristic. In a semiconductor device according to the present invention, each of predetermined transistors in outermost unit blocks in the array has a transistor size according to the stress from the STI. | 09-11-2008 |
20080258238 | Semiconductor Device Manufactured Using an Oxygenated Passivation Process During High Density Plasma Deposition - In one aspect, the method comprises forming trenches in a semiconductor substrate and filling the trenches with a dielectric material. The process of filling the trenches includes depositing the dielectric material with a plasma gas mixture, etching the dielectric material with a chemical etch including nitrogen fluoride and using a passivation process to passivate the dielectric material after etching with a gas mixture that includes oxygen and hydrogen. | 10-23-2008 |
20080258239 | METHODS FOR MANUFACTURING A TRENCH TYPE SEMICONDUCTOR DEVICE HAVING A THERMALLY SENSITIVE REFILL MATERIAL - Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular, methods of manufacturing and devices of a trench type semiconductor devices containing organic refill materials are provided. | 10-23-2008 |
20080265338 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-30-2008 |
20080303102 | Strained Isolation Regions - An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure. | 12-11-2008 |
20090032886 | SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS - A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction. | 02-05-2009 |
20090140350 | LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES - An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width. | 06-04-2009 |
20090194825 | SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE - By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements. | 08-06-2009 |
20090250769 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 10-08-2009 |
20130277759 | Semiconductor Fin Structures and Methods for Forming the Same - A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region. | 10-24-2013 |
20140291770 | Method of Making a FinFET Device - The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. | 10-02-2014 |
20140346612 | BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES - A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices. | 11-27-2014 |
20150318349 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer. | 11-05-2015 |
257400000 | With heavily doped channel stop portion | 2 |
20140291771 | TID Hardened and Single Even Transient Single Event Latchup Resistant MOS Transistors and Fabrication Process - A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring. | 10-02-2014 |
20160141355 | ACTIVE DEVICE AND SEMICONDUCTOR DEVICE WITH THE SAME - A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region. The active device is self-isolated by a conductive guarding structure, and the semiconductor device comprising embodied STI-free active devices solves STI edge issues. | 05-19-2016 |