| Entries |
| Document | Title | Date |
|---|
| 20080217701 | Design solutions for integrated circuits with triple gate oxides - An integrated circuit includes a first core circuit and a second core circuits. The first core circuit includes a first MOS device, wherein a first gate dielectric of the first MOS device has a first thickness. The second core circuit includes a second MOS device, wherein a second gate dielectric of the second MOS device has a second thickness less than the first thickness. A first power supply line having a first power supply voltage is connected to the first and the second core circuits a first power supply voltage. | 09-11-2008 |
| 20080224234 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film. | 09-18-2008 |
| 20080230850 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern. | 09-25-2008 |
| 20080246094 | Method for Manufacturing SRAM Devices with Reduced Threshold Voltage Deviation - A semiconductor device includes a semiconductor substrate; a gate dielectric layer disposed on the semiconductor substrate; a gate conductive layer doped with impurities selected from nitrogen, carbon, silicon, germanium, fluorine, oxygen, helium, neon, xenon or a combination thereof on the gate dielectric layer; and source/drain doped regions formed adjacent to the gate conductive layer in the semiconductor substrate, wherein the source and drain doped regions are substantially free of the impurities doped into the gate conductive layer. These impurities reduce the diffusion rates of the N-type of P-type dopants in the gate conductive layer, thereby improving the device performance. | 10-09-2008 |
| 20080258236 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n | 10-23-2008 |
| 20080265336 | METHOD OF FORMING A HIGH-K GATE DIELECTRIC LAYER - A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer. | 10-30-2008 |
| 20080265337 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device fabrication method for forming a gate insulating film of a low leakage transistor and a gate insulating film of a high performance transistor. A first SiON film is formed over a Si substrate through first film formation. The first SiON film is left where the low leakage transistor is to be formed, and is removed where the high performance transistor is to be formed. Through second film formation, a second SiON film is formed where the first SiON film is removed, and a third SiON film including the first SiON film is formed where the first SiON film is left. The formed first SiON film has thickness and nitrogen concentration so that the third SiON film has thickness and nitrogen concentration to be the gate insulting film of the low leakage transistor. | 10-30-2008 |
| 20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 12-04-2008 |
| 20080315324 | METHOD TO OBTAIN UNIFORM NITROGEN PROFILE IN GATE DIELECTRICS - The present invention, in one aspect, provides a method of manufacturing a microelectronics device | 12-25-2008 |
| 20090014812 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors. | 01-15-2009 |
| 20090039444 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate including an upper surface having a first region including a pair of first impurity diffusion regions and a first channel region located between the impurity diffusion regions and a second region including a recess having a predetermined depth relative to the upper surface, a first gate insulating film, a first gate electrode of a first transistor supplying a first voltage, a second gate insulating film having a second thickness larger than a first thickness of the first gate insulating film, an upper surface of the second gate insulating film located at a same level as an upper surface of the first gate insulating film, and a second gate electrode of a second transistor supplying a second voltage being higher than the first voltage. | 02-12-2009 |
| 20090039445 | VARIABLE WIDTH OFFSET SPACERS FOR MIXED SIGNAL AND SYSTEM ON CHIP DEVICES - MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer. | 02-12-2009 |
| 20090050978 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate insulating film between the source and the drain, plural insular back gate diffusion layers of the first conductive type provided in the source so as to be in contact with the semiconductor substrate, wherein the back gate diffusion layers are spaced apart and arranged in the predetermined direction in the source, and a contact hole extending in the predetermined direction on the source and at least one of the back gate diffusion layers. | 02-26-2009 |
| 20090050979 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film. | 02-26-2009 |
| 20090057778 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type. | 03-05-2009 |
| 20090057779 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having a first area implanted with first conductive type impurities; an isolating film defining a first active area and a second active area in the first area; first LDD areas spaced from each other on the first active area at a first interval and implanted with second conductive type impurities; and second LDD areas spaced from each other on the second active area at a second interval narrower than the first interval and implanted with the second conductive type impurities. | 03-05-2009 |
| 20090072323 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate. | 03-19-2009 |
| 20090090978 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET. | 04-09-2009 |
| 20090096036 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided. | 04-16-2009 |
| 20090108372 | SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS - A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means. | 04-30-2009 |
| 20090108373 | Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks - Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET. | 04-30-2009 |
| 20090108374 | HIGH DENSITY SRAM CELL WITH HYBRID DEVICES - Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-up devices of the inverters and the pass gate devices are planar FETs or pull-down and pull-up devices of the inverters are FinFETs while the pass gate devices are planar FETs. | 04-30-2009 |
| 20090114998 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A first MIS transistor is formed in a low voltage transistor formation region and includes a gate insulating film and a first gate electrode composed of a metal film and a polycrystalline silicon film. A second MIS transistor is formed in a high voltage transistor formation region and includes a gate insulating film and a second gate electrode composed of a polycrystalline silicon film. An equivalent oxide thickness of the gate insulating film formed in the low voltage transistor formation region is thinner than an equivalent oxide thickness of the gate insulating film formed in the high voltage transistor formation region. A level of the surface of a semiconductor substrate in the low voltage transistor formation region is higher than a level of the surface of a semiconductor substrate in the high voltage transistor formation region. | 05-07-2009 |
| 20090146220 | MULTI DEVICE AND METHOD OF MANUFACTURING THE SAME - Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be a two-layered structure in which a first LDD region and a second LDD region are disposed vertically downward from the surface of a wafer, and the second LDD region is substantially the same as an LDD structure in the second MOS transistor in doping concentration. | 06-11-2009 |
| 20090174009 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration. | 07-09-2009 |
| 20090194822 | CONTINUOUS MULTIGATE TRANSISTORS - An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric layer, electrically coupled to the gate to form continuous multigate transistors. | 08-06-2009 |
| 20090194823 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET. | 08-06-2009 |
| 20090230482 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region. | 09-17-2009 |
| 20090250766 | Work Function Based Voltage Reference - A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. | 10-08-2009 |
| 20090250767 | ED INVERTER CIRCUIT AND INTEGRATE CIRCUIT ELEMENT INCLUDING THE SAME - A second semiconductor layer of a second nitride-based compound semiconductor with a wider bandgap formed on a first semiconductor layer of a first nitride-based compound semiconductor with a smaller bandgap includes an opening, on which a gate insulating layer is formed at a portion exposed through the opening. A first source electrode and a first drain electrode formed across a first gate electrode make an ohmic contact to the second semiconductor layer. A second source electrode and a second drain electrode formed across a second gate electrode that makes a Schottky contact to the second semiconductor layer make an ohmic contact to the second semiconductor layer. | 10-08-2009 |
| 20090250768 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate | 10-08-2009 |
| 20090261423 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a fin field effect transistor configured to include at least a first fin and a second fin. Threshold voltage of the first fin and threshold voltage of the second fin are different from each other in the fin field effect transistor. | 10-22-2009 |
| 20090261424 | METHOD FOR FABRICATING A DUAL WORKFUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. | 10-22-2009 |
| 20090278208 | Semiconductor integrated circuit device and method of fabricating the same - A semiconductor integrated circuit device with higher integration density and a method of fabricating the same are provided. The semiconductor integrated circuit device may include trench isolation regions in a semiconductor substrate that define an active region and a gate pattern that is used for a higher voltage and formed on the active region of the semiconductor substrate. Trench insulating layers may be formed in the semiconductor substrate on and around edges of the gate pattern so as to be able to relieve an electrical field from the gate pattern. The depths of each of the trench insulating layers may be defined according to an operating voltage. Source and drain regions enclose the trench insulating layers and may be formed in the semiconductor substrate on both sides of the gate pattern. Therefore, the semiconductor integrated circuit device may have a higher integration density and may relieve an electrical field from the gate pattern. | 11-12-2009 |
| 20090283842 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate comprising first and second transistor regions that are isolated by an element isolation region; a first impurity diffusion suppression layer formed on the semiconductor substrate in the first transistor region; a second impurity diffusion suppression layer formed on the semiconductor substrate in the second transistor region, and having a thickness larger than that of the first impurity diffusion suppression layer; a first crystal layer formed on the first impurity diffusion suppression layer; a second crystal layer formed on the second impurity diffusion suppression layer; a first gate electrode formed on the first crystal layer via a first gate insulating film; a second gate electrode formed on the second crystal layer via a second gate insulating film; a first channel region formed in a region in the semiconductor substrate, the first impurity diffusion suppression layer and the first crystal layer below the first gate electrode in the first transistor region, and containing a first p-type impurity; a second channel region formed in a region in the semiconductor substrate, the second impurity diffusion suppression layer and the second crystal layer below the second gate electrode in the second transistor region, and containing a second p-type impurity; first source/drain regions formed on both sides of the first channel region; and second source/drain regions formed on both sides of the second channel region; wherein a concentration of the first p-type impurity in a region of the first channel region in the first crystal layer is lower than that in a region of the first channel region in the semiconductor substrate; and a concentration of the second p-type impurity in a region of the second channel region in the second crystal layer is lower than that in a region of the second channel region in the semiconductor substrate. | 11-19-2009 |
| 20090289310 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region. | 11-26-2009 |
| 20090321849 | SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness. | 12-31-2009 |
| 20090321850 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 12-31-2009 |
| 20100001351 | TRIPLE WELL TRANSMIT-RECEIVE SWITCH TRANSISTOR - A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor. | 01-07-2010 |
| 20100013028 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film. | 01-21-2010 |
| 20100025776 | DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS BY LOCAL GATE ENGINEERING - In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced. | 02-04-2010 |
| 20100038724 | Metal-Gate High-K Reference Structure - Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure. | 02-18-2010 |
| 20100038725 | CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION - Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region. | 02-18-2010 |
| 20100052073 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage MISFET is inevitably high in level. Accordingly, the depth of a gate contact is shallow so that process compatibility with the typical portion is necessary. In the present invention, in, e.g., the channel width direction of the high-breakdown-voltage MISFET, the boundary of a thick-film gate oxide region is located inwardly of the end of a gate electrode. At the gate electrode portion thus lowered in level, a gate contact is disposed so that the boundary of the thick film is located inwardly of the end of the gate electrode and between the gate contact and a channel end. | 03-04-2010 |
| 20100059832 | Semiconductor device - Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed. | 03-11-2010 |
| 20100078734 | Method of manufacturing semiconductor device having plural transistors formed in wellregion and semiconductor device - A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the same conductive type, and the first transistor and the second transistor have the same threshold voltage. A first well is formed in the first element formation region by use of a first mask pattern, and a second well is formed in the second element formation region by use of a second mask pattern. A channel region of the first transistor and a channel region of the second transistor have a shape which is line-symmetrical with respect to a reference line. The first mask pattern has a shape which is line-symmetrical with respect to the reference line. | 04-01-2010 |
| 20100102397 | Transistor, semiconductor device including a transistor and methods of manufacturing the same - A transistor, a semiconductor device including the transistor and methods of manufacturing the same are provided, the transistor including a threshold voltage adjusting layer contacting a channel layer. A source electrode and a drain electrode contacting may be formed opposing ends of the channel layer. A gate electrode separated from the channel layer may be formed. A gate insulating layer may be formed between the channel layer and the gate electrode. | 04-29-2010 |
| 20100109095 | METHOD FOR FABRICATING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material. | 05-06-2010 |
| 20100123200 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device which includes, on the same semiconductor substrate, a first FET and a second FET higher in threshold voltage than the first FET. The first FET includes a first gate insulating film and a first gate electrode. The second FET includes a second gate insulating film and a second gate electrode. The first gate electrode, the second gate insulating film, and the second gate electrode contain at least one metal element selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ta, and W. Concentration of the at least one metal element at an interface between the second gate insulating film and the second gate electrode in the second FET is higher than concentration of the at least one metal element at an interface between the first gate insulating film and the first gate electrode in the first FET. | 05-20-2010 |
| 20100123201 | Semiconductor Devices - A semiconductor device includes a substrate, a first channel layer pattern, a second channel layer pattern, a first transistor and a second transistor. The substrate has a first region and a second region. The first channel layer pattern is formed in the first region of the substrate and has a first volume. The second channel layer pattern is formed in the second region of the substrate and has a second volume that is different from the first volume. The first transistor includes a first gate insulation layer pattern on the first channel layer pattern, a first gate electrode on the first gate insulation layer pattern, and a first source/drain region in contact with the first channel layer pattern. The second transistor includes a second gate insulation layer pattern on the second channel layer pattern, a second gate electrode on the second gate insulation layer pattern, and a second source/drain region in contact with the second channel layer pattern. | 05-20-2010 |
| 20100133627 | DEPLETION-TYPE NAND FLASH MEMORY - A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage. | 06-03-2010 |
| 20100140720 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well. | 06-10-2010 |
| 20100148278 | Semiconductor Device and Fabricating Method Thereof - A semiconductor device and fabricating method thereof are disclosed. The method includes forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area, partially etching the polysilicon layer in the low-voltage area, forming an anti-reflective layer on the polysilicon layer to reduce a step difference between the high-voltage and low-voltage areas, forming a photoresist pattern in the high-voltage and low-voltage areas, and forming a high-voltage gate and a low-voltage gate by etching the polysilicon layer using the photoresist pattern as an etch mask. | 06-17-2010 |
| 20100148279 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film. | 06-17-2010 |
| 20100155854 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage. | 06-24-2010 |
| 20100155855 | Band Edge Engineered Vt Offset Device - Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a first type. The structure further includes a second FET having a channel of a second compound semiconductor of second atomic proportions resulting in a second band structure and a first type. The first compound semiconductor is different from the second compound semiconductor such that the first FET has a first band structure different from second band structure, giving rise to a threshold voltage different from that of the second FET. | 06-24-2010 |
| 20100155856 | Transistor, a transistor arrangement and method thereof - A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer. | 06-24-2010 |
| 20100164014 | REDUCTION OF THRESHOLD VOLTAGE VARIATION IN TRANSISTORS COMPRISING A CHANNEL SEMICONDUCTOR ALLOY BY REDUCING DEPOSITION NON-UNIFORMITIES - A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced. | 07-01-2010 |
| 20100164015 | SEMICONDUCTOR DEVICE - When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage. | 07-01-2010 |
| 20100176459 | ASSEMBLY OF NANOSCALED FIELD EFFECT TRANSISTORS - The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic. | 07-15-2010 |
| 20100176460 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation region containing oxygen atoms and isolating the first transistor from the second transistor. | 07-15-2010 |
| 20100187639 | Semiconductor device and fabrication method - A semiconductor device has a semiconductor substrate in which first and second wells are formed. The substrate and wells are of the same conductivity type, but the second well has a higher impurity concentration than the first well. High-voltage MOS transistors are formed in the first well, and a low-voltage MOS transistor is formed in the second well. The high-voltage MOS transistors include a first transistor having a gate oxide layer with a first thickness and a second transistor having a gate oxide layer with a second thickness less than the first thickness. The low-voltage MOS transistor has a third gate oxide layer with a third thickness less than the first thickness. The second high-voltage MOS transistor provides efficient current conduction. | 07-29-2010 |
| 20100193878 | HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT - A semiconductor device | 08-05-2010 |
| 20100193879 | Isolation Region Implant and Structure - A method and structure for modulating the threshold voltage of transistor is provided. An opening for an isolation region is formed within a substrate using a masking layer. The masking layer is then pulled back from the opening, and dopants are implanted into the substrate through the exposed surface of the substrate and the sidewalls of the opening. This implantation can be tailored to modulate the threshold voltage of transistors with smaller gate widths without modulating the threshold voltage of other transistors with larger gate widths. | 08-05-2010 |
| 20100230764 | INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD - An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel. | 09-16-2010 |
| 20100237436 | SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit comprising a first transistor in a first Fin; a power supply circuit in a second Fin, the power supply circuit comprising a second transistor connected between the circuit and a power supply line; and a substrate contact electrically connected to the semiconductor substrate and configured to apply a substrate voltage to a substrate, wherein a width of the first Fin in a cross-section of the first Fin perpendicular to a channel length direction of the first transistor is equal to or smaller than a twofold of a largest depletion layer width of a depletion layer formed in a channel part of the first transistor, and a width of the second Fin in a cross-section of the second Fin perpendicular to a channel length direction of the second transistor is larger than a twofold of a largest depletion layer width of a depletion layer in a channel of the second transistor. | 09-23-2010 |
| 20100244145 | Semiconductor memory device using hot electron injection - A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer. | 09-30-2010 |
| 20100289088 | THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER - An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above. | 11-18-2010 |
| 20100289089 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. | 11-18-2010 |
| 20100289090 | ENHANCING UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING STI STRUCTURES AFTER THE GROWTH PROCESS - When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced. | 11-18-2010 |
| 20100295137 | METHOD AND APPARATUS PROVIDING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSITORS IN AN INTEGRATED CIRCUIT - An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors. | 11-25-2010 |
| 20100301427 | WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER - In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration. | 12-02-2010 |
| 20100308418 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor. | 12-09-2010 |
| 20100314691 | Method for selective gate halo implantation in a semiconductor die and related structure - According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region. | 12-16-2010 |
| 20100320545 | PLANAR AND NON-PLANAR CMOS DEVICES WITH MULTIPLE TUNED THRESHOLD VOLTAGES - A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material. | 12-23-2010 |
| 20100327372 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance ratio of Si—H bond to N—H bond per unit volume, an amount of Cl per unit volume and an amount of H per unit volume of the second sidewall is larger than that of the first sidewall; and a threshold voltage of the second transistor is higher than that of the first transistor. | 12-30-2010 |
| 20100327373 | UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING - Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned. | 12-30-2010 |
| 20110006378 | Semiconductor Manufacturing Method Using Maskless Capping Layer Removal - A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices. | 01-13-2011 |
| 20110042756 | Semiconductor device and method for manufacturing the same - A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions A | 02-24-2011 |
| 20110049642 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS - In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided. | 03-03-2011 |
| 20110068412 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer. | 03-24-2011 |
| 20110089498 | INTEGRATION OF LOW AND HIGH VOLTAGE CMOS DEVICES - A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first portion of the substrate, the first transistor being operable at a first voltage, and forming a second transistor in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage. The formation of the second transistor includes forming an extended feature of the second transistor with a photomask that is used to adjust a threshold voltage of the first transistor. | 04-21-2011 |
| 20110101466 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 05-05-2011 |
| 20110101467 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug. | 05-05-2011 |
| 20110115030 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a partially depleted first transistor formed in a semiconductor layer on an insulating layer; a second transistor formed in the semiconductor layer; and a third transistor formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below a side of the first gate electrode, the second transistor has a second gate electrode formed above the semiconductor layer via the insulating film and a second source or a second drain of the first conductivity type formed in the semiconductor layer below a side of the second gate electrode, the third transistor has a third gate electrode formed above the semiconductor layer via the insulating film and a third source or a third drain of a second conductivity type formed in the semiconductor layer below a side of the third gate electrode, one of the first source and the first drain and one of the second source and the second drain are electrically connected, and the other of the second source and the second drain, a region of the semiconductor layer just below the first gate electrode, and one of the third source and the third drain are electrically connected to one another. | 05-19-2011 |
| 20110121404 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 05-26-2011 |
| 20110121405 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING TRANSISTORS AND SEMICONDUCTOR DEVICE HAVING TRANSISTORS - A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern. | 05-26-2011 |
| 20110127616 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE - In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies. | 06-02-2011 |
| 20110133291 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - Disclosed is a fabrication method which includes: forming a first gate electrode and a second gate electrode which cross over an active region, the overall width of the second gate electrode being less than that of the first gate electrode; ion-implanting dopants into the active region at an oblique angle using the first and second gate electrodes as a mask for ion-implantation, thereby to form separated doped regions on opposite sides of the first gate electrode and to form a continuous doped region extending from one of opposite sides of the second gate electrode to the other. | 06-09-2011 |
| 20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
| 20110156167 | Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same - A circuit is defined to operate in accordance with a common control signal. The circuit includes a plurality of transistors that have respective timing margins relative to the common control signal. Some of the plurality of transistors are defined differently from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof. The different definition of any given one of the plurality of transistors causes a reduction of either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a corresponding reduction in timing margin while maintaining a positive timing margin. | 06-30-2011 |
| 20110204451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction. | 08-25-2011 |
| 20110210402 | METAL-GATE HIGH-K REFERENCE STRUCTURE - Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure. | 09-01-2011 |
| 20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
| 20110221009 | METHOD AND APPARATUS FOR REDUCING GATE RESISTANCE - An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region. | 09-15-2011 |
| 20110227169 | SEMICONDUCTOR DEVICE - The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package. | 09-22-2011 |
| 20110248357 | INTEGRATED CIRCUIT DEVICES INCLUDING DEVICE ISOLATION STRUCTURES AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed. | 10-13-2011 |
| 20110278680 | Strained Semiconductor Device and Method of Making the Same - In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess. | 11-17-2011 |
| 20110291201 | MULTI-STRAINED SOURCE/DRAIN STRUCTURES - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor. | 12-01-2011 |
| 20110298057 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction. | 12-08-2011 |
| 20110309454 | COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE - A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation. | 12-22-2011 |
| 20120018812 | METHOD AND STRUCTURE FOR BALANCING POWER AND PERFORMANCE USING FLUORINE AND NITROGEN DOPED SUBSTRATES - Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power leakage and second sets of integrated circuit transistor structures that need higher performance to achieve the desired power consumption balance and performance balance. With this, the methods and systems alter the integrated circuit design to include implantation of a first dopant into a substrate before a gate insulator formation for the first sets of integrated circuit transistor structures; and alter the integrated circuit design to include implantation of a second dopant into the substrate before a gate insulator formation for the second sets of integrated circuit transistor structures. The method and system then output the altered integrated circuit design from the computerized device and/or manufactures the device according to the altered integrated circuit design. | 01-26-2012 |
| 20120018813 | BARRIER COAT FOR ELIMINATION OF RESIST RESIDUES ON HIGH k/METAL GATE STACKS - A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs. | 01-26-2012 |
| 20120018814 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor device is disclosed as follows. A first oxide film in a first region and a second oxide film in a second region are formed on a semiconductor substrate. A high-k insulating film is formed on the first oxide film and the second oxide film. A film containing at least one of elements of Mg, La, Y, Dy, Sc, Al is formed on the high-k insulating film. After forming the film containing the element, thermal treatment is performed, so that the element in the film is diffused into the first oxide film and the second oxide film via the high-k insulating film. A metal gate electrode containing a metal material is formed on the high-k insulating film on the first oxide film and on the high-k insulating film on the second oxide film. | 01-26-2012 |
| 20120025325 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 02-02-2012 |
| 20120056271 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film. | 03-08-2012 |
| 20120056272 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor having a first conductivity type; and a second transistor having the first conductivity type and having a higher threshold voltage than the first transistor. The first transistor includes a first channel region having a second conductivity type, a first gate insulating film, a first gate electrode, and a first extension region having the first conductivity type. The second transistor includes a second channel region having the second conductivity type, a second gate insulating film, a second gate electrode, and a second extension region having the first conductivity type. The second extension region contains impurities for shallower junction. A junction depth of the second extension region is shallower than a junction depth of the first extension region. | 03-08-2012 |
| 20120080758 | METHOD FOR FABRICATING AT LEAST THREE METAL-OXIDE SEMICONDUCTOR TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers. | 04-05-2012 |
| 20120091537 | SEMICONDUCTOR DEVICE - In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors. | 04-19-2012 |
| 20120126336 | Isolation FET for Integrated Circuit - An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs. | 05-24-2012 |
| 20120139057 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device, having more than two types of threshold voltages, can be employed in a logic integrated circuit with an embedded SRAM. The semiconductor device can include at least two transistors. The two transistors can be the same conductivity type (e.g., n-type or p-type). In addition, the two transistors can have disparate voltage thresholds. | 06-07-2012 |
| 20120153401 | Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material - In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors. | 06-21-2012 |
| 20120161245 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes first and second FETs having the same conductivity type. The first FET includes a first gate electrode, a first side wall, and first extension regions respectively provided in a first active region on both sides of the first gate electrodes. The second FET includes a second gate electrode, a second side wall, and second extension regions respectively provided in a second active region on both sides of the second gate electrode. An overlap of each of the first extension regions and the first gate electrode in a gate length direction is longer than an overlap of each of the second extension regions and the second gate electrode. The distance between the first gate electrode and the first side wall is shorter than the distance between the second gate electrode and the second side wall. | 06-28-2012 |
| 20120161246 | SEMICONDUCTOR DEVICE - A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET | 06-28-2012 |
| 20120168876 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLURAL TRANSISTORS FORMED IN WELL REGION AND SEMICONDUCTOR DEVICE - A semiconductor device, includes a substrate, an element isolating film formed in the substrate, a first element formation region isolated by the element isolating film, a second element formation region positioned adjacent to the first element formation region and isolated by the element isolating film, a first well of a second conductive type formed in a whole area of the first element formation region, a first transistor of a first conductive type formed on the first element formation region, a second transistor of the first conductive type which is formed on the first element formation region and whose threshold voltage is the same as a threshold voltage of the first transistor, a second well of the second conductive type formed in a whole area of the second element formation region, and a third transistor of the first conductive type formed on the second element formation region. | 07-05-2012 |
| 20120175712 | Multiple Vt Field-Effect Transistor Devices - Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. | 07-12-2012 |
| 20120193727 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors. | 08-02-2012 |
| 20120223396 | TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS - One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. | 09-06-2012 |
| 20120228721 | SEMICONDUCTOR DEVICE AND REFERENCE VOLTAGE GENERATION CIRCUIT - In a gate electrode ( | 09-13-2012 |
| 20120235247 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 09-20-2012 |
| 20120241871 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 09-27-2012 |
| 20120248548 | ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT WITH TRANSISTORS COUPLED TO EACH OTHER - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 10-04-2012 |
| 20120261767 | METHOD AND STRUCTURE FOR REDUCING GATE LEAKAGE CURRENT AND POSITIVE BIAS TEMPERATURE INSTABILITY DRIFT - Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides. | 10-18-2012 |
| 20120261768 | SRAM CELL WITH ASYMMETRICAL PASS GATE - A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( | 10-18-2012 |
| 20120280330 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices including first and second fin active regions protruding vertically from a substrate and integrally formed with the substrate, a gate insulation layer formed on the first and second fin active regions, a first gate metal contacting the gate insulation layer on the first fin active region, and a second gate metal contacting the first gate metal on the first fin active region and contacting the gate insulation layer on the second fin active region. | 11-08-2012 |
| 20120292715 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping | 11-22-2012 |
| 20120299118 | Multiple Threshold Voltages in Field Effect Transistor Devices - A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel. | 11-29-2012 |
| 20120319210 | METHOD FOR 1/F NOISE REDUCTION IN NMOS DEVICES - An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than | 12-20-2012 |
| 20130043543 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including a first driving transistor region having a first driving transistor disposed therein and a second driving transistor region having a second driving transistor disposed therein, wherein the second driving transistor is driven at a lower voltage than the first driving transistor, a first gate insulating layer formed at edges of the second driving transistor region, and a second gate insulating layer formed at a center of the second driving transistor region, wherein the first gate insulating layer is thicker than the second gate insulating layer. | 02-21-2013 |
| 20130049134 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - In a semiconductor device and a method of making the same, a first transistor has a gate stack comprising an underlying layer formed of a first material and an overlying layer formed of a second material. A second transistor has a gate stack comprising an underlying layer formed of a third material and an overlying layer formed of the second material. A third transistor has a gate stack comprising an underlying layer formed of the first material and an overlying layer formed of a fourth material. A fourth transistor has a gate stack comprising an underlying layer formed of the third material and an overlying material formed of the fourth material. Each of the first through fourth materials has a respectively different work function, so that each of the first through fourth transistors has a respectively different threshold voltage. | 02-28-2013 |
| 20130140644 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed. | 06-06-2013 |
| 20130181298 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 07-18-2013 |
| 20130200467 | DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES - A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors. | 08-08-2013 |
| 20130214364 | REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER - A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate. | 08-22-2013 |
| 20130234257 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 09-12-2013 |
| 20130241003 | FINFET AND FABRICATING METHOD THEREOF - A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. | 09-19-2013 |
| 20130241004 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced. | 09-19-2013 |
| 20130256808 | Semiconductor Device and Method of Manufacturing the Same - The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved. | 10-03-2013 |
| 20130264654 | Integrated Switching Device with Parallel Rectifier Element - An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer. | 10-10-2013 |
| 20130264655 | SEMICONDUCTOR DEVICE, DESIGNING METHOD THEREFOR, AND MANUFACTURING METHOD THEREFOR - In a semiconductor device including active regions which are adjacent to each other with an element isolation region interposed therebetween and which are different in height from the element isolation region, when a contact is formed in a gate wiring on the element isolation region, a contact failure is caused. Provided is a semiconductor device including an element isolation region, two active regions adjacent to each other with the element isolation region interposed therebetween and having surfaces which are higher than that of the element isolation region, a gate wiring commonly led from the respective active regions and extending through the element isolation region, and a contact for connecting the gate wiring to a conductor layer above the gate wiring. The contact is provided in a region other than the element isolation region, or is provided in an expanded element isolation region. | 10-10-2013 |
| 20130285156 | FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING - A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers. | 10-31-2013 |
| 20130299916 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer. | 11-14-2013 |
| 20130307086 | MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES - In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics. | 11-21-2013 |
| 20130313654 | Integrated Circuit Devices Including Device Isolation Structures and Methods of Fabricating the Same - An integrated circuit device includes a substrate having adjacent first and second regions, and a device isolation structure in the substrate between the first and second regions. The first and second regions of the substrate may respectively include transistors configured to be driven at different operational voltages, and the device isolation structure may electrically separates the transistors of the first region from the transistors of the second region. The device isolation structure includes outer portions immediately adjacent to the first and second regions and an inner portion therebetween. The outer portions of the device isolation structure comprise a material having an etching selectivity with respect to that of the inner portion. Related devices and fabrication methods are also discussed. | 11-28-2013 |
| 20130320459 | Semiconductor Isolation Structure with Air Gaps in Deep Trenches - A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate. | 12-05-2013 |
| 20130328133 | INTEGRATED CIRCUIT DEVICE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - Integrated circuit device with transistors having different threshold voltages and methods of forming the device are provided. The device may include the first, second and third transistors having threshold voltages different from each other. The first transistor may be free of a stacking fault and the second transistor may include a stacking fault. The concentration of the channel implant region of the third transistor may be different from the concentration of the channel implant region of the first transistor. | 12-12-2013 |
| 20130334612 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - An integrated circuit includes a plurality of transistors. Each transistor is associated with a corresponding body terminal. At least one transistor is reverse biased at a first voltage level, and at least one other transistor is reverse biased at a second voltage level that is different from the first voltage level. Each body terminal is electrically isolated from every other body terminal via an isolation barrier. A transistor that is reverse biased at the first voltage level is electrically connected to a transistor that is reverse biased at the second voltage level, such that the electrically connected transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit. | 12-19-2013 |
| 20140001569 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS | 01-02-2014 |
| 20140001570 | COMPOSITE HIGH-K GATE DIELECTRIC STACK FOR REDUCING GATE LEAKAGE | 01-02-2014 |
| 20140001571 | SEMICONDUCTOR STRUCTURE WITH MULTIPLE TRANSISTORS HAVING VARIOUS THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF | 01-02-2014 |
| 20140015066 | SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor. | 01-16-2014 |
| 20140027859 | METHODS OF FORMING TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS AND THE RESULTING DEVICES - Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal). | 01-30-2014 |
| 20140042552 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - Provided is a semiconductor device having an insulating gate field effect transistor equipped with a metal oxide film in a portion, on the side of a source region, between a gate insulating film and a gate electrode. The metal oxide film is provided above a p | 02-13-2014 |
| 20140061819 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 03-06-2014 |
| 20140077310 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other. | 03-20-2014 |
| 20140084382 | DUAL METAL FILL AND DUAL THRESHOLD VOLTAGE FOR REPLACEMENT GATE METAL DEVICES - A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors. | 03-27-2014 |
| 20140091399 | ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A VERTICLE CONDUCTIVE STRUCTURE - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 04-03-2014 |
| 20140091400 | Gate Dielectric Of Semiconductor Device - A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described. | 04-03-2014 |
| 20140097502 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses. | 04-10-2014 |
| 20140124872 | SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided. | 05-08-2014 |
| 20140131811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature. | 05-15-2014 |
| 20140145273 | INTEGRATED JUNCTION AND JUNCTIONLESS NANOTRANSISTORS - Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor. | 05-29-2014 |
| 20140183659 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
| 20140191332 | PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS - Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different. | 07-10-2014 |
| 20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 09-04-2014 |
| 20140252495 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 09-11-2014 |
| 20140264625 | Merged Active Devices on a Common Substrate - Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented. | 09-18-2014 |
| 20140264626 | METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer. | 09-18-2014 |
| 20140299940 | SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor. | 10-09-2014 |
| 20140312429 | Power Semiconductor Device with Oscillation Prevention - There are disclosed herein various implementations of composite semiconductor devices with active oscillation control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device may be configured to include one or both of a reduced output resistance due to, for example, a modified body implant and a reduced transconductance due to, for example, a modified oxide thickness to cause a gain of the composite semiconductor device to be less than approximately 10,000. | 10-23-2014 |
| 20140327087 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions. | 11-06-2014 |
| 20140339645 | METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES - One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material. | 11-20-2014 |
| 20140339646 | NON-PLANAR TRANSITOR FIN FABRICATION - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins. | 11-20-2014 |
| 20140367795 | METHODS OF FORMING DIFFERENT FINFET DEVICES HAVING DIFFERENT FIN HEIGHTS AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH DEVICES - One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height. | 12-18-2014 |
| 20140367796 | MOS DEVICE ASSEMBLY - A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage. | 12-18-2014 |
| 20140374837 | SEMICONDUCTOR DEVICE - A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin. | 12-25-2014 |
| 20150008533 | MULTI-PORT SRAM MANUFACTURING - Some embodiments relate to an integrated circuit including fin field effect transistors (FinFETs) thereon. The integrated circuit includes first and second active fin regions having a first conductivity type and spaced apart from one another. A gate dielectric layer is disposed over the first and second active fin regions. First and second gate electrodes are disposed over the first and second active fin regions, respectively. The first and second gate electrodes are also disposed over the gate dielectric layer. The first and second gate electrodes are electrically coupled together and are electrically separated from the first and second active fin regions by the gate dielectric layer. The first gate electrode is made of a first metal having a first workfunction, and the second gate electrode is made of a second metal having a second workfunction that differs from the first workfunction. | 01-08-2015 |
| 20150014786 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell. | 01-15-2015 |
| 20150014787 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a first insulation film on a portion of a first region of a semiconductor substrate and forming a second insulation film between a second region and a third region of the semiconductor substrate; etching an upper portion of the first insulation film such that the thickness of the first insulation film is less than the thickness of the second insulation film; forming a third insulation film in the second region and forming a fourth insulation film in the third region; and forming a first gate electrode on the first insulation film whose upper portion was etched, forming a second gate electrode on the third insulation film, and forming a third gate electrode on the fourth insulation film. | 01-15-2015 |
| 20150041916 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A co-implant concentration of a source region of a pull-down transistor is higher than those of other co-implant concentrations. Thus, dopants in a halo region of the source region may be prevented from excessively being diffused into a channel region during a post annealing process. As a result, dispersion of saturation threshold voltages of unit memory cells may be reduced. | 02-12-2015 |
| 20150041917 | FIELD-EFFECT TRANSISTOR STACK VOLTAGE COMPENSATION - Field-effect transistor (FET) stack voltage compensation. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series between the first and terminal and the second terminal. Each switching element has a parameter that is configured to yield a desired voltage drop profile among the connected switching elements. Such a desired voltage drop profile can be achieved by some or all FETs in a stack having variable dimensions such as variable gate width or variable numbers of fingers associated with the gates. | 02-12-2015 |
| 20150069524 | Method of Forming Different Voltage Devices with High-K Metal Gate - A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( | 03-12-2015 |
| 20150069525 | SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES - A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers. | 03-12-2015 |
| 20150076617 | METHODS OF FORMING PATTERNS OF A SEMICONDUCTOR DEVICE - Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask. | 03-19-2015 |
| 20150091097 | HARDMASK FOR A HALO/EXTENSION IMPLANT OF A STATIC RANDOM ACCESS MEMORY (SRAM) LAYOUT - Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor. | 04-02-2015 |
| 20150115369 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 04-30-2015 |
| 20150137261 | SEMICONDUCTOR DEVICE - A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates. | 05-21-2015 |
| 20150145062 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 05-28-2015 |
| 20150145063 | FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES - A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device. | 05-28-2015 |
| 20150303115 | MODIFICATION OF A THRESHOLD VOLTAGE OF A TRANSISTOR BY OXYGEN TREATMENT - Methodologies and resulting devices are provided for modified FET threshold voltages. Embodiments include: providing an active region of a transistor on a semiconductor substrate; depositing a workfunction metal on the active region; and modifying a threshold voltage of the transistor by treating the workfunction metal with oxygen. Other embodiments include: providing first and second active regions in a semiconductor substrate for first and second transistors, respectively; forming a first workfunction metal on the first active region; forming a second workfunction metal on the second active region; and modifying a first threshold voltage level of the first transistor, a second threshold voltage level of the second transistor, or a combination thereof by treating the first workfunction metal, second workfunction metal, or a combination thereof with oxygen, wherein the second threshold voltage level is greater than the first threshold voltage level. | 10-22-2015 |
| 20150303194 | FINFET SEMICONDUCTOR DEVICES INCLUDING DUMMY STRUCTURES - Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure. | 10-22-2015 |
| 20150303202 | SEMICONDUCTOR DEVICES HAVING VERTICAL DEVICE AND NON-VERTICAL DEVICE AND METHODS OF FORMING THE SAME - A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate. | 10-22-2015 |
| 20150311189 | LOW NOISE AND HIGH PERFORMANCE LSI DEVICE - In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied. | 10-29-2015 |
| 20150318282 | Multiple Channel Length Finfets with Same Physical Gate Length - A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure. | 11-05-2015 |
| 20150318293 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided. | 11-05-2015 |
| 20150325576 | INDEPENDENT GATE VERTICAL FINFET STRUCTURE - A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction. | 11-12-2015 |
| 20150333060 | Semiconductor Device - A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part. | 11-19-2015 |
| 20150333142 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer. The second metal gate includes a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer. The first p-work function metal layer and the second p-work function metal layer include a same p-typed metal material. A thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer. The first p-work function metal layer, the second p-work function metal layer, and the n-work function metal layer include a U shape. | 11-19-2015 |
| 20150340344 | LOW PARASITIC CAPACITANCE SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package includes a substrate, a transistor, and a lead frame disposed on a side of the substrate opposite to the transistor. The transistor is disposed on the substrate, and includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, a first drain pad, a source plug, and a drain plug. The source and the drain electrodes are disposed on the active layer. An orthogonal projection of the source electrode on the active layer forms a source region. The first insulating layer covers at least a portion of the source electrode and at least a portion of the drain electrode. The first source pad and the first drain pad are disposed on the first insulating layer. An orthogonal projection of the first source pad on the active layer forms a source pad region overlaps the drain region. | 11-26-2015 |
| 20150340362 | TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS - An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material. | 11-26-2015 |
| 20150348788 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first dummy gate on the semiconductor substrate in the first region and a device layer on the semiconductor substrate in the second region. The method also includes forming a dielectric layer on of the first dummy gate and the device layer; and removing the first dummy gate to form a first trench. Further, the method includes forming a first metal layer on the first trench and the surfaces of the dielectric layer and the device layer; and performing a first planarization process onto the first metal layer using a polishing slurry having a first protective agent to form a first gate electrode in the first trench and form a protective layer on the device layer preventing the device layer being damaged during the first planarization process. | 12-03-2015 |
| 20150348973 | SEMICONDUCTOR INTEGRATED CIRCUIT (IC) DEVICE AND METHOD OF MANUFACTURING THE SAME - The charge retention characteristics of a semiconductor integrated circuit (IC) device are improved. A semiconductor integrated circuit (IC) device SM includes an n | 12-03-2015 |
| 20150349071 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance. | 12-03-2015 |
| 20150349076 | VARIABLE LENGTH MULTI-CHANNEL REPLACEMENT METAL GATE INCLUDING SILICON HARD MASK - A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks. | 12-03-2015 |
| 20150364556 | INTEGRATED CIRCUIT CHIPS HAVING FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE DESIGNS - An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor. | 12-17-2015 |
| 20150372112 | REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY - After formation of a gate cavity straddling at least one semiconductor material portion, a gate dielectric layer and at least one work function material layer is formed over the gate dielectric layer. The at least one work function material layer and the gate dielectric layer are patterned such that remaining portions of the at least one work function material layer are present only in proximity to the at least one semiconductor material portion. A conductive material having a greater conductivity than the at least one work function material layer is deposited in remaining portions of the gate cavity. The conductive material portion within a replacement gate structure has the full width of the replacement gate structure in regions from which the at least one work function material layer and the gate dielectric layer are removed. | 12-24-2015 |
| 20150380507 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line. | 12-31-2015 |
| 20160005658 | METAL GATE STRUCTURE AND METHOD OF MAKING THE SAME - A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer. | 01-07-2016 |
| 20160005734 | INTEGRATED CIRCUIT PRODUCT COMPRISED OF MULTIPLE P-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES - Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer. | 01-07-2016 |
| 20160027892 | METAL GATE STRUCTURE - The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer. | 01-28-2016 |
| 20160043076 | INTEGRATION OF ANALOG TRANSISTOR - An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose. | 02-11-2016 |
| 20160043643 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode. | 02-11-2016 |
| 20160049396 | Systems and Methods for Fabricating Semiconductor Devices at Different Levels - Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures. | 02-18-2016 |
| 20160056082 | CHEMICAL MECHANICAL POLISHING METHOD FOR FIRST INTERLAYER DIELECTRIC LAYER - A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region, forming a first gate structure in the low-density region and a second gate structure in the high-density region, form an etch stop layer on the first and second gate structures, and forming an interlayer dielectric layer on the etch stop layer and on the semiconductor substrate. The method further includes performing a first chemical mechanical polishing (CMP) process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the first gate structure, performing a second CMP process on the etch stop layer to expose a surface of a portion of the etch stop layer disposed on the second gate structure, and performing a third CMP process to completely remove the etch stop layer. | 02-25-2016 |
| 20160056289 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced. | 02-25-2016 |
| 20160071844 | FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF - A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed. | 03-10-2016 |
| 20160071944 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other. | 03-10-2016 |
| 20160079154 | SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME - Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench. | 03-17-2016 |
| 20160086949 | Dummy Metal Gate Structures to Reduce Dishing During Chemical-Mechanical Polishing - The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect. | 03-24-2016 |
| 20160087037 | SEMICONDUCTOR STRUCTURE WITH STRAINED SOURCE AND DRAIN STRUCTURES AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid. | 03-24-2016 |
| 20160093535 | METHOD AND APPARATUS OF MULTI THRESHOLD VOLTAGE CMOS - A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer. | 03-31-2016 |
| 20160093536 | INTEGRATED CIRCUIT HAVING PLURAL TRANSISTORS WITH WORK FUNCTION METAL GATE STRUCTURES - The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. | 03-31-2016 |
| 20160099330 | SEMICONDUCTOR DEVICE WITH NANOWIRES IN DIFFERENT REGIONS AT DIFFERENT HEIGHTS - A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses. | 04-07-2016 |
| 20160104699 | SEMICONDUCTOR APPARATUS - There is provided a semiconductor apparatus comprising: a first switching element formed of a wide band gap semiconductor; and a second switching element formed of another wide band gap semiconductor and connected in parallel with the first switching element; wherein the first switching element and the second switching element respectively include a control electrode, a first main electrode and a second main electrode, and respectively have an output capacitance characteristic in which an output capacitance decreases as a voltage between the first main electrode and the second main electrode increases, and the output capacitance characteristics of the first switching element and the second switching element or threshold voltages for respectively turning on/off the first switching element and the second switching element are different from each other. | 04-14-2016 |
| 20160104704 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance. | 04-14-2016 |
| 20160111420 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure. | 04-21-2016 |
| 20160126139 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer. | 05-05-2016 |
| 20160126240 | METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP - A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a characteristic, and the first RF component is configured to operate in a first RF band associated with a first frequency. The device further includes a second RF component on the die. The second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value. The second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency. | 05-05-2016 |
| 20160126243 | Semiconductor Device with Enhancement and Depletion FinFET Cells - A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins. | 05-05-2016 |
| 20160133535 | SILICON PACKAGE HAVING ELECTRICAL FUNCTIONALITY BY EMBEDDED PASSIVE COMPONENTS - A packaged electronic system comprises a slab ( | 05-12-2016 |
| 20160133627 | Semiconductor Device - A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface. | 05-12-2016 |
| 20160141211 | SEMICONDUCTOR DEVICE INCLUDING POWER AND LOGIC DEVICES AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions. | 05-19-2016 |
| 20160163601 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities. | 06-09-2016 |
| 20160181254 | LOW-DRIVE CURRENT FINFET STRUCTURE FOR IMPROVING CIRCUIT DENSITY OF RATIOED LOGIC IN SRAM DEVICES | 06-23-2016 |
| 20160181256 | LOW-DRIVE CURRENT FINFET STRUCTURE FOR IMPROVING CIRCUIT DENSITY OF RATIOED LOGIC IN SRAM DEVICES | 06-23-2016 |
| 20160190127 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell. | 06-30-2016 |
| 20160190237 | LATCHUP REDUCTION BY GROWN ORTHOGONAL SUBSTRATES - An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer. | 06-30-2016 |
| 20160203988 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF | 07-14-2016 |
| 20170236759 | DUAL WORK FUNCTION CMOS DEVICES | 08-17-2017 |
