| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257377000 | With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide) | 26 |
| 20080203493 | Semiconductor memory device and fabrication process thereof - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element. | 08-28-2008 |
| 20080230844 | Semiconductor Device with Multiple Silicide Regions - A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate. | 09-25-2008 |
| 20080246092 | Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure - A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect. | 10-09-2008 |
| 20080251855 | LOW CONTACT RESISTANCE CMOS CIRCUITS AND METHODS FOR THEIR FABRICATION - A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer. | 10-16-2008 |
| 20080277736 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×10 | 11-13-2008 |
| 20080296696 | Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices - Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate. | 12-04-2008 |
| 20080315319 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film. | 12-25-2008 |
| 20090020827 | THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME - A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench. | 01-22-2009 |
| 20090045469 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device including a silicon substrate; a gate insulating film on the silicon substrate; a gate electrode on the gate insulating film; and source/drain regions formed in the substrate on both sides of the gate electrode, wherein the gate electrode includes a first silicide layered region formed of a silicide of a metal M | 02-19-2009 |
| 20090079008 | CMOS Fabrication Process - Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm | 03-26-2009 |
| 20090085126 | Hybrid metal fully silicided (FUSI) gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 04-02-2009 |
| 20090096034 | Partially and Fully Silicided Gate Stacks - Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer. | 04-16-2009 |
| 20090194820 | CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS - A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient. | 08-06-2009 |
| 20090194821 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film. | 08-06-2009 |
| 20100019327 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having first and second active areas defined thereon by isolation layers, a first gate electrode in the first active area, in which the first gate electrode includes a first silicide, and a second gate electrode in the second active area, in which the second gate electrode includes a second silicide having a composition ratio of silicon different from a composition ratio of silicon of the first silicide. | 01-28-2010 |
| 20100059830 | Semiconductor device - In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10 | 03-11-2010 |
| 20100078731 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer. | 04-01-2010 |
| 20100109091 | RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS - During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency. | 05-06-2010 |
| 20100123198 | Semiconductor devices and methods of manufacturing the same - Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same. One or more of the semiconductor devices include a substrate having first and second active regions; a P-channel field-effect transistor associated with the first active region and including at least one of the source and drain regions; a N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; a first contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the P-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; a second contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the N-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; an interlayer insulating film formed on the P-channel and the N-channel field-effect transistors and including first and second contact holes, wherein the first contact hole includes a first lower region that exposes the SiGe epitaxial layer of the first contact pad layer and the second contact hole includes a second lower region that penetrates through the SiGe epitaxial layer of the second contact pad layer to expose the Si epitaxial layer of the second contact pad layer; first and second metal silicide films formed respectively in the first and second lower regions of the contact holes; and contact plugs formed on the first and second metal silicide films and filled in the first and second contact holes. | 05-20-2010 |
| 20100193876 | METHOD TO REDUCE MOL DAMAGE ON NiSi - Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance. | 08-05-2010 |
| 20100207215 | Semiconductor Device and Method of Producing the Same - A semiconductor device includes a semiconductor substrate; an N-channel type transistor forming region formed on the semiconductor substrate; a P-channel type transistor forming region formed on the semiconductor substrate and arranged adjacent to the N-channel type transistor forming region; and a gate electrode formed on the semiconductor substrate over the N-channel type transistor forming region and the P-channel type transistor forming region. The gate electrode has a boundary inclusion portion formed in a first region including a boundary line between the N-channel type transistor forming region and the P-channel type transistor forming region and a boundary exclusion portion formed in a second region not including the boundary line. The gate electrode includes a conductive silicon layer and a metal silicide layer formed on the conductive silicon layer. The metal silicide layer has a first thickness in the boundary inclusion portion and a second thickness from the first thickness in the boundary exclusion portion. | 08-19-2010 |
| 20130062705 | SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREFOR - In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a V | 03-14-2013 |
| 20140151816 | NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region. | 06-05-2014 |
| 20140246729 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern. | 09-04-2014 |
| 20150061034 | DEVICES HAVING INHOMOGENEOUS SILICIDE SCHOTTKY BARRIER CONTACTS - A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a plurality of transistors formed thereon, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region on the silicon including surface. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and n-type surface regions. | 03-05-2015 |
| 20150076615 | INTERDIGITATED FINFETS - A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer. | 03-19-2015 |
