Class / Patent application number | Description | Number of patent applications / Date published |
257367000 | Insulated gate controlled breakdown of pn junction (e.g., field plate diode) | 10 |
20080197417 | Segmented pillar layout for a high-voltage vertical transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 08-21-2008 |
20080197418 | Gate pullback at ends of high-voltage vertical transistor structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 08-21-2008 |
20080265329 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING IT - A semiconductor device which has a semiconductor body and a method for producing it. At the semiconductor body, a first electrode which is electrically connected to a first near-surface zone of the semiconductor body and a second electrode which is electrically connected to a second zone of the semiconductor body are arranged. A drift section is arranged between the first and the second electrode. In the drift section, a coupling structure is provided for at least one field plate arranged in the drift section. The coupling structure has a floating first area doped complementarily to the drift section and a second area arranged in the first area. The second area forms a locally limited punch-through effect or an ohmic contact to the drift section, and the field plate is electrically connected at least to the second area. | 10-30-2008 |
20090140343 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE - A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation. | 06-04-2009 |
20100148268 | INSULATED-GATE SEMICONDUCTOR DEVICE - Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region. | 06-17-2010 |
20100176452 | LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL - A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body. | 07-15-2010 |
20110068406 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, a first source portion, a second source portion, a drain portion, a first main electrode, a second main electrode, and a gate electrode. The first source portion includes a first source contact region of a second conductivity type and a back gate contact region of the first conductivity type. The drain portion includes a drain contact region of the second conductivity type, a first drift region of the second conductivity type, and a second drift region of the second conductivity type. When a reverse bias is applied to p-n junction between the semiconductor layer and the drain portion, avalanche breakdown is more likely to occur near the first drift region than near the second drift region. | 03-24-2011 |
20140001557 | SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS | 01-02-2014 |
20140167171 | SEMICONDUCTOR DEVICE - An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion. | 06-19-2014 |
20180026105 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 01-25-2018 |