Class / Patent application number | Description | Number of patent applications / Date published |
257364000 | With resistive gate electrode | 11 |
20080258225 | MOS TRANSISTORS HAVING HIGH-K OFFSET SPACERS THAT REDUCE EXTERNAL RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS transistors having high-k spacers and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack overlying a semiconductor substrate and forming an offset spacer about sidewalls of the gate stack. The offset spacer is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer and the semiconductor substrate. First ions of a conductivity-determining impurity type are implanted into the semiconductor substrate using the gate stack and the offset spacer as an implantation mask to form spaced-apart impurity-doped extensions. | 10-23-2008 |
20090173999 | FIELD EFFECT TRANSISTOR WITH GATE HAVING VARYING SHEET RESISTANCE - A field effect transistor (FET) comprising a gate structure that includes at least one gate having a varying sheet resistance in a direction between a source contact and a drain contact. In an illustrative embodiment, the FET can be configured to operate as a radio frequency switch. In this case, the FET can provide improved performance with respect to both the off-state capacitances and radio frequency isolations over similar FETs implemented with typical gates. | 07-09-2009 |
20090184373 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other. | 07-23-2009 |
20090189221 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate on either side of the gate electrode; a PMD (poly-metal dielectric) liner nitride layer having a non-stoichiometric structure formed on the gate electrode, the source region, and the drain region; and an interlayer insulating layer formed on the PMD liner nitride layer. | 07-30-2009 |
20100052058 | DOWNSIZE POLYSILICON HEIGHT FOR POLYSILICON RESISTOR INTEGRATION OF REPLACEMENT GATE PROCESS - A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure. | 03-04-2010 |
20100109085 | MEMORY DEVICE DESIGN - Memory elements and methods for making memory elements. One method of making a memory element includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell. The memory elements may be resistance random access memory elements. | 05-06-2010 |
20110241118 | METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE - A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top. | 10-06-2011 |
20120181612 | LOW TCR HIGH RESISTANCE RESISTOR - The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height. | 07-19-2012 |
20130134519 | SEMICONDUCTOR DEVICE - A semiconductor device includes a conductive film formed on an insulating film, and a first polysilicon film formed on the conductive film. A stacked film including the conductive film and the first polysilicon film forms a first pattern including a central region, and end regions each located at a side of the central region. A silicide film is formed on at least the central region of the stacked film. A discontinuity is formed in a central region of the conductive film. The conductive film is separated into the two portions by the discontinuity. | 05-30-2013 |
20130240994 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line. | 09-19-2013 |
20150348979 | HIGH DENSITY SINGLE-TRANSISTOR ANTIFUSE MEMORY CELL - Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure. | 12-03-2015 |