| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257360000 | Protection device includes insulated gate transistor structure (e.g., combined with resistor element) | 44 |
| 20080211027 | ESD structure without ballasting resistors - An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor. | 09-04-2008 |
| 20080211028 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode. | 09-04-2008 |
| 20080211029 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 09-04-2008 |
| 20080237721 | STRUCTURE AND CIRCUIT TECHNIQUE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE - An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device. | 10-02-2008 |
| 20080277729 | ELECTROSTATIC DISCHARGE PROTECTION ELEMENT - A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event. | 11-13-2008 |
| 20080296686 | CIRCUIT BOARD AND DISPLAY APPARATUS - A circuit board includes a transparent circuit substrate, at least one die and at least one electrostatic discharge (ESD) protection circuit. The transparent circuit substrate has a patterned conducting layer. The die is disposed on the transparent circuit substrate and has at least one input/output (I/O) electrical connecting pad. The ESD protection circuit is disposed on the transparent circuit substrate, and the ESD protection circuit is electrically connected with the I/O electrical connecting pad of the die through the patterned conducting layer. A display apparatus including the circuit board is also disclosed. | 12-04-2008 |
| 20080296687 | FIELD-EFFECT TRANSISTOR (FET) WITH EMBEDDED DIODE - A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions. | 12-04-2008 |
| 20080296688 | ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES - An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to V | 12-04-2008 |
| 20090039431 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in which a gate electrode of the N-type MOS transistor for ESD protection is formed of P-type polysilicon. | 02-12-2009 |
| 20090050969 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element. | 02-26-2009 |
| 20090057768 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - Disclosed is an ESD protection circuit, which includes: an ESD protection element, coupled to a pad; a transmitting gate circuit; an N MOSFET, for providing a first biasing voltage to the transmitting gate circuit according to the second voltage level; a first P MOSFET, for providing a second biasing voltage to the transmitting gate circuit according to the first voltage level; a delay circuit for determining the turning on and turning off time of the transmitting gate circuit; a first inversing logic circuit, for generating a first control signal according to the output of the delay circuit; and a second inversing logic circuit, for generating a second control signal according to the output of the first inversing logic circuit, wherein the transmitting gate circuit turns on or turns off according to the first control signal and the second control signal. | 03-05-2009 |
| 20090085117 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE THEREOF - A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning. | 04-02-2009 |
| 20090152633 | Semiconductor device - In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view. | 06-18-2009 |
| 20090159973 | SEMICONDUCTOR DEVICE HAVING NON-SILICIDE REGION IN WHICH NO SILICIDE IS FORMED ON DIFFUSION LAYER - A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region. | 06-25-2009 |
| 20090230476 | OPTICALLY TRIGGERED ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT - The present invention provides a method and apparatus for providing electrostatic discharge (ESD) protection between a first and a second circuit node. One embodiment of the ESD protection circuit includes one or more steering diodes that generate electromagnetic radiation and couple the first circuit node to ground in response to a voltage applied to the first circuit node. The ESD protection circuit also includes a latch circuit that couples the first circuit node to ground in response to the electromagnetic radiation generated by the steering diode(s). | 09-17-2009 |
| 20090242992 | Inverter, logic circuit including an inverter and methods of fabricating the same - An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer. | 10-01-2009 |
| 20090242993 | ESD protection device and manufacturing method thereof - A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process. | 10-01-2009 |
| 20100013016 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 01-21-2010 |
| 20100181621 | SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE - An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure. | 07-22-2010 |
| 20100193869 | Semiconductor device having electro-static discharge protection element - A semiconductor device includes a semiconductor substrate of a first conductivity-type, a buried diffusion layer of a second conductivity-type formed in the semiconductor substrate, a first well of the second conductivity-type having a bottom portion in contact with a top portion of the buried diffusion layer, the first well having an annular shape in a planar view, and a second well of the first conductivity-type formed to be surrounded by the first well. The semiconductor device further includes a diffusion region formed between a first portion of the second well and a second portion of the second well, the diffusion region having an impurity concentration lower than that of the second well, so that a depletion layer formed in the diffusion region can be provided, a transistor formed on the second well to function as an ESD (electro-static discharge) protection element, and an external terminal connected to a drain of the transistor. | 08-05-2010 |
| 20100200922 | Electrostatic Discharge Protection Device and Method - Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. | 08-12-2010 |
| 20100244137 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced. | 09-30-2010 |
| 20100301418 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - Disclosed is an electrostatic discharge protection device that overcomes problems of an LVTNR device by serially connecting a diode to the LVTNR device and coupling a gate of a MOSFET structure thereto. The electrostatic discharge protection device of the present invention includes a diode comprising N well/P | 12-02-2010 |
| 20110012204 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 01-20-2011 |
| 20110042747 | STRUCTURE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive. | 02-24-2011 |
| 20110089494 | Semiconductor device having fuse and protection circuit - A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse. | 04-21-2011 |
| 20110121394 | CHIP AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE THEREOF - An ESD protection device is provided, which includes a P-type doped region, an N-type doped region, a first P+ doped region, a first N+ doped region, a second N+ doped region and a third N+ doped region. The N-type doped region is located in the P-type doped region. The first P+ doped region connected to a pad is located in the N-type doped region. A part of the first N+ doped region is located in the N-type doped region and the residue part thereof is located in the P-type doped region. The second and the third N+ doped regions are located in the P-type doped region and outside the N-type doped region, and are respectively electrically connected to a first power rail and a second power rail. In addition, the second N+ doped region is located between the first and the third N+ doped regions. | 05-26-2011 |
| 20110204447 | ESD TOLERANT I/O PAD CIRCUIT INCLUDING A SURROUNDING WELL - An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body. | 08-25-2011 |
| 20110215410 | I/O and Power ESD Protection Circuits By Enhancing Substrate-Bias in Deep-Submicron CMOS Process - A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps. | 09-08-2011 |
| 20110266624 | ELECTROSTATIC DISCHARGE PROTECTION HAVING MULTIPLY SEGMENTED DIODES IN PROXIMITY TO TRANSISTOR - An ESD protection device for an I/O pad ( | 11-03-2011 |
| 20120091529 | HIGH VOLTAGE RESISTOR - Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. | 04-19-2012 |
| 20120091530 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology - An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type. | 04-19-2012 |
| 20130187232 | SEMICONDUCTOR DEVICE - In the semiconductor device including an ESD protection N-type MOS transistor having a sufficient ESD protective function, a drain region of the ESD protection N-type MOS transistor is electrically connected to a drain contact region via a drain extended region. The drain extended region is provided on a side surface and a lower surface of an ESD protection trench isolation region, and is formed of an impurity diffusion region of the same conductivity type as that of the drain region. The drain contact region is formed of an impurity diffusion region of the same conductivity type as that of the drain region. | 07-25-2013 |
| 20130207192 | Power Integrated Circuit with Incorporated Sense FET - In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. | 08-15-2013 |
| 20130228868 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES - A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion. | 09-05-2013 |
| 20130234251 | SEMICONDUCTOR INTEGRATED DEVICE - A semiconductor integrated device in which electrostatic discharge damage can be reliably prevented, includes a semiconductor substrate in which an electrostatic protection circuit including a second diffusion region surrounding a first diffusion region as a local region is formed in a main surface; a metal pad opposed to the main surface; and a conductive bump formed so as to face a top surface of the metal pad, wherein in a surface opposed to the metal pad of the conductive bump, a projection which is in contact with the metal pad is provided in a range opposed to the first diffusion region. | 09-12-2013 |
| 20140117452 | SEMICONDUCTOR STRUCTURES WITH THINNED JUNCTIONS AND METHODS OF MANUFACTURE - A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer. | 05-01-2014 |
| 20140367783 | ESD TRANSISTOR AND ESD PROTECT CIRCUIT THEREOF - An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a burier layer protruding horizontally further than the sink region under the sink region. | 12-18-2014 |
| 20160020215 | SEMICONDUCTOR STRUCTURE - Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure. | 01-21-2016 |
| 20160064373 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor. | 03-03-2016 |
| 257361000 | For operation as bipolar or punchthrough element | 4 |
| 20110095368 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge clamping circuit. The first transistor includes a first drain electrically connected to an input/output pin of a chip, a first source electrically connected to a first voltage input pin of the chip, and a first gate. The first drain is preferably an internally shrunk drain. The second transistor includes a second drain electrically connected to the input/output pin of the chip, a second source electrically connected to a second voltage input pin and a second gate. The electrostatic discharge clamping circuit is electrically connected to the first voltage input pin and the second voltage input pin. | 04-28-2011 |
| 20110121395 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device includes protection device includes: a high voltage P well formed in a semiconductor substrate, an N-drift region formed in the high voltage P well, an anode N+ diffusion region and an anode P+ diffusion region formed in the N-drift region, a buffer N+ diffusion region formed in the N-drift region and separated a predetermined distant from the anode N+ diffusion region, a buffer N-ballistic region surrounding the buffer N+ diffusion region, an anode N-ballistic region surrounding the anode N+ diffusion region and the anode P+ diffusion region, a cathode N+ diffusion region and a cathode P+ diffusion region formed in the high voltage P well and separated a predetermined distance from the N-drift region, a MOSFET gate disposed on the semiconductor substrate between the cathode N+ diffusion region and the N-drift region, and a capacitor electrode disposed on the semiconductor substrate between the anode N+ diffusion region and the buffer N+ diffusion region. | 05-26-2011 |
| 20110169093 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE OPERATION - The present disclosure provides ESD protection devices that can effectively cope with electrostatic stress of microchips for high voltage operation. The ESD protection device is a double diffused drain N-type MOSFET (DDDNMOS) ESD protection device, in which a gate, a source region and a well-pickup region are connected to a ground terminal and a drain region is connected to a power terminal or individual input/output terminals. The ESD protection device includes a first conductive type well region formed in a semiconductor substrate, a gate formed to on the semiconductor substrate, a second conductive type source region and a drain region formed in the well region at opposite sides of the gate, a first conductive type well-pickup region formed at one side of the source region, a first conductive type pocket region formed in the well region to surround the source region, a second conductive type drain drift region formed in the well region to surround the drain region, and a first conductive type divot region formed in the drain drift region between a side surface of the gate and the drain region. | 07-14-2011 |
| 20160148925 | SMART SEMICONDUCTOR SWITCH - A semiconductor device may comprise a semiconductor substrate, which is doped with dopants of a first doping type and includes a semiconductor layer adjoining a top surface of the semiconductor substrate, the semiconductor layer being doped with dopants of a second doping type; a MOS transistor being integrated in the first semiconductor region; and a protection circuit electrically connected to a portion of the first semiconductor layer and the gate electrode and being configured to charge the gate electrode dependent on a current passing from the first semiconductor layer to a drain electrode of the MOS transistor. | 05-26-2016 |
