| Entries |
| Document | Title | Date |
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| 20080211024 | Memory Device and Manufacturing Method of the Same - An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film. | 09-04-2008 |
| 20080224217 | MUGFET SWITCH - An electronic circuit on a semiconductor substrate having isolated multiple field effect transistor circuit blocks is disclosed. In some embodiment, an apparatus includes a substrate, a first semiconductor circuit formed above the substrate, a second semiconductor circuit formed above the substrate, and a MuGFET device overlying the substrate and electrically coupled to the first semiconductor circuit and the second semiconductor circuit, wherein the MuGFET device provides a signal path between the first semiconductor circuit and the second semiconductor circuit in response to an input signal. | 09-18-2008 |
| 20080230838 | Semiconductor memory device and manufacturing process therefore - An objective of this invention is to solve the problem caused by a difference in a silicon layer film thickness between a memory cell region and a region other than the memory cell region. | 09-25-2008 |
| 20080258219 | Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer - A semiconductor device is provided which comprises a semiconductor layer ( | 10-23-2008 |
| 20080258220 | ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS - This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. | 10-23-2008 |
| 20080258221 | SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES - A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device. | 10-23-2008 |
| 20080315312 | Semiconductor Devices Having Stacked Structures - A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed. | 12-25-2008 |
| 20090014797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An isolation insulating film ( | 01-15-2009 |
| 20090026542 | INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR ASSEMBLY IN THIN-SOI TECHNOLOGY - An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure. | 01-29-2009 |
| 20090032874 | METHOD FOR INTEGRATING SILICON-ON-NOTHING DEVICES WITH STANDARD CMOS DEVICES - A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit. | 02-05-2009 |
| 20090039430 | Semiconductor apparatus and method for manufacturing the same - The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured by reducing degasification of resist by reducing the area (resist area proportion, that is, the ratio of the area of resist to the whole area of a substrate) of resist pattern which is used depending on the conditions such as acceleration voltage or current density of a doping process. | 02-12-2009 |
| 20090050965 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed sandwiching the channel region and has a function as a source region and a drain region, and formed on a recess in the semiconductor substrate; and a growth suppressing portion formed on the recess in the semiconductor substrate, and configured to suppress an epitaxial growth of a crystal in the epitaxial layer from the semiconductor substrate. | 02-26-2009 |
| 20090127624 | Semiconductor device having soi substrate and method for manufacturing the same - A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region. | 05-21-2009 |
| 20090134461 | METHOD OF MANUFACTURING ELECTRONIC APPARATUS AND ELECTRONIC APPARATUS - A method of manufacturing an electronic apparatus having a resist pattern provided over a substrate provided with a thin film transistor, the method includes the steps of forming by application a resist film over the substrate in the state of covering the thin film transistor, forming a resist pattern by subjecting the resist film to exposure to light and a developing treatment, and irradiating the resist pattern with at least one of ultraviolet light and visible light in a dry atmosphere in the condition where a channel part of the thin film transistor is prevented from being irradiated with light having a wavelength of shorter than 260 nm, wherein a step of heat curing the resist pattern is conducted after the irradiation with at least one of ultraviolet light and visible light. | 05-28-2009 |
| 20090140338 | METHOD OF FABRICATING PATTERNED SOI DEVICES AND THE RESULTING DEVICE STRUCTURES - A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess. | 06-04-2009 |
| 20090146212 | NEGATIVE DIFFERENTIAL RESISTANCE DIODE AND SRAM UTILIZING SUCH DEVICE - A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor. | 06-11-2009 |
| 20090159972 | METHOD OF FABRICATING MULTI-GATE SEMICONDUCTOR DEVICES WITH IMPROVED CARRIER MOBILITY - A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter. | 06-25-2009 |
| 20090230474 | CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD - A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. | 09-17-2009 |
| 20090250758 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, EVALUATION METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width direction); an insulator with a width b formed to be in contact with a side wall of the electrodes and an insulator formed in a region between the electrodes divided into a plurality of parts; a silicide layer formed over part of the surface of the impurity region; and characteristics of the TFT are evaluated by measuring resistance of the semiconductor film of the semiconductor element. | 10-08-2009 |
| 20090256204 | SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR - A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector. | 10-15-2009 |
| 20090256205 | 2-T SRAM CELL STRUCTURE AND METHOD - The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage. | 10-15-2009 |
| 20090278203 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor film with a gate insulating film interposed therebetween, is formed over the semiconductor film. In the semiconductor film, a channel forming region, a first impurity region forming a source or drain region, and a second impurity region are provided. The channel forming region is provided in a region which overlaps with the gate electrode crossing the island-like semiconductor film, the first impurity region is provided so as to be adjacent to the channel forming region, and the second impurity region is provided so as to be adjacent to the channel forming region and the first impurity region. The first impurity region and the second impurity region are provided so as to have different conductivity, and the second impurity region and the channel forming region are made to have different conductivity or to have different concentration of an impurity element contained in the second impurity region and the channel forming region in a case of having the same conductivity. | 11-12-2009 |
| 20090302387 | INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF - An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions. | 12-10-2009 |
| 20090309160 | STRAINED-SILICON-ON-INSULATOR SINGLE-AND DOUBLE-GATE MOSFET AND METHOD FOR FORMING THE SAME - A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate. | 12-17-2009 |
| 20090321832 | Semiconductor Device - A semiconductor device according to this invention is provided with a MOS transistor of at least one type, wherein the MOS transistor has a semiconductor layer (SOI layer) provided on an SOI substrate and a gate electrode provided on the SOI layer and is normally off by setting the thickness of the SOI layer so that the thickness of a depletion layer caused by a work function difference between the gate electrode and the SOI layer becomes greater than that of the SOI layer. | 12-31-2009 |
| 20100001347 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device, comprising: a metal oxide semiconductor field effect transistor (MOSFET) formed on an SOI substrate, the MOSFET including a drain region connected to an input/output terminal, a source region connected to a ground terminal, a body region, a gate electrode above the body region, and a body contact region; and a trigger circuit including a diode array having at least one diode connected in series in the forward direction between the input/output terminal, and the gate electrode and the body contact region of the MOSFET, and a resistance portion connected between the ground terminal, and the gate electrode and the body contact region of the MOSFET. | 01-07-2010 |
| 20100006942 | Interconnection structure and electronic device employing the same - An interconnection structure and an electronic device employing the same are provided. The interconnection structure for an integrated structure includes first and second contact plugs disposed on a substrate, and a connection pattern interposed between sidewalls of the first and second contact plugs and configured to electrically connect the first and second contact plugs. | 01-14-2010 |
| 20100032761 | SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE - A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided. | 02-11-2010 |
| 20100032762 | Stack-Type Semiconductor Device - A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate. | 02-11-2010 |
| 20100044795 | Logic Switch and Circuits Utilizing the Switch - A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described. | 02-25-2010 |
| 20100065911 | SEMICONDUCTOR MEMORY DEVICE - An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. | 03-18-2010 |
| 20100078723 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 04-01-2010 |
| 20100140710 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected. | 06-10-2010 |
| 20100148262 | Resistors and Methods of Manufacture Thereof - Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor. | 06-17-2010 |
| 20100163996 | METHOD FOR MANUFACTURING CMOS CIRCUITS AND CMOS CIRCUITS MANUFACTURED THEREOF - A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer over an entire surface, activating dopants in the semiconductor areas such that a contact area with the first conductivity type is produced in the intrinsic semiconductor layer, depositing a gate dielectric, producing a gate electrode by depositing a first conductive layer and patterning the first conductive layer, performing ion doping with dopants to produce contact areas with a second conductivity type for a second type of transistor, depositing a passivation layer, opening contact openings, and depositing and patterning a second conductive layer. | 07-01-2010 |
| 20100176451 | Semiconductor - A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess. | 07-15-2010 |
| 20100181620 | STRUCTURE AND METHOD FOR FORMING PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE - A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode. | 07-22-2010 |
| 20100200918 | Heavy Ion Upset Hardened Floating Body SRAM Cells - A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed. | 08-12-2010 |
| 20100230756 | SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION - A semiconductor device is provided which comprises a semiconductor layer ( | 09-16-2010 |
| 20100258872 | SEMICONDUCTOR DEVICE - A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface. | 10-14-2010 |
| 20100314685 | CHARGING PROTECTION DEVICE - Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P | 12-16-2010 |
| 20100327357 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers. | 12-30-2010 |
| 20100327358 | SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL - The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material. | 12-30-2010 |
| 20110012202 | Selective Floating Body SRAM Cell - A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. | 01-20-2011 |
| 20110049629 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin. | 03-03-2011 |
| 20110062521 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention comprises a first transistor and a second transistor, and functions as an inverter. The first transistor includes an island semiconductor layer, a first gate insulating film surrounding the periphery of the island semiconductor layer, a gate electrode surrounding the periphery of the first gate insulating film, p+-type semiconductor layers formed in the upper and lower part of the island semiconductor layer, respectively. The second transistor includes the gate electrode, a second gate insulating film surrounding a part of the periphery of the gate electrode, an arcuate semiconductor layer contacting a part of the periphery of the second gate insulating film, n+-type semiconductor layers formed in the upper and lower part of the arcuate semiconductor layer, respectively. A first contact electrically connects the p+-type semiconductor layer in the first transistor and the n+-type semiconductor layer in the second transistor. | 03-17-2011 |
| 20110108919 | METHOD OF FABRICATING A PRECISION BURIED RESISTOR - The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region. | 05-12-2011 |
| 20110115023 | HYBRID FinFET/PLANAR SOI FETs - A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices. | 05-19-2011 |
| 20110133281 | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 06-09-2011 |
| 20110156146 | eFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-STACK FOR HKMG CMOS - An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting. | 06-30-2011 |
| 20110169088 | STRUCTURE AND METHOD HAVING ASYMMETRICAL JUNCTION OR REVERSE HALO PROFILE FOR SEMICONDUCTOR ON INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) - A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided. | 07-14-2011 |
| 20110169089 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME - An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided. | 07-14-2011 |
| 20110169090 | DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BURIED INSULATING LAYER, AND PROCESS FOR FABRICATING SAID DEVICE - The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices. | 07-14-2011 |
| 20110186929 | SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE - In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided. | 08-04-2011 |
| 20110193167 | Self-Aligned Two-Step STI Formation Through Dummy Poly Removal - An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate. | 08-11-2011 |
| 20110193168 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer ( | 08-11-2011 |
| 20110254091 | ESD Protection Structures on SOI Substrates - An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region. | 10-20-2011 |
| 20110260251 | Semiconductor Device and Method of Fabricating Same - A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated. | 10-27-2011 |
| 20110291193 | HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME - A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits. | 12-01-2011 |
| 20110309445 | SEMICONDUCTOR FABRICATION - Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics. | 12-22-2011 |
| 20120007182 | CHARGING PROTECTION DEVICE - Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P | 01-12-2012 |
| 20120032264 | High density semiconductor latch - A novel semiconductor latch is presented. The semiconductor structure is simple and has a reduced number of semiconductor junctions. It offers the advantage of being very small in area, very fast and very efficient. The current conductivity in the structures of the latch circuit is controlled by the gates voltage by means of depleting and enhancing the areas under the gate oxide. The signal isolation is obtained mainly by the carrier depletion of the channel region. By having a reduced number of semiconductor junctions, the intrinsic current leakage can be very small. This latch is the elementary component for volatile memory and logic elements based on this principle. | 02-09-2012 |
| 20120068267 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 03-22-2012 |
| 20120074495 | Series FinFET Implementation Schemes - A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET. | 03-29-2012 |
| 20120098066 | SIMULTANEOUS FORMATION OF FINFET AND MUGFET - A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure. | 04-26-2012 |
| 20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
| 20120119296 | TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES - Trench-generated transistor structures, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of a semiconductor-on-insulator (SOI) wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer. Alternatively, the gate electrode may be defined as a conventional gate stack on a shallow trench isolation region in the semiconductor layer or as a conventional gate stack in one of the BEOL interconnect levels. | 05-17-2012 |
| 20120132992 | SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE - A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided. | 05-31-2012 |
| 20120139049 | Poly Resistor and Metal Gate Fabrication and Structure - A method is provided for fabricating a microelectronic device and a resistor on a substrate. The method can include forming device regions in a monocrystalline semiconductor region of a substrate, in which the device regions have edges defined according to a first semiconductor feature overlying a major surface of the semiconductor region. A dielectric region is formed having a planarized surface overlying the semiconductor region and overlying a second semiconductor feature disposed above a surface of an isolation region in the substrate. The surface of the isolation region can be disposed below the major surface. The method can further include removing at least a portion of the first semiconductor feature exposed at the planarized surface of the dielectric region to form an opening and forming a gate at least partially within the opening. Thereafter, further processing can include forming electrically conductive contacts extending through apertures in the dielectric region to the second semiconductor feature and the device regions, respectively. The step of forming electrically conductive contacts may include forming silicide regions contacting portions of the second semiconductor feature and the device regions, respectively. In such way, the method can define a resistor having a current path through the second semiconductor feature, and a microelectronic device including the gate and the device regions. | 06-07-2012 |
| 20120153396 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device including a switch circuit includes a first gate electrode provided between a source region and a drain region of an FET and a second gate electrode provided between the first gate electrode and the drain region. The semiconductor device also includes a control terminal electrically connected to an intermediate region between the first gate electrode and the second gate electrode, the control terminal being placed at a ground potential corresponding to ON state of the FET, and the control terminal being placed at a positive potential or a negative potential corresponding to OFF state of the FET. | 06-21-2012 |
| 20120187492 | BULK SUBSTRATE FET INTEGRATED ON CMOS SOI - An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET. | 07-26-2012 |
| 20120187493 | EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME - An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided. | 07-26-2012 |
| 20120235239 | HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined. | 09-20-2012 |
| 20120261756 | INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES - Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate. | 10-18-2012 |
| 20130009246 | BULK FINFET WITH UNIFORM HEIGHT AND BOTTOM ISOLATION - A fin Field Effect Transistor (finFET), an array of finFETs, and methods of production thereof. The finFETs are provided on an insulating region, which may optionally contain dopants. Further, the finFETs are optionally capped with a pad. The finFETs provided in an array are of uniform height. | 01-10-2013 |
| 20130009247 | Method for Manufacturing Semiconductor Device - It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions. | 01-10-2013 |
| 20130087855 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane. | 04-11-2013 |
| 20130134518 | NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas. | 05-30-2013 |
| 20130175627 | SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION - SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material. | 07-11-2013 |
| 20130193515 | SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS - An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor. | 08-01-2013 |
| 20130221441 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 08-29-2013 |
| 20130249004 | Same-Chip Multicharacteristic Semiconductor Structures - In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth. | 09-26-2013 |
| 20130256800 | SOI DEVICES FOR PLASMA DISPLAY PANEL DRIVER CHIP - SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer. | 10-03-2013 |
| 20130264644 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer. | 10-10-2013 |
| 20130299908 | SIMULTANEOUS FORMATION OF FINFET AND MUGFET - A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure positioned on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure positioned on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. | 11-14-2013 |
| 20130307076 | METHOD AND STRUCTURE FOR FORMING FIN RESISTORS - A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits. | 11-21-2013 |
| 20130307077 | STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION - A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut. | 11-21-2013 |
| 20130334604 | SOI SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE DIODE AND A FILM DIODE FORMED BY USING A COMMON WELL IMPLANTATION MASK - When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer. | 12-19-2013 |
| 20140015053 | SELF-PROTECTED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor. | 01-16-2014 |
| 20140124863 | METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET - Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed. | 05-08-2014 |
| 20140131802 | Structure and Method to Form Passive Devices in ETSOI Process Flow - Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon. | 05-15-2014 |
| 20140167166 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate. | 06-19-2014 |
| 20140167167 | CMOS CELL PRODUCED IN FD-SOI TECHNOLOGY - An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage. | 06-19-2014 |
| 20140183638 | METHODS OF USING A TRENCH SALICIDE ROUTING LAYER - Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure. | 07-03-2014 |
| 20140210006 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY DEVICE - Embodiments of the invention provide an array substrate and a fabrication method thereof, and a liquid crystal display device. The array substrate comprises: a gate line, a data line, and a pixel unit formed by the gate line and the data line intersecting with each other. A first thin-film transistor and a pixel electrode are formed in the pixel unit, and the pixel electrode has slits. The pixel unit further comprises a second thin-film transistor, a first common electrode and a second common electrode, and the second thin-film transistor is configured to turn on and transmit a signal of the first common electrode to the second common electrode when a data line signal is at a high level. | 07-31-2014 |
| 20140210007 | ESD-Protection Circuit for Integrated Circuit Device - A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections. | 07-31-2014 |
| 20140217506 | Diode Structure and Method for FINFET Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device. | 08-07-2014 |
| 20140217507 | Diode Structure and Method for Gate All Around Silicon Nanowire Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration. | 08-07-2014 |
| 20140217508 | Diode Structure and Method for FINFET Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device. | 08-07-2014 |
| 20140217509 | Diode Structure and Method for Gate All Around Silicon Nanowire Technologies - A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration. | 08-07-2014 |
| 20140264606 | PIXEL STRUCTURE - A pixel structure includes a flexible substrate, an active device, a conductive pattern, a first insulation layer, and a pixel electrode. The active device is disposed on the flexible substrate and includes a gate, a channel, a source, and a drain. The source and the drain are connected to the channel and are separated from each other. The channel and the gate are stacked in a thickness direction. The active device is disposed between the conductive pattern and the flexible substrate. The conductive pattern is electrically connected to the drain of the active device. The first insulation layer covers the conductive pattern and has first contact holes separated from one another, and the first contact holes expose the conductive pattern. The first insulation layer is disposed between the pixel electrode and the conductive pattern. The pixel electrode is electrically connected to the conductive pattern through the first contact holes. | 09-18-2014 |
| 20140346603 | TRANSISTOR DEVICES HAVING AN ANTI-FUSE CONFIGURATION AND METHODS OF FORMING THE SAME - Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer. | 11-27-2014 |
| 20140367781 | LATERAL DIODE COMPATIBLE WITH FINFET AND METHOD TO FABRICATE SAME - A method to fabricate a diode device includes providing a fin structure formed in a SOI layer. The fin structure has a sacrificial gate structure disposed on the fin structure between a first end of the fin structure and a second end of the fin structure. The method further includes depositing first doped semiconductor material on the first and second ends of the fin structure, where the first doped semiconductor material on the first end of the fin structure has one of the same doping polarity or an opposite doping polarity as the first doped semiconductor material on the second end of the fin structure. The method further includes removing the sacrificial gate structure to form a gap between the deposited first doped semiconductor material; depositing a second doped semiconductor material within the gap and forming first and second electrical contacts conductively connected to the first doped semiconductor material. | 12-18-2014 |
| 20140367782 | Lateral Diode Compatible with FinFET and Method to Fabricate Same - A structure includes a fin having first end and second ends and a substantially intrinsic portion between the first and second ends. The structure further includes a first region of doped semiconductor material disposed on the first end of the fin and a second region of doped semiconductor material disposed on the second end of the fin. The first region has one of the same doping polarity or an opposite doping polarity as the second region. The structure also includes a third region of doped semiconductor material disposed on the intermediate portion of the fin adjacent to the first region and the second region. The third region has a doping polarity that differs from the doping polarity of at least one of the first and second regions and forms a p-n junction with the at least one of the first and second regions. | 12-18-2014 |
| 20150054081 | EPITAXIAL SEMICONDUCTOR RESISTOR WITH SEMICONDUCTOR STRUCTURES ON SAME SUBSTRATE - An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material. | 02-26-2015 |
| 20150054082 | SEMICONDUCTOR STRUCTURE WITH DEEP TRENCH THERMAL CONDUCTION - Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches. | 02-26-2015 |
| 20150069514 | Millimetre wave integrated circuits with thin film transistors - MMIC circuits with thin film transistors are provided without the need of grinding and etching of the substrate after the fabrication of active and passive components. Furthermore, technology for active devices based on non-toxic compound semiconductors is provided. The success in the MMIC methods and structures without substrate grinding/etching and the use of semiconductors without toxic elements for active components will reduce manufacturing time, decrease economic cost and environmental burden. MMIC structures are provided where the requirements for die or chip attachment, alignment and wire bonding are eliminated completely or minimized. This will increase the reproducibility and reduce the manufacturing time for the MMIC circuits and modules. | 03-12-2015 |
| 20150091090 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer. | 04-02-2015 |
| 20150097243 | SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY - A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer. | 04-09-2015 |
| 20150115365 | CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS - Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed. | 04-30-2015 |
| 20150129967 | DUAL GATE FD-SOI TRANSISTOR - Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module. | 05-14-2015 |
| 20150137246 | Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed - Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOT”) and Silicon-On-Sapphire (“SOS”) substrates. | 05-21-2015 |
| 20150145047 | IMPLEMENTING BURIED FET UTILIZING DRAIN OF FINFET AS GATE OF BURIED FET - A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer. | 05-28-2015 |
| 20150318303 | FIELD EFFECT TRANSISTORS INCLUDING CONTOURED CHANNELS AND PLANAR CHANNELS - Disposable gate structures and a planarization dielectric layer are formed over doped semiconductor material portions on a crystalline insulator layer. Gate cavities are formed by removing the disposable gate structures selective to the planarization dielectric layer. Doped semiconductor material portions are removed from underneath the gate cavities to provide pairs of source and drain regions separated by a gate cavity. Within a first gate cavity, a faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer, while a second gate is temporarily coated with an amorphous material layer. A contoured semiconductor region is epitaxially grown on the faceted crystalline dielectric material portion in the first gate cavity, while a planar semiconductor region is epitaxially grown in the second gate cavity. The semiconductor regions can provide at least one contoured channel region and at least one planar channel region. | 11-05-2015 |
| 20150325590 | HIGH-FREQUENCY DEVICE INCLUDING HIGH-FREQUENCY SWITCHING CIRCUIT - A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate. | 11-12-2015 |
| 20150325647 | INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs on ICs. FET locations are defined on a layered semiconductor wafer, preferably a Silicon On Insulator (SOI) wafer. One or more FET locations are defined as silicon gate locations and remaining as Replacement Metal Gate (RMG) FET locations with at least one of each on the IC. Polysilicon gates are formed in all FET locations. Gates in silicon gate locations are tailored, e.g., doped and silicided. Remaining polysilicon gates are replaced with metal in RMG FET locations. FETs are connected together into circuits with RMG FETs being connected to silicon gate FETs. | 11-12-2015 |
| 20150348959 | PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES - Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors. | 12-03-2015 |
| 20150349120 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion. | 12-03-2015 |
| 20150380438 | TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation. | 12-31-2015 |
| 20160013207 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME | 01-14-2016 |
| 20160035762 | Methods for Manufacturing RFID Tags and Structures Formed Therefrom - Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices. | 02-04-2016 |
| 20160056152 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE - One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening. | 02-25-2016 |
| 20160064416 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane. | 03-03-2016 |
| 20160064417 | BULK AND DIELECTRIC-ISOLATED FINFET-BASED INTEGRATED CIRCUIT - A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed. | 03-03-2016 |
| 20160086975 | SCHOTTKY CLAMPED RADIO FREQUENCY SWITCH - Various methods and devices that involve radio frequency (RF) switches with clamped bodies are provided. An exemplary RF switch with a clamped body comprises a channel that separates a source and a drain. The RF switch also comprises a clamp region that spans the channel, extends into the source and drain, and has a lower dopant concentration than both the source and drain. The RF switch also comprises a pair of matching silicide regions formed on either side of the channel and in contact with the clamp region. The clamp region forms a pair of Schottky diode barriers with the pair of matching silicide regions. The RF switch can operate in a plurality of operating modes. The pair of Schottky diode barriers provide a constant sink for accumulated charge in the clamped body that is independent of the operating mode in which the RF switch is operating. | 03-24-2016 |
| 20160099251 | SEMICONDUCTOR DEVICE - An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element. | 04-07-2016 |
| 20160118406 | Semiconductor Structure with Active Device and Damaged Region - A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device. | 04-28-2016 |
| 20160155758 | SEMICONDUCTOR DEVICE WITH THREE OR FOUR-TERMINAL-FINFET | 06-02-2016 |
| 20170236898 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES | 08-17-2017 |
