With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257213000 - FIELD EFFECT DEVICE

257288000 - Having insulated electrode (e.g., MOSFET, MOS diode)

257314000 - Variable threshold (e.g., floating gate memory device)

257315000 - With floating gate electrode

257316000 - With additional contacted control electrode

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application number	Description	Number of patent applications / Date published
257322000	With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction)	6
20080211010	Semiconductor device - A semiconductor device includes: a package; two semiconductor chip fixing parts located adjacently to each other in the package; and first and the second semiconductor chips, each of which is fixed on the semiconductor chip fixing part and has a field effect transistor formed therein. A gate lead G	09-04-2008
20090101962	Semiconductor devices and methods of manufacturing and operating same - A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.	04-23-2009
20090194806	SINGLE POLY TYPE EEPROM AND METHOD FOR MANUFACTURING THE EEPROM - Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having an activation region and a device isolation area, not overlapping a device isolation region but overlapping only a top of the activation region. A select gate may be formed on and/or over a top of the activation region. According to embodiments, a ratio of a capacitance of a control node side to a capacitance of a bit line side may increase, which may improve a coupling ratio. According to embodiments, a junction capacitance may be maximized by not doping the floating gate with an impurity, which may allow for a reduction in chip size by securing design margins.	08-06-2009
20160013197	SALICIDED STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE	01-14-2016
20160013198	RECESSED SALICIDE STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE	01-14-2016
20160035736	High Endurance Non-Volatile Memory Cell - The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.	02-04-2016