| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257307000 | Parallel interleaved capacitor electrode pairs (e.g., interdigitized) | 10 |
| 20080197399 | Nanotip capacitor - A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips. | 08-21-2008 |
| 20080224198 | APPARATUS FOR WORKING AND OBSERVING SAMPLES AND METHOD OF WORKING AND OBSERVING CROSS SECTIONS - The apparatus for working and observing samples comprises a sample plate on which a sample is to be placed; a first ion beam lens barrel capable of irradiating a first ion beam over a whole predetermined irradiation range at one time; a mask that can be arranged between the sample plate and the first ion beam lens barrel, and shields part of the first ion beam; mask-moving means capable of moving the mask; a charged particle beam lens barrel capable of scanning a focused beam of charged particles in the range irradiated with the first ion beam; and detection means capable of detecting a secondarily generated substance. | 09-18-2008 |
| 20090236649 | EMBEDDED MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory. | 09-24-2009 |
| 20100078700 | Semiconductor Memory Device - To realize a semiconductor memory device whose capacitance value per unit area in a memory cell is increased without increase in the area of the memory cell. The memory cell includes a transistor, a memory element, a first capacitor, and a second capacitor. The first capacitor includes a semiconductor film, a gate insulating film, and a gate electrode which are included in the transistor and is formed at the same time as the transistor. The second capacitor includes an electrode which is included in the memory element and an insulating film and an electrode which are formed over the electrode. Further, the second capacitor is formed over the first capacitor. In this manner, the first capacitor and the second capacitor which are connected in parallel with the memory element are formed. | 04-01-2010 |
| 20110260231 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a memory device and a method for manufacturing the same. The memory device comprising an MOSFET formed in a semiconductor layer and a capacitor structure below the MOSFET, wherein the capacitor structure comprises two capacitor electrodes, and one of a source region and a drain region of the MOSFET is electrically connected to one of the two capacitor electrodes, wherein the capacitor structure comprises a plurality of first sub-capacitors and a plurality of second sub-capacitors which are stacked in an alternate manner, each of the plurality of the first sub-capacitors and the plurality of the second sub-capacitors comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween, and the plurality of the first sub-capacitors and the plurality of the second sub-capacitors are connected in parallel with the two capacitor electrodes, and wherein each of the first sub-capacitors has a bottom capacitor plate which is formed from a common first electrode layer with a top capacitor plate of an underlying second sub-capacitor, and each of the second sub-capacitors has a bottom capacitor plate which is formed from a common second electrode layer with a top capacitor plate of an underlying first sub-capacitor, and wherein the first electrode layer and the second electrode layer are made of different conductive materials. | 10-27-2011 |
| 20190142294 | REDUCING NOISE LEVELS ASSOCIATED WITH SENSED ECG SIGNALS | 05-16-2019 |
| 257308000 | With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) | 4 |
| 20080315275 | Capacitor pair structure for increasing the match thereof - A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers. | 12-25-2008 |
| 20080315276 | Capacitor pair structure for increasing the match thereof - A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers. | 12-25-2008 |
| 20090032857 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers ( | 02-05-2009 |
| 20090096002 | System and Method for Source/Drain Contact Processing - System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin. | 04-16-2009 |
