| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257302000 | Vertical transistor | 41 |
| 20080197396 | Gate metal routing for transistor with checkerboarded layout - In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 08-21-2008 |
| 20080197397 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 08-21-2008 |
| 20080230822 | VERTICAL TRENCH MEMORY CELL WITH INSULATING RING - A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing outdiffusions from the trench memory cells. | 09-25-2008 |
| 20080290389 | DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a portion of which is disposed on the substrate. The deep trench capacitor is disposed in the deep trench, and comprises a bottom electrode, a capacitor dielectric layer and a top electrode. The vertical transistor comprises a gate structure disposed in the trench and above the substrate, a first doped region disposed in the substrate on sidewalls and bottom of the trench, and a second doped region disposed in the substrate on top of the trench. The buried strap is disposed in the substrate below the vertical transistor, and is adjoined to the first doped region and the top electrode. | 11-27-2008 |
| 20090008692 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness. | 01-08-2009 |
| 20090032856 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided. | 02-05-2009 |
| 20090096000 | DRAM CELLS WITH VERTICAL TRANSISTORS - The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures. | 04-16-2009 |
| 20090173981 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device has a first laminated portion including first insulating layers and first conductive layers laminated alternately, and a second laminated portion provided on an upper surface of the first laminated portion and including a second conductive layer formed between second insulating layers. The first laminated portion has a first semiconductor layer formed so as to contact with a gate insulating film and extend in a laminated direction. The second laminated portion has a second semiconductor layer formed so as to contact with a third insulating layer and the first semiconductor layer and extend in the laminated direction. The first semiconductor layer is of a first conductive type, and a portion of the second semiconductor layer which contacts with the side surface of the second conductive layer is of a second conductive type. | 07-09-2009 |
| 20090267126 | RECESS CHANNEL TRANSISTOR - A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction. | 10-29-2009 |
| 20090321805 | INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE - One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed. | 12-31-2009 |
| 20100117132 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor. | 05-13-2010 |
| 20100163949 | VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA - A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. | 07-01-2010 |
| 20100163950 | Power Device with Monolithically Integrated RC Snubber - A semiconductor structure includes a power transistor monolithically integrated with a RC snubber in a die. The power transistor includes body regions extending in a silicon region, gate electrodes insulated from the body region by a gate dielectric, source regions extending in the body regions, the source and the body regions being of opposite conductivity type, and a source interconnect contacting the source regions. The RC snubber comprises including snubber electrodes insulated from the silicon region by a snubber dielectric such that the snubber electrodes and the silicon region form a snubber capacitor having a predetermined value. The snubber electrodes are connected to the source interconnect in a manner so as to form a snubber resistor of a predetermined value between the snubber capacitor and the source interconnect. The snubber capacitor and the snubber resistor are configured to substantially dampen output ringing when the power transistor switches states. | 07-01-2010 |
| 20100264478 | METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE - A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material. | 10-21-2010 |
| 20100276741 | INTEGRATED CIRCUIT WITH BURIED DIGIT LINE - A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess. | 11-04-2010 |
| 20110024815 | SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor apparatus including a buried gate removes factors deteriorating the operational reliability of the semiconductor device such as the electrical connection between a contact and a word line, and increases a processing margin when forming the contact disposed on a source/drain region. The method includes forming a recess in a semiconductor substrate, forming a gate in a lower portion of the recess, forming a first insulation layer over the gate, growing silicon over the first insulation layer in the recess, and depositing a second insulation layer over the semiconductor substrate and in the remaining portion of the recess. | 02-03-2011 |
| 20110037111 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove. | 02-17-2011 |
| 20110049599 | SEMICONDUCTOR DEVICE - In Trench-Gate Fin-FET, in order that the advantage which is exerted in Fin-FET can be sufficiently taken even if a transistor becomes finer and, at the same time, decreasing of on-current can be suppressed by saving a sufficiently large contact area in the active region, a fin width | 03-03-2011 |
| 20110068384 | Semiconductor Device Comprising Buried Word Lines - A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction. | 03-24-2011 |
| 20110089476 | Checkerboarded high-voltage vertical transistor layout - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 04-21-2011 |
| 20110220980 | MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME - A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F | 09-15-2011 |
| 20110241093 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously. | 10-06-2011 |
| 20110260229 | SEMICONDUCTOR DEVICE HAVING VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars. | 10-27-2011 |
| 20120012912 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current. | 01-19-2012 |
| 20120012913 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line. | 01-19-2012 |
| 20120292681 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a groove in a periphery, a gate electrode partially embedded in the groove to sandwich the substrate from opposite directions by side walls of the groove, and a diffusion layer formed over the substrate and surrounded by the gate electrode. A resistance value of the diffusion layer is changed by changing a potential between the gate electrode and the diffusion layer. | 11-22-2012 |
| 20120299075 | SOI Trench Dram Structure With Backside Strap - In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion. | 11-29-2012 |
| 20130015515 | FET eDRAM TRENCH SELF-ALIGNED TO BURIED STRAPAANM Anderson; Brent A.AACI JerichoAAST VTAACO USAAGP Anderson; Brent A. Jericho VT USAANM Barth, JR.; John E.AACI WillistonAAST VTAACO USAAGP Barth, JR.; John E. Williston VT USAANM Nowak; Edward J.AACI Essex JunctionAAST VTAACO USAAGP Nowak; Edward J. Essex Junction VT USAANM Rankin; Jed H.AACI RichmondAAST VTAACO USAAGP Rankin; Jed H. Richmond VT US - A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array. | 01-17-2013 |
| 20130062678 | Recessed Access Device for a Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 03-14-2013 |
| 20130075801 | SELF-ADJUSTED CAPACITIVE STRUCTURE - A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer. | 03-28-2013 |
| 20130126956 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line, | 05-23-2013 |
| 20130146958 | METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF - A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines. | 06-13-2013 |
| 20130181272 | IC DIE, SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD AND IC DIE MANUFACTURING METHOD - In an example embodiment, an integrated circuit (IC) comprises a substrate separating one of a source and drain from a semiconductor region. The IC comprises a vertical transistor including the source or drain. A gate electrode is formed in a trench extending into the semiconductor region; the gate electrode is electrically insulated from the semiconductor region by a dielectric lining in the trench and the other of said source or drain in the semiconducting region. An insulating trench terminates the vertical transistor; a vertical capacitor region (V-Cap) is adjacent to the vertical transistor; a first capacitor plate of the V-Cap comprises the source or drain separated from the semiconductor region by the substrate; the V-Cap further comprises at least one trench extending into the semiconductor region; the at least one trench comprises an electrically insulating liner material insulating a conductive material defining a second capacitor plate separated from the first capacitor plate. | 07-18-2013 |
| 20130193502 | MEDIUM VOLTAGE MOSFET DEVICE - A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches. | 08-01-2013 |
| 20130248958 | MEMORY WITH ISOLATION STRUCTURE - A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell. | 09-26-2013 |
| 20140035018 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL TRANSISTORS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region. | 02-06-2014 |
| 20140061745 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium. | 03-06-2014 |
| 20140077284 | SEMICONDUCTOR DEVICE - In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film. | 03-20-2014 |
| 20150008498 | Semiconductor Component Arrangement Comprising a Trench Transistor - A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps. | 01-08-2015 |
| 20150028408 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion. | 01-29-2015 |
| 20150348977 | VERTICALLY INTEGRATED MEMORY CELL - A vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor. | 12-03-2015 |
