| Entries |
| Document | Title | Date |
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| 20080197385 | INSULATED GATE FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME, AND IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SAME - An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor having a gate electrode on a semiconductor substrate with a gate insulating film interposed between the semiconductor substrate and the gate electrode, and having a source region and a drain region formed in the semiconductor substrate on both sides of the gate electrode, the insulated gate field effect transistor including: a first diffusion layer of a P type formed in the semiconductor substrate at a position deeper than the source region and the drain region; and a second diffusion layer of the P type having a higher concentration than the first diffusion layer and formed in the semiconductor substrate at a position deeper than the first diffusion layer. | 08-21-2008 |
| 20080203450 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE PICKUP SYSTEM USING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved. | 08-28-2008 |
| 20080217666 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A floating node structure of a CMOS image sensor disposed in a floating node region defined by an isolation structure of a substrate is described. The floating node structure comprises an n-doped region within the floating node region, a p-well surrounding the periphery and the bottom of the n-doped region in the substrate within the folating node region, a surface passivation layer disposed at least on the surface of the p-well, and a contact plug coupling the n-doped region to a source follower transistor of the CMOS image sensor. | 09-11-2008 |
| 20080237664 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - Provided are a semiconductor device and a method of driving the semiconductor device. The semiconductor device includes an optical reaction transistor. The optical reaction transistor includes a semiconductor substrate, a tunnel insulation layer formed on the semiconductor substrate, an optical reaction layer formed on the tunnel insulation layer, a blocking insulation layer formed on the optical reaction layer, and a gate electrode formed on the blocking insulation layer. | 10-02-2008 |
| 20080237665 | Semiconductor device and electronic device - The present invention relates to a semiconductor device which includes a photoelectric conversion layer; an amplifier circuit amplifying an output current of the photoelectric conversion layer and including two thin film transistors; a first terminal supplying a high-potential power supply voltage; a second terminal supplying a low-potential power supply voltage; an electrode electrically connecting the two thin film transistors and the photoelectric conversion layer; a first wiring electrically connecting the first terminal and a first thin film transistor which is one of the two thin film transistors; and a second wiring electrically connecting the second terminal and a second thin film transistor which is the other of the two thin film transistors. In the semiconductor device, the value of voltage drop of the first wiring and the second wiring are increased by bending the first wiring and the second wiring. | 10-02-2008 |
| 20080237666 | Solid-state imaging element and method for producing the same - There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor. | 10-02-2008 |
| 20080246063 | PHOTODIODE WITH MULTI-EPI FILMS FOR IMAGE SENSOR - The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate; a first epitaxy semiconductor layer disposed on the semiconductor substrate and having a first type of dopant and a first doping concentration; a second epitaxy semiconductor layer disposed over the first epitaxy semiconductor layer and having the first type of dopant and a second doping concentration less than the first doping concentration; and an image sensor on the second epitaxy semiconductor layer. | 10-09-2008 |
| 20080272413 | Light-Sensitive Component - In order to detect light with in particular a high blue component, the inversion zone and the space charge zone of a CMOS-like structure are used. In conjunction with an at least partly transparent gate electrode, in particular a transparent conductive oxide or a patterned gate electrode, it becomes possible to absorb the short-wave component of incident light within the inversion zone and to reliably conduct away the generated charge carrier pairs to first and second contacts. During operation, a control voltage is applied to the gate electrode with a magnitude that generates a continuous inversion zone below the optionally patterned gate electrode. | 11-06-2008 |
| 20080308851 | Photoelectric conversion element having a semiconductor and semiconductor device using the same - A semiconductor device, particularly, a photoelectric conversion element having a semiconductor layer is demonstrated. The photoelectric conversion element of the present invention comprises, over a substrate, a photoelectric conversion layer and first and second electrodes which are electrically connected to the photoelectric conversion layer. The photoelectric conversion element further comprises a wiring board over which a third and fourth electrodes are provided. The characteristic point of the present invention is that a bonding layer, which readily forms an alloy with a conductive material, is formed over the first and second electrodes. This bonding layer improves the bonding strength between the first and third electrodes and the second and fourth electrode, which contributes to the prevention of the connection defect between the substrate and the wiring board and consequentially to high reliability of the photoelectric conversion element. | 12-18-2008 |
| 20090078972 | SENSOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE HAVING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A sensor thin film transistor includes a gate electrode, a gate insulation layer formed on the gate electrode, a semiconductor layer having a portion positioned above the gate electrode and on a side of the gate insulation layer opposite the gate electrode, and a source electrode and drain electrode having spaced apart ends positioned on the semiconductor layer, wherein the sensor thin film transistor is operative such that a signal-to-noise ratio is equal to or greater than about 200 when the gate-off voltage applied to the gate electrode is equal to or less than about 0V. | 03-26-2009 |
| 20090101946 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CIS and a method for manufacturing the same are provided. The CIS includes an interlayer insulation layer formed on a substrate having a photodiode and a transistor formed thereon; a plurality of color filters formed on the interlayer insulation layer and spaced a predetermined interval apart from each other; a metal sidewall formed to fill the predetermined interval between the plurality of the color filters; and a microlens formed on each of the plurality of color filters. | 04-23-2009 |
| 20090146195 | Noise reduction in active pixel sensor arrays - A system for detecting high speed noise in active pixel sensors includes a photodiode for receiving low levels of light, a reset transistor, an amplifier transistor, a row select transistor, and a high-speed analog-to-digital converter. The reset transistor gate receives a reset signal, and the reset transistor drain receives a reset voltage. The amplifier transistor gate is connected to the photodiode and the reset transistor's source. The amplifier transistor receives a supply voltage at the drain terminal. The row select transistor gate terminal receives a row select signal. The row select drain terminal is connected to the amplifier transistor source terminal. The high-speed analog-to-digital converter includes an analog input port connected to the row select transistor source and a digital output port capable of resolving high-speed excitation events received by the photodiode. | 06-11-2009 |
| 20090166687 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same may include a gate on a semiconductor substrate, a photodiode on the semiconductor substrate at a first side of the gate, a floating diffusion region on the semiconductor substrate at a second side of the gate, in which the second side is opposite to the first side, a channel under the gate, the channel connecting the photodiode with the floating diffusion region, and a barrier region under the photodiode. | 07-02-2009 |
| 20090179237 | CMOS image sensor and method for fabricating the same - CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in the semiconductor substrate of the device isolation region, a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film, and a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film, thereby reducing generation of a darkcurrent at an interface between the photodiode region and a field region. | 07-16-2009 |
| 20090256179 | IMAGE SENSOR - Embodiments relate to and image sensor. In embodiments, the image sensor may include a semiconductor substrate, a photodiode region, a gate electrode, a dummy gate, and an interlayer dielectric layer. The semiconductor substrate includes a field oxide layer. The photodiode region may be formed on the semiconductor substrate. The gate electrode may be formed on the semiconductor substrate. The dummy gate may be formed on the field oxide layer. The interlayer dielectric layer may be formed on one side of the dummy gate and includes an opening exposing the photodiode region. | 10-15-2009 |
| 20090261392 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME AND ELECTRONIC APPARATUS - A solid-state imaging device is provided. The solid-state imaging device includes a pixel section, a peripheral circuit section, a silicide blocking layer formed in the pixel section except for part or whole of an area above an isolation portion in the pixel section, and a metal-silicided transistor formed in the peripheral circuit section. | 10-22-2009 |
| 20090278180 | CMOS IMAGE SENSOR WITH ASYMMETRIC WELL STRUCTURE OF SOURCE FOLLOWER - Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged. | 11-12-2009 |
| 20090321798 | CMOS Image Sensor and Method of Manufacturing the Same - Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process. | 12-31-2009 |
| 20100019293 | PIN PHOTODIODE AND MANUFACTURING METHOD OF SAME - The objective of this invention is to provide a semiconductor device containing a photodiode and having stable, high sensitivity with respect to short wavelength light near 405 nm, and a manufacturing method for said semiconductor device. PIN photodiode ( | 01-28-2010 |
| 20100096674 | METHODS AND SYSTEMS OF THICK SEMICONDUCTOR DRIFT DETECTOR FABRICATION - Gray-tone lithography technology is used in combination with a reactive plasma etching operation in the fabrication method and system of a thick semiconductor drift detector. The thick semiconductor drift detector is based on a trench array, where the trenches in the trench array penetrate the bulk with different depths. These trenches form an electrode. By applying different electric potentials to the trenches in the trench array, the silicon between neighboring trenches fully depletes. Furthermore, the applied potentials cause a drifting field for generated charge carriers, which are directed towards a collecting electrode. | 04-22-2010 |
| 20100109059 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE PICKUP DEVICE USING THE SAME - Disclosed herein is a semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region. | 05-06-2010 |
| 20100148230 | TRENCH ISOLATION REGIONS IN IMAGE SENSORS - Trenches are formed in a substrate or layer and a solid source doped with one or more dopants is deposited over the image sensor such that the solid source fills the one or more trenches and is disposed on the surface of the substrate. The surface of the image sensor is then planarized so that the solid source remains only in the trenches. A thermal drive operation is performed to cause at least a portion of the one or more dopants in the solid source to diffuse into the portions of the substrate or layer that are immediately adjacent to and surround the sidewall and bottom surfaces of the trenches. The diffused dopant or dopants form passivation regions that passivate the interface between the substrate or layer and the sidewall and bottom surfaces of the trenches. | 06-17-2010 |
| 20100224917 | Solid-state image pickup apparatus and method of manufacturing the same - Disclosed is a solid-state image pickup apparatus including a semiconductor substrate, a photoelectric converter, a transfer gate, an insulating layer, a first silicon layer, and a pixel transistor portion. The photoelectric converter converts light energy of incident light into electrical energy and obtains a signal charge. The photoelectric converter is formed on a surface side in the semiconductor substrate. The transfer gate reads the signal charge from the photoelectric converter, and the transfer gate is formed on the semiconductor substrate adjacent to the photoelectric converter. The insulating layer is formed on the photoelectric converter in the semiconductor substrate. The first silicon layer is formed on the insulating layer. The pixel transistor portion amplifies and outputs the signal charge read by the transfer gate. The pixel transistor portion is formed on the insulating layer with the first silicon layer being an active region. | 09-09-2010 |
| 20100237392 | DEPFET TRANSISTOR HAVING A LARGE DYNAMIC RANGE - The invention relates to a DEPFET transistor ( | 09-23-2010 |
| 20100276735 | SEMICONDUCTOR DEVICE WITH PHOTONICS - A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer. | 11-04-2010 |
| 20100295107 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME AND ELECTRONIC APPARATUS - A solid-state imaging device is provided. The solid-state imaging device includes a pixel section, a peripheral circuit section, a silicide blocking layer formed in the pixel section except for part or whole of an area above an isolation portion in the pixel section, and a metal-silicided transistor formed in the peripheral circuit section. | 11-25-2010 |
| 20110001173 | Monolithically Integrated Antenna and Receiver Circuit for the Detection of Terahertz Waves - The present invention relates to a device for detecting millimeter waves, having at least one field effect transistor with a source, a drain, a gate, a gate-source contact, a source-drain channel, and a gate-drain contact. Compared to a similar such device, the problem addressed by the present invention, among others, is that of providing a device which enables the provision of a field effect transistor for detecting the power and/or phase of electromagnetic radiation in the Thz frequency range. In order to create such a device, it is suggested according to the invention, that a device be provided which has an antenna structure wherein the field effect transistor is connected to the antenna structure in such a manner that an electromagnetic signal received by the antenna structure in the THz range is fed into the field effect transistor via the gate-source contact, and wherein the field effect transistor and the antenna structure are arranged together on a single substrate. | 01-06-2011 |
| 20110049588 | Semiconductor Device and Manufacturing Method Thereof - An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion element with excellent characteristics. An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion device with excellent characteristic through a simple process. A semiconductor device is provided, which includes a light-transmitting substrate; an insulating layer over the light-transmitting substrate; and a photoelectric conversion element over the insulating layer. The photoelectric conversion element includes a single crystal semiconductor layer including a semiconductor region having an effect of photoelectric conversion, a semiconductor region having a first conductivity type, and a semiconductor region having a second conductivity type; a first electrode electrically connected to the semiconductor region having the first conductivity type; and a second electrode electrically connected to the semiconductor region having the second conductivity type. | 03-03-2011 |
| 20110057238 | CMOS PIXEL SENSOR WITH DEPLETED PHOTOCOLLECTORS AND A DEPLETED COMMON NODE - An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output. | 03-10-2011 |
| 20110227137 | SEMICONDUCTOR DEVICE AND DRIVING METHOD OF THE SAME - The present invention provides a semiconductor device including a memory that has a memory cell array including a plurality of memory cells, a control circuit that controls the memory, and an antenna, where the memory cell array has a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction different from the first direction, and each of the plurality of memory cells has an organic compound layer provided between the bit line and the word line. Data is written by applying optical or electric action to the organic compound layer. | 09-22-2011 |
| 20110272749 | LIGHT RECEIVING CIRCUIT - Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage. The control circuit outputs a control state output signal, which is a GND terminal voltage when a delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is less than a desired delay amount, and is the drain voltage of the NMOS transistor when the delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is the desired delay amount or more. The light receiving circuit outputs the control state output signal as an output signal. | 11-10-2011 |
| 20110291164 | CMOS three-dimensional image sensor detectors with assured non collection of late arriving charge, more rapid collection of other charge, and with improved modulation contrast - A CMOS-implementable TOF detector promptly collects charge whose creation time can be precisely known, while rejecting collection of potentially late arriving charge whose creation time may not be precisely known. Charges created in upper regions of the detector structure are ensured to be rapidly collected, while charges created in the lower regions of the detector structure, potentially late arriving charges, are inhibiting from being collected. | 12-01-2011 |
| 20120032241 | IMAGE SENSOR - An image sensor includes: a substrate, at least a pixel, and at least a light shield is provided. Wherein the pixel includes a photodiode and at least a transistor, and the transistor is connected to a metal line via a contact. The light shield is positioned around at least one side of the pixel, wherein the light shield is made while forming the contact. | 02-09-2012 |
| 20120080730 | SEMICONDUCTOR DEVICE WITH PHOTONICS - A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer. | 04-05-2012 |
| 20120119270 | DRIVING METHOD OF A SEMICONDUCTOR DEVICE - A horizontal scanning period is divided into n parts (n is a natural number), so that horizontal scanning can be performed (n×y) times in one frame period. That is, n signals can be outputted from each pixel, and storage times of the n signals are different from one another. Then, since a signal suited to the intensity of light irradiated to each pixel can be selected, information of an object can be accurately read. | 05-17-2012 |
| 20120126298 | SELF-POWERED INTEGRATED CIRCUIT WITH PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the photovoltaic cell portion. | 05-24-2012 |
| 20120168835 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 07-05-2012 |
| 20120175690 | SI PHOTODIODE WITH SYMMETRY LAYOUT AND DEEP WELL BIAS IN CMOS TECHNOLOGY - A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced. | 07-12-2012 |
| 20120181588 | PIXEL SENSOR CELLS WITH A SPLIT-DIELECTRIC TRANSFER GATE - Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage. | 07-19-2012 |
| 20120187461 | SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INTERFACE FOR AMBIENT COUPLING - A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material. | 07-26-2012 |
| 20120193689 | PIXEL OF A MULTI-STACKED CMOS IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC. | 08-02-2012 |
| 20120193690 | PHOTOELECTRIC CONVERSION APPARATUS - There is provided a photoelectric conversion apparatus which is characterized by comprising a plurality of photoelectric conversion regions of a first conductivity type, and a plurality of semiconductor regions of a second conductivity type opposite to the first conductivity type; and in that the plurality of photoelectric conversion regions of the first conductivity type and the plurality of semiconductor regions are alternately arranged, and a voltage controlling unit is further provided to change a width of a depletion layer formed in a semiconductor substrate by controlling a voltage to be applied to the semiconductor region of the second conductivity type provided between the plurality of photoelectric conversion regions of the first conductivity type. | 08-02-2012 |
| 20120199892 | Light Signal Transfer Device with Conductive Carbon Line - A light signal transfer device comprises a substrate having a gate dielectric layer; a source and drain doped regions formed in the substrate; a gate formed on the gate dielectric layer; a carbon nano-tube material formed under the gate dielectric layer to act a channel; and a photo-diode doped region formed adjacent to one of the source and drain doped regions, wherein the areas of the channel and the photo-diode doped region are fixed, the carbon nano-tube material reducing area of the channel and increase photo reception area for the photo-diode doped region to improve performance of the light signal transfer device. | 08-09-2012 |
| 20120228681 | IMAGE AND LIGHT SENSOR CHIP PACKAGES - An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip. | 09-13-2012 |
| 20120241825 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first thin film diode ( | 09-27-2012 |
| 20120256241 | Semiconductor Device and Method of Driving the Same - To provide a semiconductor device and a driving method of the same that is capable of enlarging a signal amplitude value as well as increasing a range in which a linear input/output relationship operates while preventing a signal writing-in time from becoming long. The semiconductor device having an amplifying transistor and a biasing transistor and the driving method thereof, wherein an electric discharging transistor is provided and pre-discharge is performed. | 10-11-2012 |
| 20120261729 | SHALLOW-TRENCH-ISOLATION (STI)-BOUNDED SINGLE-PHOTON AVALANCHE PHOTODETECTORS - Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications. | 10-18-2012 |
| 20120273854 | GLOBAL SHUTTER PIXEL WITH IMPROVED EFFICIENCY - A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer. | 11-01-2012 |
| 20120292675 | PHOTOVOLTAIC DEVICE WITH LATERAL P-I-N LIGHT-SENSITIVE DIODES - A photovoltaic device includes lateral P-I-N light-sensitive diodes respectively formed in portions of a planar semiconductor material (e.g., polycrystalline or crystalline silicon) layer that is entirely disposed on an insulating material (e.g., SiO2) layer utilizing, e.g., STI or SOI techniques. Each light-sensitive diode includes parallel elongated doped regions respectively formed by P+ and N+ dopant extending entirely through the semiconductor layer material and separated by an intervening elongated intrinsic (native) region. The light-sensitive diodes are connected in series by patterned conductive (e.g., metal film) structures. Optional bypass diodes are formed next to each lateral P-I-N light-sensitive diodes. Optional trenches are defined between adjacent light-sensitive diodes. The photovoltaic devices are either utilized to form low-cost embedded low power photovoltaic arrays on CMOS IC devices, or produced on low-cost SOI substrates to provide, for example, low-cost, high voltage solar arrays for solar energy concentrators. | 11-22-2012 |
| 20120292676 | Novel Very Fast Optic Nonvolatile Memory with Alternative Carrier Lifetimes and Bandgap Energies, Optic Random Access, and Mirrored "Fly-back" Configurations - The present invention is for a fast optic nonvolatile memory cell (FONM) that operates with a speed >1000000 times faster than the commercially available FLASH memory. The information (or charges) can be entered into the FONM cell by switching on a built-in laser or LED (Light Emitting Diode). Excited by the lights, and driven by electric fields, the regions of low carrier lifetimes thermally generate excess electrons or positive charges to fill the storage gaps or interfaces. To detect the stored information, two BJTs (Bipolar Junction Transistors) are arranged in a mirrored configuration—with alternative regions of high or low carrier lifetimes and bandgap energies. By comparing the BJT “fly-back” characteristics a voltage difference can be detected as a signal of whether the information is stored or not stored. | 11-22-2012 |
| 20120313155 | Photo Detector and Methods of Manufacturing and Operating Same - A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers. | 12-13-2012 |
| 20130056806 | UNIT PIXEL OF COLOR IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film having one surface thereof being in contact with the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel formed between the source and the drain and configured to form flow of an electric current between the source and drain. | 03-07-2013 |
| 20130056807 | PHOTOELECTRIC CONVERTING APPARATUS - A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other. | 03-07-2013 |
| 20130119447 | NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric. | 05-16-2013 |
| 20130153975 | Device Having a Plurality of Photosensitive Microcells Arranged in Row or Matrix Form - The invention provides a Silicon Photomultiplier (SiPM). The SiPM includes a plurality of microcells, a nonlinear element integrated in each one of the plurality of microcells, and a trigger line for outputting a summated current of the plurality of microcells, wherein the nonlinear element provides for a separated timing and energy signal. | 06-20-2013 |
| 20130207168 | PHOTODIODE EMPLOYING SURFACE GRATING TO ENHANCE SENSITIVITY - A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a surface grating of periodic field oxide in a periodic configuration and/or gate structures in a periodic configuration is formed. The field oxide may be formed using an STI process or a LOCOS process. A semiconductor device with a surface grating including both field oxide and gate structures has the gate structures over the semiconductor substrate, between the field oxide. The surface grating has a pitch length up to 3 microns. The surface grating covers at least half of the photodiode. | 08-15-2013 |
| 20130234219 | RADIOACTIVE-RAY IMAGING APPARATUS, RADIOACTIVE-RAY IMAGING DISPLAY SYSTEM AND TRANSISTOR - Disclosed herein is a transistor including: a semiconductor layer; a first gate insulation film and a first interlayer insulation film which are provided on a specific surface side of the semiconductor layer; a first gate electrode provided at a location between the first gate insulation film and the first interlayer insulation film; an insulation film provided on the other surface side of the semiconductor layer; source and drain electrodes provided by being electrically connected to the semiconductor layer; and a shield electrode layer provided in such a way that at least portions of the shield electrode layer face edges of the first gate electrode, wherein at least one of the first gate insulation film, the first interlayer insulation film and the insulation film include a silicon-oxide film. | 09-12-2013 |
| 20130264618 | METHOD FOR MANUFACTURING BACKSIDE-ILLUMINATED IMAGE SENSOR - A method for manufacturing a backside-illuminated image sensor includes (1) forming an isolation film on the front side of a semiconductor substrate with a buried insulating layer formed therein to define an active region; (2) forming a light-receiving element in the active region of the semiconductor substrate; and (3) forming an inter-layer dielectric layer on the front side of the semiconductor substrate on which the light-receiving element is formed. The method may include forming a super contact hole to pass through the inter-layer dielectric layer and the buried insulating layer in a pad region defined on the front side of the semiconductor substrate reaching the semiconductor substrate. The method may include forming a barrier layer of a metal oxide film containing transition metal at the bottom and sidewall of the super contact hole. The method may include filling a conductive material in the super contact hole, in which the barrier layer is formed, to form a super contact. | 10-10-2013 |
| 20130270618 | TOUCH PANEL AND FABRICATING METHOD THEREOF - A touch panel and fabricating method thereof are provided. The patterned transparent conductive layer, disposed on the substrate, includes first electrodes. The photo-sensing layers are disposed on the first electrodes. The first patterned conductive layer includes gate electrodes, scan lines and second electrodes. The gate electrodes and the scan lines are disposed on the substrate. The second electrodes are disposed on the photo-sensing layers. The first electrodes, the photo-sensing layers and the second electrodes constitute photo-sensors. The second patterned conductive layer includes source electrodes and drain electrodes, wherein the gate electrodes, the channel layers, the source electrodes and the drain electrodes constitute read-out transistors and each of the read-out transistors is electrically connected to the corresponding photo-sensor respectively. | 10-17-2013 |
| 20130320418 | Self-Aligned Implantation Process for Forming Junction Isolation Regions - A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation. | 12-05-2013 |
| 20130320419 | CIS Image Sensors with Epitaxy Layers and Methods for Forming the Same - A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric. | 12-05-2013 |
| 20130341690 | ULTRA-VIOLET LIGHT SENSING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides an ultra-violet light sensing device. The ultra-violet light sensing device includes a first conductivity type substrate, a second conductivity type region, and a first conductivity type high density region. The first conductivity type substrate includes a light incident surface. The second conductivity type region is disposed in the first conductivity type substrate and adjacent to the light incident surface. The first conductivity type high density region is disposed under the second conductivity type region. The present invention also provides another ultra-violet light sensing device, which further includes a first conductivity type high density shallow region which is sandwiched between the light incident surface and the second conductivity type region. Manufacturing methods for these ultra-violet light sensing devices are also disclosed in the present invention. | 12-26-2013 |
| 20140001521 | HIGH-FREQUENCY OPTOELECTRONIC DETECTOR, SYSTEM AND METHOD | 01-02-2014 |
| 20140008707 | HIGH SENSITIVITY IMAGE SENSORS AND METHODS OF OPERATING THE SAME - A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions. | 01-09-2014 |
| 20140015023 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-16-2014 |
| 20140021518 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes: a first substrate; a photo transistor on the first substrate; and a switching transistor connected to the photo transistor. The photo transistor includes a light blocking film on the first substrate, a first gate electrode on the light blocking film and in contact with the light blocking film, a first semiconductor layer on the first gate electrode and overlapping the light blocking film, and a first source electrode and a first drain electrode on the first semiconductor layer. The switching transistor includes a second gate electrode on the first substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and a second source electrode and a second drain electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are at a same layer of the display device, and each includes crystalline silicon germanium. | 01-23-2014 |
| 20140027826 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 01-30-2014 |
| 20140054661 | NANOWIRE PHOTO-DETECTOR GROWN ON A BACK-SIDE ILLUMINATED IMAGE SENSOR - An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. | 02-27-2014 |
| 20140061737 | Isolation for Semiconductor Devices - A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material. | 03-06-2014 |
| 20140077282 | TFT FLAT SENSOR AND MANUFACTURING METHOD THEREFOR - A TFT flat sensor comprises pixel units each comprising: a common electrode and a common electrode insulating layer on a substrate, wherein a first via hole is provided in the common electrode insulating layer at a location corresponding to the common electrode; a gate electrode on the common electrode insulating layer; a first conductive film layer on the common electrode and the gate electrode wherein the first conductive film layer contacts the common electrode through a first via hole; a gate insulating layer, an active layer, a drain electrode and a source electrode, a second conductive film layer, a protection layer and a third conductive film layer on the first conductive film layer; a second via hole is provided in the protection layer at a location corresponding to the source electrode through which the third conductive film layer contacts the source electrode. | 03-20-2014 |
| 20140091374 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 04-03-2014 |
| 20140091375 | Implant Isolated Devices and Method for Forming the Same - A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region. | 04-03-2014 |
| 20140103408 | SOLID-STATE IMAGING DEVICE - In a solid-state imaging device, N regions serving as photoelectric conversion diodes are formed on outer peripheries of P regions in upper portions of island-shaped semiconductors formed on a substrate, and P | 04-17-2014 |
| 20140103409 | SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF - An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate. | 04-17-2014 |
| 20140110771 | SOLID-STATE IMAGING DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, a first line provided in the peripheral circuit area and on a first principal surface of the semiconductor substrate, a second line provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a first through electrode connected to one end of the first line and one end of the second line and passing through the semiconductor substrate, and a second through electrode connected to the other end of the first line and the other end of the second line and passing through the semiconductor substrate. | 04-24-2014 |
| 20140131778 | Wide Bias Background Subtraction Pixel Front-End with Short Protection - Pixel Front end circuits particularly applicable to photodetectors requiring wide bias ranges and/or with high background currents. In various versions, wide bias ranges, short protection, and background current subtraction, both predetermined and automatically sampled, are disclosed. | 05-15-2014 |
| 20140183606 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment of the invention, there is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming a trench downward from an upper face of a semiconductor layer at a position where an element isolation area is formed in the semiconductor layer, and melting the upper face of the trench-formed semiconductor layer to close an open end of the trench. | 07-03-2014 |
| 20140191302 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip. | 07-10-2014 |
| 20140203340 | PHOTODIODE AND PRODUCTION METHOD - The photodiode has a p-type doped region ( | 07-24-2014 |
| 20140209985 | GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector. | 07-31-2014 |
| 20140217485 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 08-07-2014 |
| 20140231886 | TWO-DIMENSIONAL MATERIAL STACKED FLEXIBLE PHOTOSENSOR - A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure. | 08-21-2014 |
| 20140239360 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE PICKUP DEVICE USING THE SAME - A semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region. | 08-28-2014 |
| 20140264500 | Photovoltaic Device Formed On Porous Silicon Isolation - A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P− epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P− epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators. | 09-18-2014 |
| 20140264501 | DEPLETION-MODE FIELD-EFFECT TRANSISTOR-BASED PHOTOTRANSITOR - A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon. | 09-18-2014 |
| 20140284669 | OPTOELECTRONIC INTEGRATED DEVICE INCLUDING A PHOTODETECTOR AND A MOSFET TRANSISTOR, AND MANUFACTURING PROCESS THEREOF - An optoelectronic integrated device includes a body made of semiconductor material, which is delimited by a front surface and includes a substrate having a first type of conductivity, an epitaxial region, which has the first type of conductivity and forms the front surface, and a ring region having a second type of conductivity, which extends into the epitaxial region from the front surface, and delimiting an internal region. The optoelectronic integrated device moreover includes a MOSFET including at least one body region having the second type of conductivity, which contacts the ring region and extends at least in part into the internal region from the front surface. A photodetector includes a photodetector region having the second type of conductivity, and extends into the semiconductor body starting from the front surface, contacting the ring region. | 09-25-2014 |
| 20140332868 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively. | 11-13-2014 |
| 20140374808 | SEMICONDUCTOR COMPONENT WITH TRENCH GATE - The present invention relates to a semiconductor component ( | 12-25-2014 |
| 20150035027 | SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INERFACE FOR AMBIENT COUPLING - A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material. | 02-05-2015 |
| 20150041870 | SENSOR AND METHOD FOR FABRICATING THE SAME - A sensor and its fabrication method are provided, the sensor includes: a base substrate, a group of gate lines and a group of data lines arranged as crossing each other, and a plurality of sensing elements arranged in an array and defined by the group of gate lines and the group of data lines, each sensing element comprising a TFT device and a photodiode sensing device, wherein: the TFT device is a top gate TFT; the photodiode sensing device includes: a bias electrode and a bias electrode pin connected with the bias electrode, both of which are disposed on the base substrate; a photodiode disposed on the bias electrode and a transparent electrode disposed on the photodiode and connected with the source electrode. | 02-12-2015 |
| 20150054041 | CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING - A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device. | 02-26-2015 |
| 20150108555 | METHOD OF MANUFACTURING IMAGE SENSORS - In a method of manufacturing an image sensor, a photodiode is formed in a substrate. The substrate is etched to form an opening vertically aligned with the photodiode. A gate insulation layer and a first preliminary polysilicon layer are formed on an inner surface of opening and a front surface of substrate. A first doping process is performed on first preliminary polysilicon layer to form first polysilicon layer, and the first polysilicon layer in the opening is uniformly doped with first conductivity type impurities. A second preliminary polysilicon layer is formed on first polysilicon layer. A second doping process is performed on second preliminary polysilicon layer to form second polysilicon layer doped with first conductivity type impurities. The first and second polysilicon layers are patterned to form a buried gate electrode in the opening. The first impurity region is formed at an upper portion of substrate adjacent to buried gate electrode. | 04-23-2015 |
| 20150123177 | Patterned Poly Silicon Structure as Top Electric Contact to MOS-Type Optical Modulators - A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate. | 05-07-2015 |
| 20150145006 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - The semiconductor device includes a plurality of pixels arranged in rows and columns, and first transistors fewer than the number of the plurality of pixels. The plurality of pixels each includes a photodiode and an amplifier circuit. The amplifier circuit holds the accumulated charge and includes at least a second transistor electrically connected to a cathode of the photodiode. The cathode of the photodiode in the pixel in an n-th row and the cathode of the photodiode in the pixel in an (n+1)-th row are electrically connected to the first transistor. The number n is a natural number. The pixel in the n-th row and the pixel in the (n+1)-th row are in an identical column. | 05-28-2015 |
| 20150364519 | ACTIVE PIXEL SENSOR HAVING A RAISED SOURCE/DRAIN - An integrated circuit having an array of APS cells. Each cell in the array has at least one transistor source or drain region that is raised relative to a channel region formed in a semiconductor substrate. The raised source or drain region includes doped polysilicon deposited on the surface of the semiconductor body and a region of the bodyextending to the channel region that has been doped to an opposite doping type from that of the channel region by diffusion of dopants from the deposited polysilicon. | 12-17-2015 |
| 20160013352 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR USING THE SAME | 01-14-2016 |
| 20160035773 | SEMICONDUCTOR IMAGE SENSORS HAVING CHANNEL STOP REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type. | 02-04-2016 |
| 20160086983 | SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE - A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures. | 03-24-2016 |
| 20160099374 | SEMICONDUCTOR DEVICE - A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented. | 04-07-2016 |
| 20160118527 | CHARGE COUPLED DEVICE BASED ON ATOMICALLY LAYERED VAN DER WAALS SOLID STATE FILM FOR OPTO-ELECTRONIC MEMORY AND IMAGE CAPTURE - An opto-electronic sensor may provide one or more layers of atomically layered photo-sensitive materials. The sensor may include a gate electrode layer, a dielectric layer in contact with the gate electrode layer, and a working media layer that is photo-sensitive deposited on the dielectric layer. The working media layer may provide one or more layers of one or more materials where each of the one or more layers is an atomic layer. The sensor may also include side electrodes in contact with the working media layer. | 04-28-2016 |
| 20160133616 | PHOTO-SENSITIVE SILICON PACKAGE EMBEDDING SELF-POWERED ELECTRONIC SYSTEM - A self-powered electronic system comprises a first chip ( | 05-12-2016 |
| 20160148959 | Monolithic Integration Techniques for Fabricating Photodetectors with Transistors on Same Substrate - Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues. | 05-26-2016 |
| 20160155763 | Monolithic Integration Techniques for Fabricating Photodetectors with Transistors on Same Substrate | 06-02-2016 |
| 20160155770 | IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME | 06-02-2016 |
| 20160181293 | Semiconductor Photomultiplier | 06-23-2016 |
| 20160181445 | SILICON PHOTONICS INTEGRATION METHOD AND STRUCTURE | 06-23-2016 |
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