| Entries |
| Document | Title | Date |
|---|
| 20080258134 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH MASKLESS SUPERLATTICE DEPOSITION FOLLOWING STI FORMATION AND RELATED STRUCTURES - A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. The semiconductor device may further include a lateral spacer between the superlattice layer and the STI region and which may include a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion. | 10-23-2008 |
| 20080296556 | Method For Dopant Calibration of Delta Doped Multilayered Structure - In a calibration method, the relation between dopant concentrations of δ-doping layers in a multilayered semiconductor structure and process parameters is determined S | 12-04-2008 |
| 20090057649 | Assembly of Ordered Carbon Shells on Semiconducting Nanomaterials - In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described. | 03-05-2009 |
| 20090152529 | LIGHT EMITTING DEVICES WITH INHOMOGENEOUS QUANTUM WELL ACTIVE REGIONS - A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer. | 06-18-2009 |
| 20090173932 | Thermoelectric Material, Infrared Sensor and Image Forming Device - A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO | 07-09-2009 |
| 20090236586 | EPITAXIAL MATERIAL USED FOR GAN BASED LED WITH LOW POLARIZATION EFFECT AND MANUFACTURING METHOD THEREOF - A method of manufacturing epitaxial material used for GaN based LED with low polarization effect, which includes steps of growing n-type InGaAlN layer composed of GaN buffer layer ( | 09-24-2009 |
| 20090315016 | ATOMIC LAYER DEPOSITION FOR FUNCTIONALIZING COLLOIDAL AND SEMICONDUCTOR PARTICLES - A method for producing a product of a functionalized nanocomposition colloidal material using atomic layer deposition to coat the colloidal material. The ALD layer comprises an inorganic material which enables improved optical and electrical properties for the nanocomposite. | 12-24-2009 |
| 20100084630 | Apparatus and Method of Detecting Electromagnetic Radiation - A high speed and miniature detection system, especially for electromagnetic radiation in the GHz and THz range comprises a semiconductor structure having a 2D charge carrier layer or a quasi 2D charge carrier layer with incorporated single or multiple defects, at least first and second contacts to the charge carrier layer, and a device for measuring photovoltage between the first and second contacts. System operation in various embodiments relies on resonant excitation of plasma waves in the semiconductor structure. | 04-08-2010 |
| 20100155700 | Thermoelectric Cooler for Semiconductor Devices with TSV - This invention discloses a thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip. | 06-24-2010 |
| 20100207100 | Radiation-Emitting Semiconductor Body - A radiation-emitting semiconductor body includes a contact layer and an active zone. The semiconductor body has a tunnel junction arranged between the contact layer and the active zone. The active zone has a multi-quantum well structure containing at least two active layers that emit electromagnetic radiation when an operating current is impressed into the semiconductor body. | 08-19-2010 |
| 20100258785 | Superlattice nanopatterning of wires and complex patterns - Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate. | 10-14-2010 |
| 20100276664 | THIN-WALLED STRUCTURES - Various embodiments provide thin-walled structures and methodologies for their formation. In one embodiment, the thin-walled structure can be formed by disposing a semiconductor material in a patterned aperture using a selective growth mask that includes a plurality of patterned apertures, followed by a continuous growth of the semiconductor material using a pulsed growth mode. The patterned aperture can include at least one lateral dimension that is small enough to allow a threading defect termination at sidewall(s) of the formed thin-walled structure. In addition, high-quality III-N substrate structures and core-shell MQW active structures can be formed from the thin-walled structures for use in devices like light emitting diodes (LEDs), lasers, or high electron mobility transistors (HEMTs). | 11-04-2010 |
| 20100276665 | PRODUCTION OF SEMICONDUCTOR DEVICES - A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process. | 11-04-2010 |
| 20100276666 | CONTROLLED QUANTUM DOT GROWTH - The present disclosure generally relates to techniques for controlled quantum dot growth as well as a quantum dot structures. In some examples, a method is described that includes one or more of providing a substrate, forming a defect on the substrate, depositing a layer on the substrate and forming quantum dots along the defect. | 11-04-2010 |
| 20100289004 | ZNO-BASED THIN FILM AND ZNO-BASED SEMICONDUCTOR ELEMENT - Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer | 11-18-2010 |
| 20100308303 | QUANTUM DOT MEMORY - A method of making a quantum dot memory cell, the quantum dot memory cell including an array of quantum dots disposed between a first electrode and a second electrode, includes obtaining values for a tunneling current through the quantum dot memory cell as a function of a voltage applied to the quantum dot memory cell and selecting parameters of the quantum dot memory cell such that the tunneling current through the quantum dot memory cell exhibits a bistable current for at least some values of the voltage applied to the quantum dot memory cell. The values for the tunneling current are determined on the basis of a density of states of the array of quantum dots. | 12-09-2010 |
| 20110006285 | CORE-ALLOYED SHELL SEMICONDUCTOR NANOCRYSTALS - The invention relates to a core-alloyed shell semiconductor nanocrystal comprising: (i) a core of a semiconductor material having a selected band gap energy; (ii) a core-overcoating shell consisting of one or more layers comprised of an alloy of the said semiconductor of (i) and a second semiconductor; (iii) and an outer organic ligand layer, provided that the core semiconductor material is not HgTe. In certain embodiments, the core semiconductor material is PbSe and the alloy shell semiconductor material has the PbSe | 01-13-2011 |
| 20110079768 | PHOTOACTIVE MATERIALS CONTAINING BULK AND QUANTUM-CONFINED SEMICONDUCTOR STRUCTURES AND OPTOELECTRONIC DEVICES MADE THEREFROM - The present invention provides photoactive materials that include quantum-confined semiconductor nanostructures in combination with non-quantum confined and bulk semiconductor structures to enhance or create a type II band offset structure. The photoactive materials are well-suited for use as the photoactive layer in photoactive devices, including photovoltaic devices, photoconductors and photodetectors. | 04-07-2011 |
| 20110140083 | Semiconductor Device Structures with Modulated Doping and Related Methods - A semiconductor device may include a doped semiconductor region having a modulated dopant concentration. The doped semiconductor region may be a silicon doped Group III nitride semiconductor region with a dopant concentration of silicon being modulated in the Group III nitride semiconductor region. In addition, a semiconductor active region may be configured to generate light responsive to an electrical signal therethrough. Related methods, devices, and structures are also discussed. | 06-16-2011 |
| 20110168978 | High Efficiency Thermoelectric Materials and Devices - Growth of thermoelectric materials in the form of quantum well superlattices on three-dimensionally structured substrates provide the means to achieve high conversion efficiency of the thermoelectric module combined with inexpensiveness of fabrication and compatibility with large scale production. Thermoelectric devices utilizing thermoelectric materials in the form of quantum well semiconductor superlattices grown on three-dimensionally structured substrates provide improved thermoelectric characteristics that can be used for power generation, cooling and other applications. | 07-14-2011 |
| 20110180783 | BOUNDARY-MODULATED NANOPARTICLE JUNCTIONS AND A METHOD FOR MANUFACTURE THEREOF - A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed. | 07-28-2011 |
| 20110198569 | APPARATUS AND METHODS OF NANOPATTERNING AND APPLICATIONS OF SAME - A method for patterning nanostructures in a semiconductor heterostructure, which has at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer. The method includes the steps of making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure; bonding the semiconductor heterostructure to a support substrate such that the first surface of the first layer of the semiconductor heterostructure is faced to the support substrate; etching off the second layer of the semiconductor heterostructure; and depositing a third layer over the second surface of the first layer of the semiconductor heterostructure. | 08-18-2011 |
| 20110204330 | JOINED NANOSTRUCTURES AND METHODS THEREFOR - Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures. | 08-25-2011 |
| 20110233519 | Fabrication of GaN Substrate by Defect Selective Passivation - Defect selective passivation in semiconductor fabrication for reducing defects. | 09-29-2011 |
| 20110240962 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An epitaxial substrate for an electronic device having a Si single crystal substrate, a buffer as an insulating layer formed on the Si single crystal substrate, and a main laminated body formed by plural group III nitride layers epitaxially grown on the buffer, wherein a lateral direction of the epitaxial substrate is defined as an electric current conducting direction. The buffer including at least an initially grown layer in contact with the Si single crystal substrate and a superlattice laminate constituted of a superlattice multilayer structure on the initially grown layer. | 10-06-2011 |
| 20110248241 | NITRIDE SEMICONDUCTOR ELEMENT - A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer. | 10-13-2011 |
| 20110309329 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a substrate, an Al | 12-22-2011 |
| 20110315959 | ELECTRONIC AND OPTOELECTRONIC DEVICES WITH QUANTUM DOT FILMS - Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. | 12-29-2011 |
| 20120007048 | III-Nitride Based Semiconductor Structure with Multiple Conductive Tunneling Layer - A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer. | 01-12-2012 |
| 20120061648 | APPARATUS, METHOD AND COMPUTER PROGRAM PRODUCT PROVIDING RADIAL ADDRESSING OF NANOWIRES - Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array. | 03-15-2012 |
| 20120068157 | Transistor Having Graphene Base - A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than E | 03-22-2012 |
| 20120074385 | Semiconductor Devices And Methods of Manufacturing The Same - A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer. | 03-29-2012 |
| 20120119189 | OHMIC CONTACT TO SEMICONDUCTOR - An ohmic contact to a semiconductor layer including a heterostructure barrier layer and a metal layer adjacent to the heterostructure barrier layer is provided. The heterostructure barrier layer can form a two dimensional free carrier gas for the contact at a heterointerface of the heterostructure barrier layer and the semiconductor layer. The metal layer is configured to form a contact with the two dimensional free carrier gas. | 05-17-2012 |
| 20120168719 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE, IN WHICH CURRENT FLOWS IN LATERAL DIRECTION AND METHOD OF PRODUCING THE SAME - To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact. | 07-05-2012 |
| 20120319082 | LOW THERMAL CONDUCTIVITY MATRICES WITH EMBEDDED NANOSTRUCTURES AND METHODS THEREOF - A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C. | 12-20-2012 |
| 20120326123 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 12-27-2012 |
| 20130009132 | LOW THERMAL CONDUCTIVITY MATERIAL - Embodiments of a material having low cross-plane thermal conductivity are provided. Preferably, the material is a thermoelectric material. In general, the thermoelectric material is designed to block phonons, which reduces or eliminates heat transport due to lattice vibrations and thus cross-plane thermal conductivity. By reducing the thermal conductivity of the thermoelectric material, a figure-of-merit (ZT) of the thermoelectric material is improved. In one embodiment, the thermoelectric material includes multiple superlattice periods that block, or reflect, multiple phonon wavelengths. | 01-10-2013 |
| 20130048947 | METHODS TO FABRICATE VERTICALLY ORIENTED ANATASE NANOWIRE ARRAYS ON TRANSPARENT CONDUCTIVE SUBSTRATES AND APPLICATIONS THEREOF - The present invention relates to growth of vertically-oriented crystalline nanowire arrays upon a transparent conductive or other substrate for use in 3 | 02-28-2013 |
| 20130175499 | Boundary-Modulated Nanoparticle Junctions And A Method For Manufacture Thereof - A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed. | 07-11-2013 |
| 20130240835 | SEMICONDUCTOR DEVICE AND RECEIVER - A semiconductor device includes a p-type semiconductor layer, an n-type semiconductor layer, a pn junction portion at which the p-type semiconductor layer and the n-type semiconductor layer are joined to each other, and a multiple quantum barrier structure or a multiple quantum well structure that is provided in at least one of the p-type semiconductor layer and the n-type semiconductor layer and functions as a barrier against at least one of electrons and holes upon biasing in a forward direction. Upon biasing in a reverse direction, a portion that allows band-to-band tunneling of electrons is formed at the pn junction portion. | 09-19-2013 |
| 20130334495 | SUPERLATTICE STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A superlattice structure, and a semiconductor device including the same, include a plurality of pairs of layers are in a pattern repeated at least two times, in which a first layer and a second layer constitute a pair, the first layer is formed of Al | 12-19-2013 |
| 20140001437 | JOINED NANOSTRUCTURES AND METHODS THEREFOR | 01-02-2014 |
| 20140175378 | EPITAXIAL FILM GROWTH ON PATTERNED SUBSTRATE - An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein. | 06-26-2014 |
| 20140346441 | Semiconductor Layer Including Compositional Inhomogeneities - A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer. | 11-27-2014 |
| 20170236708 | SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR | 08-17-2017 |
| 20170236924 | SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR | 08-17-2017 |
