| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257017000 | With particular barrier dimension | 7 |
| 20110140084 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a substrate; and an active layer disposed on the substrate, wherein the active layer includes a first barrier layer containing GaAs, a quantum dot layer, which is disposed on the first barrier layer, which includes a quantum dot containing InAs, which includes a side barrier layer which covers at least a part of the quantum dot and a side surface of the quantum dot, and having an elongation strain inherent therein, and a second barrier layer disposed on the quantum dot layer. | 06-16-2011 |
| 20130285015 | PHOTOACTIVE DEVICES WITH IMPROVED DISTRIBUTION OF CHARGE CARRIERS, AND METHODS OF FORMING SAME - Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure. | 10-31-2013 |
| 20140008613 | STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction. | 01-09-2014 |
| 20140158984 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a silicon substrate, an aluminum nitride layer and a plurality of grading stress buffer layers. The aluminum nitride layer is disposed on the silicon substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al | 06-12-2014 |
| 20150123075 | INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME - Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness T | 05-07-2015 |
| 20150303344 | SUPERLATTICE STRUCTURE - A structure comprised of an InAsSb layer adjacent to a GaSb layer, with the adjacent InAsSb and GaSb layers repeating to form a superlattice (SL). The structure is preferably an unstrained SL, wherein the composition of the InAsSb layer is InAs | 10-22-2015 |
| 20160155807 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR PACKAGE | 06-02-2016 |
