| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257020000 | Field effect device | 59 |
| 20090032802 | MOSFET DEVICE FEATURING A SUPERLATTICE BARRIER LAYER AND METHOD - A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer. | 02-05-2009 |
| 20090173934 | Nonvolatile memory and three-state FETs using cladded quantum dot gate structure - The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration. QD-gate FETs, potentially suitable for 8 nm channel lengths, in vertical configuration (VFET) are also described. | 07-09-2009 |
| 20090200540 | Metal-Oxide-Semiconductor Device Including a Multiple-Layer Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes a superlattice structure wherein a mini-band is formed. The energy filter is operative to control an injection of carriers from the first source/drain into the channel. The energy filter, in combination with the first source/drain, is configured to produce an effective zero-Kelvin first source/drain. | 08-13-2009 |
| 20100006821 | NANOSCALE MULTI-JUNCTION QUANTUM DOT DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern. | 01-14-2010 |
| 20100084631 | Phase-controlled field effect transistor device and method for manufacturing thereof - A phase controllable field effect transistor device is described. The device provides first and second scattering sites disposed at either side of a conducting channel region, the conducting region being gated such that on application of an appropriate signal to the gate, energies of the electrons in the channel region defined between the scattering centres may be modulated. | 04-08-2010 |
| 20100090197 | METHOD OF MANUFACTURING SEMICONDUCTOR NANOWIRE SENSOR DEVICE AND SEMICONDUCTOR NANOWIRE SENSOR DEVICE MANUFACTURED ACCORDING TO THE METHOD - Provided are a method of manufacturing a semiconductor nanowire sensor device and a semiconductor nanowire sensor device manufactured according to the method. The method includes preparing a first conductive type single crystal semiconductor substrate, forming a line-shaped first conductive type single crystal pattern from the first conductive type single crystal semiconductor substrate, forming second conductive type epitaxial patterns on both sidewalls of the first conductive type single crystal pattern, and forming source and drain electrodes at both ends of the second conductive type epitaxial patterns. | 04-15-2010 |
| 20100096619 | ELECTRONIC DEVICES USING CARBON NANOTUBES HAVING VERTICAL STRUCTURE AND THE MANUFACTURING METHOD THEREOF - Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same. The method of manufacturing an electronic device having a vertical CNT includes the steps of: (a) preparing a substrate on which a silicon source is formed; (b) forming a first insulating layer on the substrate, and etching the first insulating layer such that a top surface of the silicon source is exposed; (c) forming a second insulating layer on the silicon source, and forming a gate by patterning the second insulating layer; (d) forming a third insulating layer on the gate, and forming a through hole in which a carbon nanotube channel is to be formed by etching the third insulating layer and the second insulating layer; (e) forming a fourth insulating layer surrounding the gate on the through hole and the third insulating layer, and forming a spacer by etching the fourth insulating layer; (f) forming a metal catalyst on the silicon source; (g) vertically growing the carbon nanotube channel on the silicon source using the metal catalyst; (h) forming a fifth insulating layer on the through hole in which the carbon nanotube is formed and the third insulating layer; and (i) patterning the fifth insulating layer such that the carbon nanotube channel is exposed, and forming a silicon drain. An arrangement problem of horizontal CNTs can be solved by applying vertical CNTs and a selective silicon growth technique. | 04-22-2010 |
| 20100108987 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided. | 05-06-2010 |
| 20100127241 | Electronic Devices with Carbon Nanotube Components - An electronic device has a source electrode, a drain electrode spaced apart from said source electrode, and at least one of a conducting material, dielectric material and a semiconductor material disposed between said source electrode and said drain electrode. At least one of the source electrode, the drain electrode and the semiconductor material includes at least one nanowire. | 05-27-2010 |
| 20100181551 | Quantum dot transistor - One or more quantum dots are used to control current flow in a transistor. Instead of being disposed in a channel between source and drain, the quantum dot (or dots) are vertically separated from the source and drain by an insulating layer. Current can tunnel between the source/drain electrodes and the quantum dot (or dots) by tunneling through the insulating layer. Quantum dot energy levels can be controlled with one or more gate electrodes capacitively coupled to some or all of the quantum dot(s). Current can flow between source and drain if a quantum dot energy level is aligned with the energy of incident tunneling electrons. Current flow between source and drain is inhibited if no quantum dot energy level is aligned with the energy of incident tunneling electrons. Here energy level alignment is understood to have a margin of about the thermal energy (e.g., 26 meV at room temperature). | 07-22-2010 |
| 20100213440 | Silicon-Quantum-Dot Semiconductor Near-Infrared Photodetector - A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response. | 08-26-2010 |
| 20100224861 | Twin-drain spatial wavefunction switched field-effect transistors - A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned. | 09-09-2010 |
| 20100243989 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a superlattice buffer layer that is formed on the substrate and is composed of first Al | 09-30-2010 |
| 20100270535 | ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS - A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof. | 10-28-2010 |
| 20110233520 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device including a base substrate; a semiconductor layer formed on the base substrate and having a mesa protrusion including a receiving groove; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer, the source electrode having a source leg and the drain electrode having a drain leg; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part received into the receiving groove. The mesa protrusion has a superlattice structure including at least one trench at an interface between the mesa protrusion and the source electrode and between the mesa protrusion and the drain electrode, respectively, and the source leg and the drain leg are received in the trench. | 09-29-2011 |
| 20110278540 | FIELD-EFFECT TRANSISTOR - Provided is a field-effect transistor which is capable of suppressing current collapse. An HEMT as the field-effect transistor includes: a first semiconductor layer made of a first nitride semiconductor; and a second semiconductor layer formed on the first semiconductor layer and made of a second nitride semiconductor having a greater band gap than a band gap of the first nitride semiconductor, wherein the first semiconductor layer includes a region in which a threading dislocation density increases in a stacking direction. | 11-17-2011 |
| 20110309330 | 2-dimensional quantum wire array field effect transistor/power-transistor/switch/photo-cell - One, groups of several or many parallel vertical quantum wires arranged as 2-dimensional array interconnecting the source and drain of a transistor, are modulated with respect to their quantum-mechanical conductivity via the strength of an applied field. | 12-22-2011 |
| 20120007049 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers. | 01-12-2012 |
| 20120032146 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 02-09-2012 |
| 20120145995 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a nitride-based semiconductor device and a method for manufacturing the same. The nitride-based semiconductor device includes: a base substrate having a front surface and a rear surface opposite to the front surface; an epitaxial growth film formed on the front surface of the base substrate; a semiconductor layer formed on the rear surface of the base substrate; and an electrode structure body provided on the epitaxial growth film. | 06-14-2012 |
| 20120199813 | EXTREME HIGH MOBILITY CMOS LOGIC - A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. | 08-09-2012 |
| 20120256166 | DEPOSITION OF NANOPARTICLES - The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process. | 10-11-2012 |
| 20120280208 | QUANTUM DOT CHANNEL (QDC) QUANTUM DOT GATE TRANSISTORS, MEMORIES AND OTHER DEVICES - This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories. | 11-08-2012 |
| 20130082240 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space. | 04-04-2013 |
| 20130207078 | InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same - A double heterojunction field effect transistor (DHFET) includes a substrate, a buffer layer consisting of GaN back-barrier buffer layer formed on the substrate, a channel layer consisting of an In | 08-15-2013 |
| 20130313520 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 11-28-2013 |
| 20130328015 | EXTREME HIGH MOBILITY CMOS LOGIC - A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. | 12-12-2013 |
| 20140084245 | QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN - Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions. | 03-27-2014 |
| 20140151636 | SINGLE-WALLED CARBON NANOTUBES/QUANTUM DOT HYBRID STRUCTURES AND METHODS OF MAKING AND USE OF THE HYBRID STRUCTURES - Briefly described, embodiments of the present disclosure relate to structures including single-walled carbon nanotube/quantum dot networks, devices including the structures, and methods of making devices including the single-walled carbon nanotube/quantum dot networks. | 06-05-2014 |
| 20140175379 | EPITAXIAL FILM ON NANOSCALE STRUCTURE - An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein. | 06-26-2014 |
| 20140209861 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR, AND POWER SUPPLY APPARATUS - A semiconductor device includes a drift layer having a structure wherein a plurality of quantum dot layers each including a quantum dot containing In | 07-31-2014 |
| 20140264273 | SUPERLATTICE CRENELATED GATE FIELD EFFECT TRANSISTOR - The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches. | 09-18-2014 |
| 20140264274 | SEMICONDUCTOR DEVICE - To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap. | 09-18-2014 |
| 20140291614 | THIN FILM TRANSISTOR - A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a transition layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The transition layer is sandwiched between the insulating layer and the semiconductor layer. The transition layer is a silicon-oxide cross-linked polymer layer including a plurality of Si atoms. The plurality of Si atoms is bonded with atoms of the insulating layer and atoms of the semiconductor layer. | 10-02-2014 |
| 20140291615 | EXTREME HIGH MOBILITY CMOS LOGIC - A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate. | 10-02-2014 |
| 20140306181 | NITRIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - This specification relates to an enhancement-type semiconductor device having a passivation layer formed using a photoelectrochemical (PEC) method, and a fabricating method thereof.
| 10-16-2014 |
| 20140326951 | FIELD EFFECT POWER TRANSISTORS - A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate. | 11-06-2014 |
| 20150021552 | III-NITRIDE TRANSISTOR INCLUDING A P-TYPE DEPLETING LAYER - A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages. | 01-22-2015 |
| 20150034903 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first layer made of a group III nitride semiconductor of a first conductivity type, a second layer made of a group III nitride semiconductor of a second conductivity type on a first surface of the first layer, a third layer made of a group III nitride semiconductor of the first conductivity type on a first region of a surface of the second layer, a gate electrode extending through the second layer and the third layer and the first surface of the first layer, and insulated from the first, second, and third layers, a first electrode in contact with the third layer, a second electrode in contact with a second region of the surface of the second layer that is different from the first region, and a third electrode provided on a side of a second surface of the first layer. | 02-05-2015 |
| 20150034904 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device, a first-layer includes a group-III nitride semiconductor of a first conduction type. A second-layer includes a group-III nitride semiconductor of a second conduction type on a first surface of the first layer. A third-layer includes an Al-containing group-III nitride semiconductor on a first region of a surface of the second layer. A gate electrode has one end above a surface of the third-layer and has the other end within the first-layer via the second-layer. The gate electrode is insulated from the first- to third-layers. A first electrode is connected to the third-layer. A second electrode is connected to a second region of the surface of the second-layer. A third electrode is provided above a second surface of the first layer. The second surface is opposite to the first surface of the first layer. | 02-05-2015 |
| 20150053921 | ENHANCED SWITCH DEVICE AND MANUFACTURING METHOD THEREFOR - An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the substrate; fabricating and forming a dielectric layer on the nitride transistor structure, on which a gate region is defined; forming a groove structure on the gate region; depositing a p-type semiconductor material in the groove; removing the p-type semiconductor material outside the gate region on the dielectric layer; etching the dielectric layer in another position than the gate region on the dielectric layer to form two ohmic contact regions; and forming a source electrode and a drain electrode on the two ohmic contact regions, respectively. | 02-26-2015 |
| 20150076449 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a superlattice buffer layer formed on a substrate. An upper buffer layer is formed on the superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the upper busier layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is formed by cyclically laminating nitride semiconductor films having different composition. The upper buffer layer is formed by a nitride semiconductor material having a band gap wider than a band gap of the first semiconductor layer and doped with an impurity element that causes a depth of an acceptor level to be greater than or equal to 0.5 eV. | 03-19-2015 |
| 20150090957 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first superlattice buffer layer formed on a substrate. A second superlattice buffer layer is formed on the first superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the second superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. The first superlattice buffer layer is formed by alternately and cyclically laminating a first superlattice formation layer and a second superlattice formation layer. The second superlattice buffer layer is formed by alternately and cyclically laminating the first superlattice formation layer and the second superlattice formation layer. The first superlattice formation layer is formed by Al | 04-02-2015 |
| 20150108429 | CARBON NANOTUBE PRINTED ELECTRONICS DEVICES - Electronic devices include a network of purified and randomly aligned carbon nanotubes. The electronic devices include conductive regions that comprise conductive inks, and substrates such as flexible plastic materials including PET. Networks of randomly aligned carbon nanotubes are exposed to UV radiation to convert metallic carbon nanotubes to semiconductive carbon nanotubes. Conductive regions are printed onto a substrate using printing techniques such as inkjet printing and gravure printing. Devices are fabricated at low temperatures, without annealing and without vacuum. | 04-23-2015 |
| 20150108430 | TRANSISTOR CHANNEL - A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material. | 04-23-2015 |
| 20150123076 | QUANTUM CASCADE DETECTOR - A quantum cascade detector includes a semiconductor substrate, and an active layer formed by laminating unit laminate structures each having an absorption region with a first barrier layer to a second well layer and a transport region with a third barrier layer to an n-th well layer. A second absorption well layer has a layer thickness ½ or less of that of a first absorption well layer thickest in one period, and a coupling barrier layer has a layer thickness smaller than that of an exit barrier layer thickest in one period. The unit laminate structure has a detection lower level arising from a ground level in the first well layer, a detection upper level generated by coupling an excitation level in the first well layer and a ground level in the second well layer, and a transport level structure for electrons. | 05-07-2015 |
| 20150144877 | VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS - A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins. | 05-28-2015 |
| 20150144878 | SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE DEPLETION LAYER STACK AND RELATED METHODS - A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions. | 05-28-2015 |
| 20150357472 | QUANTUM WELL FIN-LIKE FIELD EFFECT TRANSISTOR (QWFINFET) HAVING A TWO-SECTION COMBO QW STRUCTURE - The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure. | 12-10-2015 |
| 20160013306 | METHOD AND APPARATUS FOR 3D CONCURRENT MULTIPLE PARALLEL 2D QUANTUM WELLS | 01-14-2016 |
| 20160049473 | ALL AROUND CONTACT DEVICE AND METHOD OF MAKING THE SAME - A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end. | 02-18-2016 |
| 20160049504 | INTEGRATED MULTICHANNEL AND SINGLE CHANNEL DEVICE STRUCTURE AND METHOD OF MAKING THE SAME - An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device. | 02-18-2016 |
| 20160064488 | NITRIDE BASED SEMICONDUCTOR DEVICE - A nitride based semiconductor device includes: a substrate; a first buffer layer disposed on the substrate; a second buffer layer disposed on the first buffer layer; a third buffer layer disposed on the second buffer layer, the third buffer layer including an AlGaN-based nitride semiconductor; a fourth buffer layer disposed on the third buffer layer, the fourth buffer layer including a GaN-based nitride semiconductor; a barrier layer disposed on the fourth buffer layer, the barrier layer including an AlGaN-based nitride semiconductor; and a source electrode and a drain electrode, each disposed on the barrier layer, and a gate electrode disposed between the source electrode and the drain electrode, wherein the third buffer layer is subjected to lattice relaxation. There can be provided a nitride based semiconductor device capable of reducing a leakage current and improving breakdown capability. | 03-03-2016 |
| 20160064538 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity. | 03-03-2016 |
| 20160126340 | MULTICHANNEL DEVICES WITH IMPROVED PERFORMANCE AND METHODS OF MAKING THE SAME - A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. | 05-05-2016 |
| 20160149023 | SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS - A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel. | 05-26-2016 |
| 20160190267 | ALL AROUND CONTACT DEVICE AND METHOD OF MAKING THE SAME - A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end. | 06-30-2016 |
| 20160197173 | Semiconductor Device having Group III-V Material Active Region and Graded Gate Dielectric | 07-07-2016 |
| 20160254378 | NITRIDE SEMICONDUCTOR | 09-01-2016 |
