Patent application number | Description | Published |
20130064992 | Process for Eliminating Fog Particles on a Surface of High P Concentration PSG Film - A process for eliminating fog particles on a surface of a high P concentration PSG film is provided. The process mainly comprises steps of: feeding oxygen to a plasma environment in a reaction chamber; mixing plasma with oxygen; causing oxygen to react with unstable phosphorus atoms in the PSG film by using energy of plasma; and forming a passive film on the surface of the PSG film to prevent phosphorus in the PSG film from reacting with hydrogen and oxygen in the air. With the process for eliminating fog particles on a surface of a high P concentration PSG film, by feeding oxygen into the reaction chamber, the high-density plasma can be mixed with oxygen effectively, so as to achieve formation of the passive film on the surface of the phosphosilicate glass and thereby block water vapour from contacting boron and phosphorus to cause crystallization. | 03-14-2013 |
20130224399 | METHOD OF FORMING NITROGEN-FREE DIELECTRIC ANTI-REFLECTION LAYER - The present invention provides a method of forming a nitrogen-free dielectric anti-reflection layer comprising: introducing a reaction gas into the discharge tube until the reaction gas reaching a stable state; introducing the reaction gas into the reaction chamber and then generating a plasma, or generating a plasma and then introducing the reaction gas into the reaction chamber, wherein the time delay occurs between the two processes is utilized to perform the deposition of the nitrogen-free dielectric anti-reflection layer; finally stop introducing the reaction gas and then stop generating the plasma. The method can flexibly control the extinction coefficient and the refractive index of the nitrogen-free dielectric anti-reflection layer so as to obtain a straight photoresist pattern and greatly reduce the photoresist standing waves effect and photoresist poisoning effect. | 08-29-2013 |
20130227502 | ALGORITHM OF CU INTERCONNECT DUMMY INSERTING - The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect. | 08-29-2013 |
20130316539 | METHOD FOR REDUCING MORPHOLOGICAL DIFFERENCE BETWEEN N-DOPED AND UNDOPED POLYSILICON GATES AFTER ETCHING - The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively. | 11-28-2013 |
20140077343 | DUMMY WAFER STRUCTURE AND METHOD OF FORMING THE SAME - A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity. | 03-20-2014 |
20140106475 | METHOD FOR ETCHING POLYSILICON GATE - A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other. | 04-17-2014 |
20140153000 | APPARATUS FOR DETECTING THE FLATNESS OF WAFER AND THE METHOD THEREOF - An apparatus for detecting the flatness of a top surface of a wafer includes a plurality of detector elements, a metal sink and a plurality of injection pipes. Each detector element comprises: a metal tube body, jet pipes, a light receiver and a light emitter. The method comprises: injecting ultra-pure water into the detector elements by injection pipes; emitting parallel beams along an upward-oblique direction, a preset Angle θ being formed between the beams and the vertical direction. The radiated beams above the water surface are incident on a receiver. The intensity of the beams received by the light receiver is used to calculate the height of the detecting point of the surface of the silicon wafer to determine the flatness condition of the wafer surface. The flatness of the photo-resist covered on the wafer surface can also be accurately measured by this method. | 06-05-2014 |
20150064930 | PROCESS OF MANUFACTURING THE GATE OXIDE LAYER - A process of manufacturing the gate oxide layer, which uses the wet oxidation by deuterium to form gate oxide layer, wherein the nitriding treatment is applied to formed gate oxide layer by high temperature annealing process, the stable Si-D bonds is formed on surface of the gate oxide layer to reduce silicon dangling bonds, which reduce the defect of the gate oxide interface and lower the interface defect density of the gate oxide layer and the charge density effectively to avoid NBTI, is provided. | 03-05-2015 |