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| 20080278540 | ATMOSPHEREIC PLASMA INKJET PRINTING APPARATUSES AND METHODS FOR FABRICATING COLOR FILTER USING THE SAME - Atmospheric plasma inkjet printing apparatus and methods for fabricating color filters using the same. The atmosphere plasma inkjet printing apparatus includes a nozzle plate having a first column of nozzles and a second column of nozzles. An inkjet printhead module corresponds to the first column of nozzles. An atmospheric plasma module is corresponds to the second column of nozzles. | 11-13-2008 |
| 20090064933 | FILM COATING SYSTEM AND ISOLATING DEVICE THEREOF - A film coating system for coating an object includes a working station and an isolating device. The object is disposed on the working station, and the isolating device is utilized to isolate the object. The isolating device includes a body generating a first power, a first working fluid, a second working fluid, a first guiding portion and a second guiding portion. The first guiding portion guides the first working fluid to pass through the body, thereby forming a first working region to coat the object thereon. The second guiding portion guides the second working fluid excited by the first power of the body to pass through the body, thereby forming a second working region to separate the first working region from the object. | 03-12-2009 |
| 20090133742 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - A solar cell includes a substrate, a conductor layer and an anti-reflection coating (ARC) layer. The substrate has a front side, a back side and a doped region adjacent to the front side. The conductor layer has a first portion embedded into the doped region and a second portion other than the first portion. The ARC layer is disposed on the front side of the substrate, the second portion of the conductor layer is disposed in the ARC layer, and the conductor layer has an exposed surface exposed out of the ARC layer. The exposed surface of the conductor layer is substantially flush with an exposed surface of the ARC layer. A method of manufacturing the solar cell is also disclosed. | 05-28-2009 |
| 20100025022 | FAN ASSEMBLY - A fan assembly for use in an electronic device is provided. The fan assembly includes a housing, a fan, a throttle valve, and a regulator. The housing has an outlet. The fan is disposed in the housing and adapted to provide an air current. The air current generates an air volume through the outlet. The throttle valve is movably disposed in the housing at the outlet. The regulator is connected to the throttle valve to control the movement of the throttle valve to adjust the size of the outlet. | 02-04-2010 |
| 20110094571 | SOLAR CELL WITH UPPER AND LOWER CONDUCTOR LAYERS STACKED TOGETHER - A solar cell includes a substrate, a lower conductor layer, an anti-reflection coating (ARC) layer and an upper conductor layer. The substrate has a front side, a back side and a doped region adjacent to the front side. The lower conductor layer has a first portion embedded into the doped region and a second portion other than the first portion. The ARC layer is disposed on the front side of the substrate and covers the lower conductor layer such that the second portion of the lower conductor layer is disposed in the ARC layer. The upper conductor layer has a first portion embedded into the ARC layer and a second portion other than the first portion of the upper conductor layer. The second portion of the upper conductor layer is exposed out of the ARC layer, and the upper conductor layer is electrically connected to the lower conductor layer. | 04-28-2011 |
| 20110120372 | PLASMA DEPOSITION APPARATUS AND DEPOSITION METHOD UTILIZING SAME - A plasma deposition apparatus is provided. The plasma deposition apparatus comprises a chamber. A pedestal is placed in the chamber. A plasma generator is placed in the chamber and over the pedestal. The plasma generator comprises a plasma jet for plasma thin film deposition having a discharge direction angle θ | 05-26-2011 |
| 20120282724 | METHOD OF MANUFACTURING SOLAR CELL WITH UPPER AND LOWER CONDUCTOR LAYERS STACKED TOGETHER - A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer. | 11-08-2012 |
| 20120288981 | METHOD OF MANUFACTURING SOLAR CELL WITH TWO EXPOSED SURFACES OF ARC LAYER DISPOED AT DIFFERENT LEVELS - A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer. | 11-15-2012 |
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| 20080267991 | IMMUNO-MODULATING ANTITUMOR ACTIVITIES OF GANODERMA LUCIDUM (REISHI) POLYSACCHARIDES - The present invention provides methods of modulating an immune response in an organism by administering medicinally active extracts and fractions, and a method for preparing the same by extracting and fractioning constituents from the tissue of components of | 10-30-2008 |
| 20090075397 | Method for characterizing sugar-binding interactions of biomolecules - This invention provides a donor bead for use in an assay, wherein the bead (a) is coated with a layer of hydrogel having directly or indirectly bound thereto a polyacrylamide-supported sugar or a polyacrylamide-supported glycan, and (b) comprises a photosensitizer which, upon excitation by laser light of a suitable wavelength, converts ambient oxygen to singlet state oxygen. This invention also provides an acceptor bead for use in an assay, wherein the bead (a) is coated with a layer of hydrogel having directly or indirectly bound thereto a polyacrylamide-supported sugar or a polyacrylamide-supported glycan, and (b) comprises a chemiluminescer and a fluorophore, whereby when the bead is contacted with singlet state oxygen, the singlet state oxygen reacts with the chemiluminescer which in turn activates the fluorophore so as to cause the emission of light of a predetermined wavelength. This invention further provides related kits, detection methods and characterization methods. | 03-19-2009 |
| 20100057356 | NAVIGATION SYSTEM CAPABLE OF UPDATING MAP DATA AND METHOD THEREOF - A navigation system includes a plurality of navigation devices and a server. The plurality of navigation devices is used for generating a plurality of position data respectively. Each navigation device generates at least one path data according to the plurality of position data and at least one corresponding electronic map and transmits the path data to the server. Then, the server calculates at least one optimum path data and updates the plurality of navigation devices according to the optimum path data. | 03-04-2010 |
| 20100113519 | 1,5-Dideoxy-1,5-imino-D-glucitol Compounds - 1,5-Dideoxy-1,5-imino-D-glucitol compounds as shown in the specification. Also disclosed is a method of treating a hexosaminidase-associated disease. | 05-06-2010 |
| 20110065758 | Compositions and assays for treatment and diagnosis of helicobacter pylori infection and conditions - Methods of diagnosing | 03-17-2011 |
| 20130119532 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 05-16-2013 |
| 20130175705 | Stress Compensation Layer for 3D Packaging - A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate. | 07-11-2013 |
| 20130187277 | CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER - A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings. | 07-25-2013 |
| 20130221522 | MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE - The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements. | 08-29-2013 |
| 20140167263 | Methods and Apparatus for Package with Interposers - Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well. | 06-19-2014 |
| 20140183746 | Zero Stand-Off Bonding System and Method - A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate. | 07-03-2014 |
| 20140191394 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 07-10-2014 |
| 20140264810 | Packages with Molding Material Forming Steps - A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface. | 09-18-2014 |
| 20140264849 | Package-on-Package Structure - A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer. | 09-18-2014 |
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| 20100219175 | ROTATABLE PLATE AND HEATING/COOLING ELEMENT IN PROXIMITY THERETO - An apparatus for selectively heating/cooling one or more substrates and establishing an approximately uniform temperature in the one or more substrates during a heating or cooling event is described. In one embodiment, the apparatus comprises a rotatable hot/cold plate onto which the one or more substrates are placed and a heating/cooling element disposed in close proximity to the rotatable hot/cold plate for selectively elevating/lowering the temperature of the one or more substrates. | 09-02-2010 |
| 20110115057 | DESIGN STRUCTURE FOR INTEGRATED CIRCUIT ALIGNMENT - A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region. | 05-19-2011 |
| 20120045192 | SYSTEM AND METHOD FOR IMPROVING IMMERSION SCANNER OVERLAY PERFORMANCE - System and method for improving immersion scanner overlay performance are described. One embodiment is a method of improving overlay performance of an photolithography immersion scanner comprising a wafer table having lens cooling water (“LCW”) disposed in a water channel therein, the wafer table having an input for receiving the LCW into the water channel and an output for expelling the LCW from the water channel. The method comprises providing a water tank at at least one of the wafer table input and the wafer table output; monitoring a pressure of water in the water tank; and maintaining the pressure of the water in the water tank at a predetermined level. | 02-23-2012 |
| 20120168751 | Integrated Circuit Test Units with Integrated Physical and Electrical Test Regions - A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region. | 07-05-2012 |
| 20120264063 | METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL - A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer. | 10-18-2012 |
| 20130239073 | METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL - Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer. | 09-12-2013 |
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| 20080283981 | Chip-On-Lead and Lead-On-Chip Stacked Structure - A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip. | 11-20-2008 |
| 20080310235 | SENSING CIRCUIT FOR MEMORIES - A memory apparatus includes a plurality of memory units, a sensing circuit and a bias-generating circuit. The plurality of memory units respectively outputs a data current to the sensing circuit, while the sensing circuit further includes a plurality of first transistors, a plurality of second transistors and a plurality of sensing amplifiers. In order to speed up the access time of the memory units, the bias-generating circuit rapidly provides a bias signal to the sensing circuit to turn on the first transistors of the sensing circuit. In the present invention, the sensing circuit uses a common reference voltage to reduce the circuit utilization area of the memory apparatus. | 12-18-2008 |
| 20090004620 | Surface treating device and surface treating method - A surface treating method for treating a tooth surface and a surface treating device thereof are provided. First, a working gas is filled into a tube. Next, a voltage is provided to the working gas for exciting the working gas into plasma. After that, the plasma is discharged through an opening of the tube for contacting the tooth surface. | 01-01-2009 |
| 20090169822 | ANTI-REFLECTION PLATE AND METHOD FOR MANUFACTURING ANTI-REFLECTION STRUCTURE THEREOF - A method for manufacturing an anti-reflection structure is provided. The method includes the following steps: First, a to-be-treated object is provided in a reactive area. Next, a plasma source is provided in the reactive area. Then, the plasma source is ionized to form plasma in atmospheric pressure. Next, the surface of the to-be-treated object is treated by plasma so as to form a plurality of micro-protuberances on the surface of the to-be-treated object. | 07-02-2009 |
| 20150010213 | IMAGE SURVEILLANCE SYSTEM AND IMAGE SURVEILLANCE METHOD - An image surveillance system and an image surveillance method are provided. The image surveillance method includes following steps. An image is captured, and at least one reference target is defined in the captured image. A monitored object in the image is identified. A distance between the monitored object and each of the at least one reference target is individually calculated. Whether to announce at least one warning is determined according to a relationship between at least one threshold and the distance. | 01-08-2015 |
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| 20120318480 | HEAT SINK HAVING JUXTAPOSED HEAT PIPES AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a heat sink having juxtaposed heat pipes and a method for manufacturing the same. The heat sink includes a base, a plurality of heat pipes and a pair of side strips. The base has a surface on which an open trough and an insertion trough on both sides of the open trough are provided. Each heat pipe has an evaporating section. The evaporating sections are juxtaposed in the open trough and adhered to each other. Each evaporating section has a planar surface. The side strips are fixed into the insertion troughs and protrude from the surface of the base. The planar surface of each evaporating section and the outer surface of each side strip are coplanar. By this structure, the thermal contact surface between the heat pipes and electronic heat-generating sources is increased, so that the heat-dissipating efficiency of the heat sink is improved. | 12-20-2012 |
| 20130025830 | HEAT SINK ASSEMBLY OF FIN MODULE AND HEAT PIPES - A heat sink assembly includes a fin module, heat pipes, and a pair of side plates. The fin module is composed of a plurality of fins and has a flat side formed with a trough and two recesses. Each of the heat pipes has an evaporation section. The evaporation sections are parallelly accommodated in the trough and in contact with each other. The side plates are separately fixed in the recesses and protrude from the flat side. The evaporation sections are formed with a flat surface coplanar with the side plates. By this arrangement, the thermal contact area between the heat pipes and a heat source is increased to thereby improve the heat-dissipating efficiency of the heat sink assembly. | 01-31-2013 |
| 20130037241 | HEAT PIPE WITH UNEQUAL CROSS-SECTIONS - The heat pipe of the invention includes an evaporation section and two condensation sections. The evaporation section is located at a part of the heat pipe. The two condensation sections are separately located at two opposite sides of the evaporation section. The evaporation section and the two condensation sections communicate with each other, and a peripheral size of the evaporation section is larger than that of each of the condensation sections. | 02-14-2013 |
| 20130048247 | HEAT PIPE MANUFACTURING METHOD AND HEAT PIPE THEREOF - A heat pipe includes a step pipe, a mesh, and a supporting component. The step pipe has an evaporating section and two condensing sections. The condensing sections are on the two ends of the step pipe, respectively. The evaporating section lies between the two condensing sections. The inner spaces of the two condensing sections and the evaporating section are interconnected. The peripheral dimension of the evaporating section is larger than the peripheral dimension of each of the condensing sections. The mesh is contained in the step pipe and located inside the evaporating section and the condensing sections. The supporting component is contained in the step pipe and wrapped in the mesh. The combination of these structures increases air's flow rate inside the heat pipe and improves the heat pipe's heat conduction efficiency. | 02-28-2013 |
| 20130048248 | HEAT PIPE MANUFACTURING METHOD AND HEAT PIPE THEREOF - A heat pipe includes a step pipe, a mesh, and a supporting component. The step pipe has an evaporating section and two condensing sections. The condensing sections are on the two ends of the step pipe, respectively. The evaporating section lies between the two condensing sections. The inner spaces of the two condensing sections and the evaporating section are interconnected. The peripheral dimension of the evaporating section is larger than the peripheral dimension of each of the condensing sections. The mesh is contained in the step pipe and located inside the evaporating section. The supporting component is contained in the step pipe and wrapped in the mesh. The combination of these structures increases air's flow rate inside the heat pipe and improves the heat pipe's heat conduction efficiency. | 02-28-2013 |
| 20130048249 | HEAT PIPE MANUFACTURING METHOD AND HEAT PIPE THEREOF - A heat pipe includes a step pipe and a sintered powder structure. The inner wall of the step pipe has a plurality of grooves. The step pipe has an evaporating section and two condensing sections. The condensing sections are on the two ends of the step pipe, respectively. The evaporating section lies between the two condensing sections. The inner spaces of the two condensing sections and the evaporating section are interconnected. The peripheral dimension of the evaporating section is larger than the peripheral dimension of each of the condensing sections. The sintered powder structure is bounded inside each of the condensing sections, improving the heat pipe's inner air flow rate and heat conduction efficiency. | 02-28-2013 |
| 20130118717 | HEAT-DISSIPATING DEVICE AND METHOD FOR FABRICATING THE SAME - A heat-dissipating device includes a plurality of fin plates arranged adjacently to each other, a heat pipe and a cover board. Each fin plate has at least two fixing tabs protruded from a top edge thereof, and a supporting portion formed between the fixing tabs. An accommodating space is defined between the supporting portion and the fixing tabs. The heat pipe has a portion disposed in the accommodating space. The cover board is formed with a plurality of slits corresponding to the fixing tabs. The fixing tabs pass through the slits and fixed to the cover board. | 05-16-2013 |
| 20130175008 | THIN HEAT PIPE - A thin heat pipe includes a thin hollow tube and a capillary structure. The capillary structure is formed in at least half of an inner wall of the thin hollow tube by a chemical etching process. | 07-11-2013 |
| 20130206369 | HEAT DISSIPATING DEVICE - A heat dissipating device includes a chamber body, a heat sink, a pipe, a first capillary structure and N vapor channels. The chamber body has an evaporation chamber and a compensation chamber, wherein the evaporation chamber has a vapor outlet and the compensation chamber has a liquid inlet. The heat sink is disposed on an outer wall of a first side of the chamber body and at least covers the compensation chamber. The pipe is installed within the heat sink, wherein a first end of the pipe is connected to the vapor outlet and a second end of the pipe is connected to the liquid inlet. The first capillary structure is formed in the evaporation chamber. The N vapor channels are formed in the first capillary structure. The N vapor channels and the compensation chamber are isolated by the first capillary structure. | 08-15-2013 |
| 20150013944 | HEAT DISSIPATING MODULE - A heat dissipating module includes a heat dissipating unit and a fan unit. The heat dissipating unit includes a plurality of heat dissipating fins sequentially stacked on top of one another. Each of the heat dissipating fins has a first end portion and a second end portion. The first end portion of each heat dissipating fin is divided into a first inclined airflow-guiding section and a second inclined airflow-guiding section, the first inclined airflow-guiding section of the first end portion of each heat dissipating fin is bent downward and slantwise, and the second inclined airflow-guiding section of the first end portion of each heat dissipating fin is bent upward and slantwise. The fan unit includes at least one fan adjacent to the heat dissipating unit for facing the first inclined airflow-guiding section and the second inclined airflow-guiding section of the first end portion of each heat dissipating fin. | 01-15-2015 |
| 20150059360 | LIQUID COOLING DEVICE HAVING DIVERSION MECHANISM - A liquid cooling device having a diversion mechanism, connected with a heat source, includes a thermoelectric cooler, a first water block, a second water block and a pump. The thermoelectric cooler has a cold end and a hot end. The first water block is disposed between the heat source and the cold end of the thermoelectric cooler. The second water block is disposed on one side of the hot end of the thermoelectric cooler. The pump connects the first water block and the second water block via a water pipe. Thereby, the temperature of an inner fluid is reduced and the overall heat dissipation effect of the device is improved. | 03-05-2015 |
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| 20130320463 | PACKAGE STRUCTURE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure includes: a substrate having a plurality of first conductive pads and a plurality of second conductive pads; an MEMS element disposed on the substrate; a cover member disposed on the MEMS element and having a metal layer formed thereon; a plurality of bonding wires electrically connected to the MEMS element and the second conductive pads of the substrate; a plurality of first wire segments, each having one end electrically connected to a corresponding one of the first conductive pads; and an encapsulant formed on the substrate and encapsulating the MEMS element, the cover member, the first wire segments and the bonding wires, wherein the other end of each of the first wire segments is exposed from the encapsulant. Compared with the prior art, the package structure of the present invention has improved overall yield and functionality. | 12-05-2013 |
| 20130341739 | PACKAGE STRUCTURE HAVING MICRO-ELECTRO-MECHANICAL SYSTEM ELEMENT AND METHOD OF FABRICATION THE SAME - A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections. | 12-26-2013 |
| 20140217605 | INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF - An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time. | 08-07-2014 |
