Entries |
Document | Title | Date |
20100333057 | Parametric Data-Based Process Monitoring for Adaptive Body Bias Control - Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage. | 12-30-2010 |
20110010683 | Trace Routing According To Freeform Sketches - Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed. With various implementations of the invention, the netlines are routed as traces by forming a container shape around the freeform sketch, approximating the geometry of the freeform sketch within the container shape, and routing traces within the container shape using the approximation of the freeform shape as a guide. | 01-13-2011 |
20110023002 | DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM - A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC. | 01-27-2011 |
20110029944 | ROUTING VARIANTS IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a schematic in an electronic design automation (EDA) application. During operation, the system obtains a source point and a destination point in the schematic from a user of the EDA application. Next, the system uses a line-probe-search technique to generate a set of route variants between the source point and the destination point. The system then provides the route variants to the user through a graphical user interface (GUI) in the EDA application and obtains, from the user, a selection of a route variant from the route variants through the GUI. Finally, the system uses the selected route variant as a route in the schematic. | 02-03-2011 |
20110055785 | METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias. | 03-03-2011 |
20110055786 | METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns effort levels to the set of routing rules, wherein a higher effort level for a routing rule indicates that a higher amount of resources are available to satisfy the routing rule. The system then modifies the routing solution to satisfy the routing rules based at least on the weights and the effort levels associated with the routing rules. | 03-03-2011 |
20110055787 | Interface Configuration System and Method - A computer-implemented method for designing an electrical interconnect device. The method comprises the steps of entering an instrument ID into a computer through an input device, entering a slot number corresponding to the instrument ID into the computer through the input device, entering an interface component identifier into the computer through the input device, associating the interface component identifier with the instrument ID and the slot number in a database in the computer, generating and displaying on a computer display a preview of a configuration of an electrical interconnect device, wherein the preview comprises a table showing the instrument ID, the slot number, the interface component identifier and an association between the interface component ID and the instrument ID, and wherein the interface component ID shown in the preview comprises a link to data associated with the interface component, and displaying in a separate window on the computer display the data associated with the interface component. | 03-03-2011 |
20110061038 | Pre-Route And Post-Route Net Correlation With Defined Patterns - A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output. | 03-10-2011 |
20110061039 | CIRCUIT BOARD DESIGN AID APPARATUS, CIRCUIT BOARD DESIGN AID METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORTING CIRCUIT BOARD DESIGN AID PROGRAM - The present disclosure includes a basic shield pattern element generation section configured to generate a basic shield pattern element based on a geometry of the pattern element and a preset pattern generation condition; a prohibition region generation section configured to generate a prohibition region based on a geometry of an element for which a clearance check is to be performed located around the wiring pattern and a clearance condition between the element for performing a clearance check and the wiring pattern; and a shield pattern geometry generation section configured to generate the shield pattern by excluding the geometry of the prohibition region from a geometry of the basic shield pattern element, thereby improving the design efficiency and design quality by efficiently generating shield patterns even when an element for which a clearance check is to be performed is present in the vicinity of the wiring pattern. | 03-10-2011 |
20110066996 | SCHEMATIC WIRE ANNOTATION TOOL - A method of automating circuit design is provided and includes storing one or more circuit design schematics in a memory, providing, by way of an interface, a plurality of search parameters for searching for nets of the schematics in the memory, searching for nets of the schematics in the memory in accordance with search parameters input into the interface and presenting, by way of the interface, information associated with a net matching the received search parameters. | 03-17-2011 |
20110072408 | METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES - A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures ( | 03-24-2011 |
20110078648 | MODULAR ROUTING FABRIC USING SWITCHING NETWORKS - A routing fabric using multiple levels of switching networks along with associated routing matrices to allow a more uniform and shorter interconnection or routing path among logic modules or routing modules compared with those in the conventional designs. The resulting routing fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc. | 03-31-2011 |
20110093828 | Pin-out Designation Method for Package-Board Codesign - A pin out designation method for package board codesign having steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns, use the pin patterns to construct multiple pin blocks, group the pin blocks around four sides of a chip and adjusts the pin blocks into a minimized package size of the chip. | 04-21-2011 |
20110107289 | METHOD OF IMPLEMENTING PHYSICALLY REALIZABLE AND POWER-EFFICIENT CLOCK GATING IN MICROPROCESSOR CIRCUITS - A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions. | 05-05-2011 |
20110119648 | ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY - A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology. | 05-19-2011 |
20110179395 | Distributed Pipeline Synthesis for High Level Electronic Design - High level synthesis techniques are disclosed, particularly, techniques for synthesizing pipelines having distributed control. In some implementations, an algorithmic description for a device design is first identified. Subsequently, a data-flow representation of the algorithmic description is generated; the data-flow representation including a plurality of operations. The plurality of operations are then scheduled, following which, a plurality of pipeline stages are generated corresponding to ones of the plurality of operations. Control logic for the pipeline stages may then be generated, followed by the generation of a netlist representation of the electronic device design based in part upon the scheduling of operations and pipeline stages. | 07-21-2011 |
20110191739 | CIRCUIT DESIGN METHOD, CIRCUIT DESIGN SYSTEM, AND RECORDING MEDIUM - A circuit design method for interconnecting a plurality of modules includes: a step of acquiring port information including input ports and output ports of the plurality of modules; a step of acquiring instance information indicating that, among the plurality of modules, there is a module including a plurality of instances having the same function; and a step of associating the input ports and the output ports based on the port information and the instance information to interconnect the plurality of modules. | 08-04-2011 |
20110276936 | METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY - A method for analog placement and global routing considering wiring symmetry performs a layout for a circuit which is described by a netlist having a set of devices and wires. First, the method inputs the netlist, and each device thereof has a design constraint and a corresponding priority. Based on the priorities, it performs a sorting on the devices to establish a constraint library. Then, based on the design constraint and corresponding priority of each device, the method establishes a hierarchical constraint tree. According to the hierarchical constraint tree, the method performs placement of each device, wherein possible shape of each device is represented by a shape curve. For each placement of the device, the method calculates a corresponding cost function. Then, it selects an optimum placement of the device according to the cost functions. The method establishes an RSMT for each wire and then performs an analog routing. | 11-10-2011 |
20110296366 | METHOD OF MAKING ROUTABLE LAYOUT PATTERN USING CONGESTION TABLE - A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit uses a congestion map. First, congestion zones are identified in a congestion map generated by an Electronic Design Automation (EDA) application. Next, routing tracks data corresponding to bounding boxes belonging to the congestion zones are used to calculate values of average vertical and horizontal congestion. Subsequently, a value of modified standard cell density is calculated based on the values of average vertical and horizontal congestion, and an unmodified standard cell density. The dimensions of a layout pattern unit are calculated using the value of the modified standard cell density and the width of standard cells. Various layout pattern units then are placed adjacent to one another to form a standard cell layout pattern. | 12-01-2011 |
20110302545 | DETAILED ROUTABILITY BY CELL PLACEMENT - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing. | 12-08-2011 |
20110314436 | AWARE MANUFACTURING OF AN INTEGRATED CIRCUIT - Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout. In some embodiments, this selection entails selecting width and/or spacing of routes along different directions on each particular layer of the IC layout. | 12-22-2011 |
20120060139 | Using Port Obscurity Factors to Improve Routing - An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number of routing tracks that may be connectable to that port. Routing priorities for the nets of the netlist may then be created using the port obscurity factors of the ports in the net. Routing may then be done in the order determined by the routing priority list and the generated layout information stored in a computer useable medium. In some cases, routing may be performed using multiple routing passes where a new routing priority list may be calculated for each routing pass. | 03-08-2012 |
20120096422 | RE-ROUTING METHOD FOR CIRCUIT DIAGRAM - A re-routing method for a circuit diagram includes the following steps. At least one pair of the signal lines is obtained from a routed circuit diagram. The routed circuit diagram is adapted to be laid out on a substrate of a Printed Circuit Board (PCB). The substrate includes warp wires and weft wires. At least one pair of the signal lines includes two signal lines in parallel. The pair of signal lines includes several pairs of line segments. It is determined whether at least one pair of parallel line segments exists in the pairs of line segments parallel to the warp or weft wires. If at least one pair of parallel line segments exists, at least one pair of parallel line segments on the routed circuit diagram is replaced with several pairs of 10-degree lines. Respective angle between the 10-degree lines and the warp or weft wires are 10 degrees. | 04-19-2012 |
20120151430 | STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL - A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout. | 06-14-2012 |
20120198407 | AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE - A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles. | 08-02-2012 |
20120246607 | System and Method for Series and Parallel Combinations of Electrical Elements - A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process. | 09-27-2012 |
20120254819 | CIRCUIT DIAGRAM CREATION SUPPORT METHOD AND APPARATUS - The disclosed method includes: generating data of a first circuit diagram by disposing a block that represents a connection relationship between first branch lines included in a first bus line in a second circuit diagram and second branch lines included in a second bus line to be connected to the first bus line in the second circuit diagram so as to connect the first bus line with the second bus line through the block, wherein the block represents that the connection relationship identified by connection relationship data is depicted in detail in a lower-layer than a layer of the block; and generating display data including the connection relationship data and the first circuit diagram to output the generated display data. | 10-04-2012 |
20130019220 | METHOD FOR GENERATING WIRING PATTERN DATAAANM MARUYAMA; TakashiAACI KotoAACO JPAAGP MARUYAMA; Takashi Koto JPAANM Sugatani; ShinjiAACI HachiohjiAACO JPAAGP Sugatani; Shinji Hachiohji JP - A method includes connecting in a wiring area a plurality of basic block patterns which include a plurality of track patterns extending to one direction and being disposed at a prescribed pitch in an intersection direction intersecting the one direction to generate a plurality of parallel wiring patterns, each of which includes the track patterns connected together; generating a wiring route running on a track pattern; cutting away a track pattern terminal end, on which no wiring route runs, out of track pattern terminal ends of a track pattern including a route end of the wiring route and an adjacent track pattern connected to a track pattern start end of the track pattern concerned; and generating a wiring pattern data including a block pattern identifier corresponding to a basic block pattern out of the basic block patterns in the wiring area and a layout position of the basic block pattern. | 01-17-2013 |
20130031524 | ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS - Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time. | 01-31-2013 |
20130055189 | METHOD FOR IMPLEMENTING CIRCUIT DESIGN FOR INTEGRATED CIRCUIT AND COMPUTER READABLE MEDIUM - In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length. | 02-28-2013 |
20130125078 | Interactive Routing Editor with Symbolic and Geometric Views for Integrated Circuit Layout - An automated system, and method of operating the same, for interactively routing interconnections in a layout of an integrated circuit. Interconnections among subchips in the integrated circuit, specified by a netlist, are displayed by the system by way of airlines. The system provides a symbolic view of the bus, showing a representative wire of the bus, such as that associated with the least-significant or most-significant bit position in the bus. The physical routing of the representative wire is interactively defined, using orthogonal wire segments in selected conductor levels. Bus properties, for example including bit pitch, wire pitch, LSB/MSB, and a direction of expansion, are associated with the routing data for each segment of the representative wire. The combination of the routing data and the bus property data enable building of the entire bus from the interactive routing of the representative wire in the symbolic view. | 05-16-2013 |
20130125079 | ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE - A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies. | 05-16-2013 |
20130132921 | COMPUTER PRODUCT, CIRCUIT DESIGN METHOD AND APPARATUS - A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data. | 05-23-2013 |
20130179853 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 07-11-2013 |
20130191804 | GRADUATED ROUTING FOR ROUTING ELECTRODES COUPLED TO TOUCH SENSOR ELECTRODES TO THEREBY BALANCE CAPACITANCE ON THE TOUCH SENSOR ELECTRODES - A system and method for balancing the capacitive charge on touch sensor electrodes so that every two adjacent routes have the same capacitance as any other adjacent two routes, wherein routing electrodes are spaced further and further apart, or graduated, as they get longer, to thereby balance the capacitance on the touch sensor electrodes without having to add or subtract an offset from each touch sensor electrode. | 07-25-2013 |
20130298100 | Graphical User Interface for Display of System Resistance - Techniques for determining resistances of analog routes in electronic designs are described herein. In an example embodiment, a computer system receives first user input that indicates, in a user interface, a first component in an electronic design. The electronic design has been placed and routed for a programmable target device. The computer system receives second user input that selects, in the user interface, a particular component from one or more second components of the electronic design, where the one or more second components have analog connectivity to the first component. The computer system determines a resistance value of an analog route between the first component and the particular component, and displays the resistance value in association with the analog route in the user interface. | 11-07-2013 |
20130305205 | Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture - The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established. | 11-14-2013 |
20130318489 | ACTIVE NET AND PARASITIC NET BASED APPROACH FOR CIRCUIT SIMULATION AND CHARACTERIZATION - A computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. Active nets are interconnections between circuit components showing a level of activity during the simulation. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a part of the circuit design, where the part determined by the active nets. The parasitic netlist is a list of parasitic nets, or unwanted circuit interconnections that are unavoidable adjuncts of the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the part of the circuit design. | 11-28-2013 |
20130318490 | METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS - A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency tradeoffs, while maintaining correct asymptotic behavior at both high and low frequency limits. In the framework of the model it is shown that a major effect is pronounced frequency dependent silicon substrate induced dispersion and loss effects, which is considered in through silicon via (TSV) parallel Y-element parameters, including capacitance and conductance. | 11-28-2013 |
20140033155 | SYSTEMS AND METHODS FOR GENERATING A HIGHER LEVEL DESCRIPTION OF A CIRCUIT DESIGN BASED ON CONNECTIVITY STRENGTHS - Provided are systems and methods for generating a higher level description of a circuit design comprising a plurality of interface instances. One or more buckets for each source instance with respect to each destination instance included in the circuit design are generated, and then the one or more buckets are sorted based on a number of bucket entries in each bucket. One or more interface instances are generated based on the sorted buckets. The higher level description of the circuit design is generated based on the one or more interface instances. | 01-30-2014 |
20140068541 | INTERCONNECT STRUCTURES AND METHODS FOR BACK END OF THE LINE INTEGRATION - A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. | 03-06-2014 |
20140075405 | METHOD OF ANALYZING INTERCONNECT FOR GLOBAL CIRCUIT WIRES - Systems, methods, and other embodiments associated with analyzing interconnects for global wires of a circuit are described. In one embodiment, for a target wire in a circuit design, a method includes determining an inductance value and a capacitance value for parallel wires to the target wire. The method then calculates a second capacitance value for non-parallel wires to the target wire and calculates an estimated inductance value for the non-parallel wires based on the second capacitance value. A circuit model for the target wire may then be generated using the inductance and capacitance values. | 03-13-2014 |
20140096101 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has: a first signal line formed in a first wiring layer formed on a semiconductor substrate, and disposed in a first direction; first and second shield lines formed in the first wiring layer, disposed on both sides of the first signal line in the first direction, and given a first fixed potential; and a plurality of third shield lines formed in a second wiring layer formed on the semiconductor substrate, disposed with a first wiring width and at a first wiring interval in a second direction almost orthogonal to the first direction in a manner to partially overlap with each of the first signal line and the first and second shield lines, and given the first fixed potential. | 04-03-2014 |
20140123094 | PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN - A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure. | 05-01-2014 |
20140181777 | AUTOMATIC CLOCK TREE ROUTING RULE GENERATION - Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing. | 06-26-2014 |
20140208285 | SELF-ALIGNED DOUBLE PATTERNING VIA ENCLOSURE DESIGN - A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so. | 07-24-2014 |
20140223402 | Multi-Board Design Apparatus, Multi-Board Design Method, Program and Computer-Readable Recording Medium - In order to always maintain connection relationships between substrates of the multi-board, a multi-board design apparatus for designing a multi-board comprising a plurality of substrates which are electrically connected is made to have: setting means by which a designer sets connection information indicating a connection relationship between each substrate configuring the multi-board; modification information detection means by which, when editing in an arbitrary substrate configuring the multi-board, modified content resulting from the editing is detected as modification information; and connection information modification means which, on the basis of the modification information which has been detected by the modification which has been detected by the modification information detection means, modifies the connection information which has been set in the setting means so as to maintain electrical connection relationships between each of the substrates in the multi-board. | 08-07-2014 |
20140282345 | VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS - A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison. | 09-18-2014 |
20140282346 | MESH PLANES WITH ALTERNATING SPACES FOR MULTI-LAYERED CERAMIC PACKAGES - An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package, using the mesh plane with alternating spaces, generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane. A method, computer system, and program code that generate the design for the multi-layered ceramic package are also disclosed. | 09-18-2014 |
20140298284 | STANDARD CELL DESIGN LAYOUT - Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant. | 10-02-2014 |
20150026656 | UPDATING PIN LOCATIONS IN A GRAPHICAL USER INTERFACE OF AN ELECTRONIC DESIGN AUTOMATION TOOL - Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain. | 01-22-2015 |
20150033200 | LSI DESIGNING APPARATUS, LSI DESIGNING METHOD, AND PROGRAM - An apparatus and method that improve design efficiency when designing an LSI. A selector module generating section inputs IP connection information describing input/output flows of signals between IPs included in an LSI to be designed, analyzes the inputted IP connection information, and generates a selector module of a selector that matches the input/output flows of signals between IPs described in the IP connection information. A macro module generating section generates a macro module in which relationships between the selector and function blocks are indicated, using the selector module generated by the selector module generating section. | 01-29-2015 |
20150067630 | METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAM - A method for designing a semiconductor integrated circuit includes: determining, by a designing device, a first wiring over which a signal is propagated and a second wiring which is not used for a propagation of the signal among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, the second wiring to be used as a wiring for storing electrical charge for an electrical charge recycling of the first wiring using the most number of the first wiring in a range that satisfies a timing constraint based on an operation rate of the signal propagated over the first wiring and a delay time of the first wiring. | 03-05-2015 |
20150067631 | DESIGN METHOD OF REPEATER CHIP - A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit. | 03-05-2015 |
20150331989 | METAL INTERCONNECT MODELING - A method performed by a computing system for modeling metal routing in a circuit design includes extracting physical parameters of a metal interconnect and substrate for the circuit design, determining a substrate capacitance value from a database, the substrate capacitance being at a maximum frequency of a frequency range to be simulated, modeling the metal interconnect with a symmetric lumped transmission line model, defining a substrate resistance value for the symmetric lumped transmission line model to be such that the substrate resistance value multiplied by the substrate capacitance value is within a range of about 100-6000 ohm femtofarads, and simulating the symmetric lumped transmission line model across the frequency range using the substrate resistance value as the substrate resistance of the symmetric lumped transmission line model. | 11-19-2015 |
20150370954 | TRIANGULAR ROUTING FOR HIGH SPEED DIFFERENTIAL PAIR LENGTH MATCHING - A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees. | 12-24-2015 |
20160070840 | INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS - A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC. | 03-10-2016 |
20160110490 | SYSTEM AND METHOD FOR OBSTACLE-AVOIDING SIGNAL BUS ROUTING - Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined. | 04-21-2016 |