Entries |
Document | Title | Date |
20100318953 | PLATFORM PROGRAMMING FOR MASS CUSTOMIZATION - This disclosure describes a configuration data structure ( | 12-16-2010 |
20110209110 | Tensor Transmission-Line Metamaterials - Tensor transmission-line metamaterial unit cells are formed that allow the creation of any number of optic/electromagnetic devices. A desired electromagnetic distribution of the device is determined, from which effective material parameters capable of creating that desired distribution are obtained, for example, through a transformation optics/electromagnetics process. These effective material parameters are then linked to lumped or distributed circuit networks that achieve the desired distribution. | 08-25-2011 |
20110302542 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 12-08-2011 |
20120030639 | COMPUTING DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES - A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards. | 02-02-2012 |
20120110529 | CLOCK DOMAIN CROSSING BUFFER - Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay. | 05-03-2012 |
20120131526 | POWER-GATED RETENTION FLOPS - A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on. | 05-24-2012 |
20120167026 | ASSEMBLY AND CIRCUIT STRUCTURE FOR MEASURING CURRENT THROUGH AN INTEGRATED CIRCUIT MODULE DEVICE - An assembly and circuit structure for measuring current through an integrated circuit (IC) module device is disclosed. The circuit structure includes a power supply, at least one IC module device, at least one amplifier, and a resistive washer. The power supply can be configured to generate direct or alternating current. The at least one IC module device having a pair of terminals can be configured to receive the generated current. The at least one amplifier can be configured to measure the amount of current that flows through the IC module device. The at least one amplifier may be electrically coupled to a resistor. Also, a resistive washer may be configured to oppose current flow through the at least one IC module so as to redirect current to flow through the resistor. | 06-28-2012 |
20120180013 | METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN - The present disclosure is directed to a method for extracting information for a circuit design. The method includes establishing a reflexive relationship between a plurality of design shapes corresponding to a plurality of circuit components in the circuit design. The method includes receiving a design change for at least one design shape of the plurality of design shapes. The method includes identifying a set of changed shapes, a set of affected shapes, and a set of involved shapes. The method includes extracting at least one of a capacitance, an inductance or a resistance for the updated circuit design based on at least one of the set of changed shapes, the set of affected shapes and the set of involved shapes. The method includes updating the plurality of circuit components in the circuit design based on at least one of the set of changed shapes and the set of affected shapes. | 07-12-2012 |
20120331433 | INTEGRATED CIRCUIT STACK - The invention relates to an integrated circuit stack ( | 12-27-2012 |
20130067424 | LIFE PREDICTION METHOD OF ELECTRONIC DEVICE AND DESIGN METHOD OF ELECTRONIC DEVICE USING THE METHOD - A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction. | 03-14-2013 |
20130326443 | METHOD OF GENERATING A RECIPE FOR A MANUFACTURING TOOL AND SYSTEM THEREOF - There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation. | 12-05-2013 |
20140007029 | METHOD FOR ANALYZING PLACEMENT CONTEXT SENSITIVITY OF STANDARD CELLS | 01-02-2014 |
20140215419 | ANALYTICAL MODEL FOR PREDICTING CURRENT MISMATCH IN METAL OXIDE SEMICONDUCTOR ARRAYS - A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom. | 07-31-2014 |
20140282323 | PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN - A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions. | 09-18-2014 |
20150020039 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 01-15-2015 |
20150100934 | INTEGRATED TRANSFORMER SYNTHESIS AND OPTIMIZATION - A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion. | 04-09-2015 |
20160055282 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via. | 02-25-2016 |
20160063163 | ARRAYS WITH COMPACT SERIES CONNECTION FOR VERTICAL NANOWIRES REALIZATIONS - An integrated circuit design tool includes a functional cell library. An entry in the cell library comprises a specification of the cell. Entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library comprising a specification of a cell including a plurality of transistors and an interconnect. At least two transistors in the plurality are in series via at least the interconnect. The transistors and the interconnect can be vertically oriented to support vertical current through a vertical channel relative to the substrate. | 03-03-2016 |
20160378897 | MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY - A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location. | 12-29-2016 |
20190147135 | THERMAL ESTIMATION DEVICE AND THERMAL ESTIMATION METHOD | 05-16-2019 |
20220138381 | MACHINE LEARNING METHOD AND COMPUTING SYSTEM - An information processing apparatus calculates a value based on the lengths of wires included in inner layers selecting the inner layers other than outermost layers and layers adjacent to the outermost layers from among a plurality of layers included in circuit data. The information processing apparatus generates training data including first layer data corresponding to the patterns of the outermost layers, second layer data corresponding to the patterns of the layers adjacent to the outermost layers, and the value based on the lengths of the wires. The information processing apparatus trains a machine learning model by using the training data. | 05-05-2022 |
20220138392 | CURVILINEAR DESIGN ADJUSTMENT AT ACUTE-ANGLED TIP - A system and method for adjusting the shapes of polygons in a design. In some embodiments, the method includes inverting a first layer of the design, the first layer comprising one or more polygons, the inverting of the first layer forming a region complementary to the union of the polygons of the first layer, and including one or more inverse polygons. The method may further include performing a rounding operation on a first corner of a first inverse polygon of the one or more inverse polygons, to form a modified polygon. | 05-05-2022 |