Class / Patent application number | Description | Number of patent applications / Date published |
716119000 |
Placement or layout
| 326 |
716125000 |
With partitioning | 5 |
20110055784 | MULTI-THREADED GLOBAL ROUTING - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During operation, the system determines bounding boxes for nets, and associates nets with partitions, wherein a partition associated with a net encloses the net's bounding box. Then, the system routes nets in non-overlapping partitions in parallel. Next, the system adjusts bounding boxes of nets which need to be routed again, and routes these nets in the next iteration. In some embodiments, the system may use a cost function to guide the routing process. The system may adjust the weights of one or more terms of the cost function as the routing process progresses. Specifically, the system may increase the importance of a congestion term as the routing process progresses. | 03-03-2011 |
20110066995 | ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS - A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media. | 03-17-2011 |
20110289469 | VIRTUAL INTERCONNECTION METHOD AND APPARATUS - A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique. | 11-24-2011 |
20130346938 | POST-PLACEMENT CELL SHIFTING - A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-26-2013 |
20140082579 | ARCHITECTURAL PHYSICAL SYNTHESIS - Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform. | 03-20-2014 |
Entries |
Document | Title | Date |
20110083115 | ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN - A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations. | 04-07-2011 |
20110113397 | LAYOUT STRUCTURE OF MOSFET AND LAYOUT METHOD THEREOF - A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction. | 05-12-2011 |
20110191737 | GENERATION OF ASYMMETRIC CIRCUIT DEVICES - A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels. | 08-04-2011 |
20120297353 | PATTERNING METHOD AND SEMICONDUCTOR DEVICE - A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate. | 11-22-2012 |
20120317532 | INTEGRATED CIRCUIT DESIGN TOOL APPARATUS AND METHOD OF DESIGNING AN INTEGRATED CIRCUIT - An integrated circuit design tool apparatus including a processing resource arranged to support a circuit simulator, a circuit simulator interrogator, and a well distance calculator is provided. The circuit simulator interrogator communicates first and second well distance values separately to the circuit simulator and receives first and second performance parameter value back from the circuit simulator interrogator in response. The well distance calculator determines a performance parameter limit value, and projects, substantially linearly, a well distance change value in respect of the performance parameter limit value using the first and second performance parameter values, the performance parameter limit value and a trial well distance change value. Also, a well distance change characterising equation using the well distance change value projected is used in order to obtain the minimum well distance value associated with the performance parameter limit value. | 12-13-2012 |
20130097570 | METHOD OF INSERTING DUMMY PATTERNS - A method of inserting dummy patterns is provided. The method includes: determining an applicable area in which dummy patterns shall be inserted and an inapplicable area in which dummy patterns shall not be inserted on a chip; and inserting dummy patterns starting from one side of the inapplicable area and arranging the inserted dummy patterns into circles. The method of the present invention ensures that dummy patters are preferentially inserted around the device that requires protection by dummy patterns, so that good uniformity of chip pattern densities is guaranteed and within-wafer uniformity is improved, thus improving the yield and performance of semiconductor devices. | 04-18-2013 |
20150046893 | TECHNIQUES FOR ELECTROMIGRATION STRESS MITIGATION IN INTERCONNECTS OF AN INTEGRATED CIRCUIT DESIGN - A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub. | 02-12-2015 |
20150082266 | METHOD OF DESIGNING INPUT/OUTPUT CIRCUIT - According to one embodiment, a method of designing an input/output circuit which includes input/output cells of a semiconductor device is provided. The method uses a computer which has a schematic generating unit and a layout generating unit. By the schematic generating unit, a symbol of one input/output cell is arranged on a schematic diagram so as to generate schematic data. The symbol has pins including a through pin, a power pin and information indicating power rails. The symbol is capable of being set so as to connect the through pin of the symbol to a pin of a symbol of another input/output cell or to the power pin of the symbol of the one input/output cell itself selectively. After generating the schematic data, the connection is set. Further, layout data is generated by the layout generating unit. | 03-19-2015 |
20150143319 | DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL - The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section. | 05-21-2015 |