Entries |
Document | Title | Date |
20100281452 | LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM, AND LAYOUT DESIGN APPARATUS - It is desired to make it possible to generate a layout whose chip area is small for a semiconductor integrated circuit having a plurality of power supply systems in an internal circuit region. Power supply line of a first power supply is generated in an internal circuit region. Each of primitive cells is generated so that it is connected to the power supply line. It is checked whether or not the timing of a signal supplied to each of the primitive cells from the power supply line of the first power supply satisfies a prescribed criterion. A line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply is generated for at least one power supply separation object cell being at least one of the primitive cells after it is checked that the prescribed criterion is satisfied. | 11-04-2010 |
20100287524 | METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION - A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files. | 11-11-2010 |
20110010682 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 01-13-2011 |
20110029943 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT AND RECORDING MEDIUM - A method for manufacturing a semiconductor integrated circuit includes: generating first data by performing floor planning based on semiconductor integrated circuit information and monitor path circuit information; generating second data by arranging at least one monitor path flip-flop and at least one monitor path circuit element in the first data based on monitor path position information; generating third data by performing arrangement or wiring based on the second data; generating a first timing analysis result by performing timing analysis on data corresponding to the semiconductor integrated circuit information of the third data; generating a second timing analysis result by performing timing analysis on data corresponding to the monitor path circuit information of the third data; modifying the semiconductor integrated circuit information by comparing the first timing analysis result with the second timing analysis result; and manufacturing the semiconductor integrated circuit based on the modified semiconductor integrated circuit information. | 02-03-2011 |
20110035716 | DESIGN SUPPORT PROGRAM, DESIGN SUPPORT DEVICE, AND DESIGN SUPPORT METHOD - A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination. | 02-10-2011 |
20110088007 | BALL GRID ARRAY AND CARD SKEW MATCHING OPTIMIZATION - A method, system, and computer storage device simultaneously compare the timing of conductive signal paths in a substrate and a printed circuit board to achieve a predetermined signal timing goal. Specifically, the method automatically calculates a substrate-based length of time it will take a signal to pass within each substrate conductor (within a conductor group) and automatically calculates a board-based length of time it will take a signal to pass within each of board conductors (within the conductor group). The method automatically adds the substrate-based length of time and the board-based length of time for each of the combined substrate-board conductors to produce a combined timing for each of the combined substrate-board conductors. The method automatically compares the combined timing of each the combined substrate-board conductors to determine whether the combined substrate-board conductors pass signals within a predetermined timing variance limit. | 04-14-2011 |
20110093827 | SEMICONDUCTOR DEVICE DESIGN METHOD - There is provided a semiconductor device design method capable of achieving optimal layout design. For example, from the entire semiconductor device, a plurality of seeds which are flip-flops are set uniformly. In the first trace, the effective range (node) of each seed is expanded in parallel so that the respective objective function values (including difficulty levels of timing convergence) of the nodes are equalized. Then, in the first merge, adjacent seeds are merged as appropriate so that the number of nodes decreases to a certain rate, and a total cost containing the difficulty level of each node and the difficulty level of circuits remaining in the entire semiconductor device is calculated. Until the total cost worsens, as in the first trace and merge, the second trace and merge, the third trace and merge, . . . are performed. Based on optimal division units thereby determined, floorplan, division layout, and the like are performed. | 04-21-2011 |
20110107285 | Timing analysis apparatus, timing analysis method, and timing analysis program - A timing analysis apparatus includes a circuit data acquisition section for acquiring circuit data; a path setup section for setting up two paths extending from a clock source to a clock supply destination as a first path and a second path in accordance with the circuit data; a distance calculation section for calculating a coupling point-to-point distance between a first output terminal of the mesh section on the first path and a second output terminal of the mesh section on the second path; a global coefficient decision section for determining, in accordance with the coupling point-to-point distance, a global coefficient that indicates the degree of variation in time period from the moment when a clock signal is issued from the clock source until the moment when the clock signal reaches each output terminal of the mesh section; and a timing verification section for verifying clock supply timing on each of the first path and the second path in accordance with the global coefficient. | 05-05-2011 |
20110113395 | Method, Electronic Design Automation Tool, Computer Program Product, and Data Processing Program for Creating a Layout for Design Representation of an Electronic Circuit and Corresponding Port for an Electronic Circuit - A method for creating a layout for design representation of an electronic circuit with at least one port. The method includes segmenting the at least one port in the design representation into different regions, classifying the different regions of the at least one port according to timing and/or electronic and/or layout characteristics, assigning a priority for each classified region of the at least one port according to rules based on the timing and/or electronic and/or layout characteristics, and routing the design representation by accessing at least one of the classified regions of the port according to an order of the assigned priorities. | 05-12-2011 |
20110113396 | DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF ESTIMATED VALUE - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 05-12-2011 |
20110185327 | DELAY CALCULATING METHOD IN SEMICONDUCTOR INTEGRATED CIRCUIT - An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained. | 07-28-2011 |
20110246956 | WIRE SPACING VERIFICATION METHOD, WIRE SPACING VERIFICATION APPARATUS, AND COMPUTER-READABLE MEDIUM - A wire-spacing verification method for a computer includes calculating a characteristic impedance of each wire model disposed in a substrate model on a basis of a propagation rate of a signal in the wire model and rise time or fall time of an element model for transmitting the signal, calculating a reference impedance for predetermined sections, creating a distribution map in a direction of a section length with respect to the characteristic impedance of each of the sections for which the reference impedance is calculated, calculating an index indicating a degree of mismatch with the reference impedance, on a basis of the created distribution map, and making an approval/denial determination on the wire model on a basis of the index. | 10-06-2011 |
20110252390 | AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
20110252391 | INTEGRATED CIRCUIT MANUFACTURING METHOD, DESIGN METHOD AND PROGRAM - An integrated circuit manufacturing method comprising: calculating a threshold value from a value of a parameter which characterizes at least a part of a design pattern shape of a transistor on the target path; calculating a difference between the calculated threshold value and a target threshold value; calculating a change quantity of a gate length corresponding to the difference between the threshold value and the target threshold value according to the functional relation between the threshold value of the transistor and the gate length, which is determined based on the empirical value or the experimental value; reducing, by the change quantity, the gate length of the transistor on the target path; and manufacturing an integrated circuit on the basis of design information of the circuit including the transistor of which the gate length is changed. | 10-13-2011 |
20110289465 | Statistical On-Chip Variation Timing Analysis - A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results. | 11-24-2011 |
20110302543 | PATTERN DESIGNING METHOD, PATTERN DESIGNING PROGRAM AND PATTERN DESIGNING APPARATUS - A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters. | 12-08-2011 |
20110307853 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A path (different power-supply path) in which verification objective paths pass through two or more power domains is searched from a netlist and power-supply information, and delay-coefficient additional determination is performed in the different power-supply path. In this step, from voltage conditions in each power domain, a voltage condition under which the timing analysis result is most negative is detected, it is determined whether or not the delay coefficient is added for the voltage condition, and the delay coefficient is added. When the delay coefficient is added, the delay coefficient obtained in consideration of the power-supply voltage variation for the delay of the cell belonging to the different power-supply path is extracted from the delay-coefficient information, and is added to the delay value calculated based on the library. Then, based on the delay value to which the delay coefficient is added, the static timing verification is performed. | 12-15-2011 |
20110314433 | COMPUTER PRODUCT, APPARATUS, AND METHOD FOR SUPPORTING DESIGN - A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction. | 12-22-2011 |
20110314434 | COMPUTER PRODUCT, APPARATUS, AND METHOD FOR SUPPORTING DESIGN - A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction. | 12-22-2011 |
20120005642 | Retiming of Multirate System - Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality. | 01-05-2012 |
20120011483 | METHOD OF CHARACTERIZING REGULAR ELECTRONIC CIRCUITS - A methods of characterizing a regular electronic circuit and using a parameterized model of an electronic circuit to create a model for another electronic circuit. In one embodiment, the method of characterizing includes: (1) characterizing fewer than all sub-circuits associated with input and output pins of the circuit to yield data regarding the sub-circuits, (2) generating a data file containing the data, the data file constituting an expandable parameterized model of the circuit. | 01-12-2012 |
20120011484 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS - A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool. | 01-12-2012 |
20120017189 | ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
20120017190 | IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME - An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit. | 01-19-2012 |
20120023469 | IMPLEMENTING TIMING PESSIMISM REDUCTION FOR PARALLEL CLOCK TREES - A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay. | 01-26-2012 |
20120023470 | METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT - An integrated circuit designing apparatus for designing a semiconductor integrated circuit. The designing includes verifying the timing based on delay information included in the design data, the delay information is extracted from results of placing and wiring of the semiconductor integrated circuit; determining whether each value of hold-time errors generated as a result of the timing verification is smaller than a criteria value; extracting, when the value of a hold-time error is smaller than the criteria value, a wiring line in which the hold-time error is improved by performing a wiring line extension process, the wiring line is included in a path having the hold-time error; calculating, for the extracted wiring line, a wiring line extension distance corresponding to an insertion delay value that improves the hold-time error; and performing the wiring line extension process to extend the extracted wiring line by the calculated wiring line extension distance. | 01-26-2012 |
20120036490 | INFORMATION PROCESSING DEVICE AND DESIGN SUPPORTING METHOD - An information processing device comprises, a physical property value generation unit to generate a plurality of physical property values for changing signal propagation time of a target path including a plurality of circuit elements within a predetermined fluctuation range, an element delay calculation unit to calculate delay time of each of signals passing through the circuit element in accordance with each of the generated physical property values and a propagation time calculation unit to calculate the signal propagation time of the target path on the basis of the delay time of the signals. | 02-09-2012 |
20120072880 | Sensitivity-based complex statistical modeling for random on-chip variation - The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). | 03-22-2012 |
20120089958 | Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices - A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD. | 04-12-2012 |
20120096420 | INTELLIGENT ARCHITECTURE CREATOR - Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
20120096421 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, DATA PROCESSING METHOD THEREOF, AND CONTROL PROGRAM THEREOF - A semiconductor integrated circuit design apparatus ( | 04-19-2012 |
20120117527 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner. | 05-10-2012 |
20120124537 | SLACK-BASED TIMING BUDGET APPORTIONMENT - A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to being replaced with comparatively faster logic may be identified during timing budget apportionment, such that the magnitude of the slack reported for those units can be adjusted to account for such potential performance improvements. Then, when timing budgets are reapportioned using the slack calculated for each unit, additional slack is available to be reapportioned to those units needing larger timing budgets. | 05-17-2012 |
20120124538 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-17-2012 |
20120131530 | PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION - A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions. | 05-24-2012 |
20120131531 | Reducing Leakage Power in Integrated Circuit Designs - A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values. | 05-24-2012 |
20120137263 | TIMING CLOSURE IN CHIP DESIGN - Disclosed are a method and system for improving timing closure in chip design. The method comprises: identifying a critical timing path in a chip design pattern, wherein a timing window of the critical timing path is smaller than a predetermined timing window; determining a variation of each segment of the critical timing path, wherein the variation indicates uncertainty of delay of a device and/or a wire caused by one or more factors; and changing at least one segment of the critical timing path based on the variation of each segment of the critical timing path to enlarge the timing window of the critical timing path. The method and system may enlarge a timing window of a critical timing path by reducing the variation thereof, thereby achieving timing closure in the chip design pattern. | 05-31-2012 |
20120144357 | Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure - A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit. | 06-07-2012 |
20120144358 | Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs - A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated. | 06-07-2012 |
20120144359 | CYCLE CUTTING WITH TIMING PATH ANALYSIS - The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow. | 06-07-2012 |
20120159414 | Simultaneous Multi-Corner Static Timing Analysis Using Samples-Based Static Timing Infrastructure - A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably, each operation has a single control flow and uses vectors of samples for performing the plurality of operations. Each sample is a value associated with a corner. This method minimizes computational resource and memory usage as well as accelerates the turn around time of multi-corner analysis. | 06-21-2012 |
20120159415 | METHOD AND APPARATUS FOR PROVIDING TIMING INFORMATION WHILE DESIGNING A MULTI-CELL CIRCUIT - A method and apparatus are described for providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit. A circuit design comprising a plurality of cells is displayed to the user. Each cell includes a pre-characterized circuit structure. A graphical user interface (GUI) may be used to request a cell placement change, a design connectivity change or a cell type change. The circuit design is modified to implement the requested change, an incremental static timing analysis is performed, and the resulting timing information associated with the requested change is presented on the displayed circuit design. Timing information may be displayed directly on a cell that receives an output from the particular cell, and/or may be displayed adjacent to the particular cell. The timing information may include current and previous frequency slack information associated with each input and output pin of the particular cell. | 06-21-2012 |
20120159416 | Constructing a Clock Tree for an Integrated Circuit Design - A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices. | 06-21-2012 |
20120174049 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 07-05-2012 |
20120174050 | METAL DENSITY AWARE SIGNAL ROUTING - Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit. | 07-05-2012 |
20120180015 | SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT - A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. | 07-12-2012 |
20120192135 | METHODS FOR ANALYZING CELLS OF A CELL LIBRARY - Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a utilization metric for the pin of the cell based on the plurality of routed connection locations and a plurality of possible connection locations for the pin, and displaying the utilization metric on a display device. | 07-26-2012 |
20120192136 | ORDERING OF STATISTICAL CORRELATED QUANTITIES - Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity. | 07-26-2012 |
20120204137 | SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE - The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package. | 08-09-2012 |
20120204138 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 08-09-2012 |
20120210286 | ADDING FINE GRAIN TUNING CIRCUITRY TO INTEGRATED CIRCUIT DESIGN - A method for adding fine grain tuning circuitry to an integrated circuit design is disclosed. In one aspect, the method includes providing a design elaborated to have representations of generic logic components and interconnections between the generic logic components, automatically selecting those of the generic logic components which are in critical timing paths, and amending the design to add the fine grain tuning circuitry automatically to the selected generic logic components in the elaborated design for use in maintaining the critical timing paths during operation of the integrated circuit. By adding the circuitry at this lower level of design while it is still generic, before the synthesis stage, the additions can be made more quickly and with less disruption to the design process. | 08-16-2012 |
20120210287 | Circuit Timing Analysis Incorporating the Effects of Temperature Inversion - Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner. | 08-16-2012 |
20120216163 | TIMING ANALYSIS METHOD, TIMING ANALYSIS APPARATUS, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING TIMING ANALYSIS PROGRAM - A timing analysis method includes performing voltage drop analysis of a circuit laid out on a semiconductor chip, creating a voltage drop region file representing voltage drop on the semiconductor chip as regions at given voltage ranges based on a result of the voltage drop analysis, calculating second OCV factors respectively corresponding to the given voltage ranges contained in the voltage drop region file for each of the regions by using an OCV factor file containing first OCV factors representing variation of delay in association with given voltages in consideration of voltage drop, creating an OCV region file containing the calculated second OCV factors and the regions in association with each other, performing delay calculation of the laid-out circuit by using a delay library, and performing timing analysis by using the delay calculation result and the second OCV factors for each of the regions contained in the OCV region file. | 08-23-2012 |
20120221992 | METHOD OF SUPPORTING LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a method of supporting a layout design, a net list of an integrated circuit is divided into net lists of clock domain circuit aggregations. A timing constraint is generated to each of the clock domain circuit aggregations. An arrangement order of the clock domain circuit aggregations is determined to satisfy the timing constraint. A layout of the integrated circuit is generated by carrying out arrangement and wiring of the clock domain circuit aggregations based on the arrangement order. | 08-30-2012 |
20120233580 | TIMING VERIFICATION SUPPORT DEVICE, METHOD, AND PROGRAM - A timing verification support device includes: a storage device to store first circuit data of a semiconductor integrated circuit; a search unit to identify, in the first circuit data, a plurality of circuit elements including a designated circuit element designated as a timing verification target and at least one circuit element included in a path traced when performing timing verification at a boundary between the designated circuit element and a portion other than the designated circuit element; and a generation unit to generate second circuit data for the timing verification including circuit data of the plurality of circuit elements. | 09-13-2012 |
20120240089 | EVENT SCHEDULER FOR AN ELECTRICAL CIRCUIT DESIGN TO ACCOUNT FOR HOLD TIME VIOLATIONS - Implementations of the present disclosure involve an apparatus and/or method for identifying and classify nodes of an electrical circuit design to account for hold time violations occurring within the circuit. The nodes may be ordered based on a criticality of the nodes that may aid in identifying those nodes of the circuit where hold time violations may be corrected. In one embodiment, the criticality may relate to the number of potentially violating paths that utilize the identified nodes such that corrective measures applied at those nodes may correct several hold time violating paths. In addition, criticality may be scaled utilizing an available buffer library and other timing information. Thus, by utilizing the methods and/or apparatuses of the present disclosure, the locations where timing violation corrective measures may be applied that improve or correct several violating data paths at once may be identified in such a manner so as to reduce the number of overall corrections made to the circuit design, reducing the cost and necessary time associated with the corrections. | 09-20-2012 |
20120240090 | CLOCK TREE DESIGNING APPARATUS AND CLOCK TREE DESIGNING METHOD - A clock tree designing apparatus in an embodiment includes: an equidistant point set calculation section configured to set a path setting block area in which a path length of a clock path takes a shortest Manhattan distance and determine a set of equidistant points between a target sink and a farthest sink; a branch point setting section configured to set, as a branch point, a point in the set of equidistant points that is farthest from a clock source within the path setting block area; and a path setting section configured to set a shared path for the target sink and the farthest sink within the path setting block area from the clock source to the branch point, and to set a clock path from the branch point to the target sink or the farthest sink. | 09-20-2012 |
20120240091 | Multi-Mode Multi-Corner Clocktree Synthesis - A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. | 09-20-2012 |
20120246605 | STATIC TIMING ANALYZER, METHOD FOR ANALYZING STATIC TIMING AND MEDIUM STORING COMPUTER PROGRAM FOR MAKING COMPUTER PROCESSOR ANALYZE STATIC TIMING - According to one embodiment, a static timing analyzer includes a time function generator, a slack function generator, a power domain voltage constant determination module, a slack value calculator, and an output module. The time function generator generates a time function based on a netlist, timing information, timing constraints information, and power domain information. The slack function generator generates a slack function based on the timing constraints information and the time function. The power domain voltage constant determination module determines a power voltage constant of the slack function based on the power domain information and the slack function such that the slack function is minimized between minimum and maximum voltages of power of the power voltage. The slack value calculator substitutes the power domain voltage constant for the slack function to calculate a slack value. The output module outputs the time function, the slack function, and the slack value. | 09-27-2012 |
20120246606 | GENERATION OF AN END POINT REPORT FOR A TIMING SIMULATION OF AN INTEGRATED CIRCUIT - A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics. | 09-27-2012 |
20120278778 | Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis - A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete. | 11-01-2012 |
20120278779 | CHARACTERIZATION DEVICE AND COMPUTER PROGRAM THEREOF - A characterization device capable of extracting the characteristic values of high-reliability hard macros at high speed. A characteristic value extraction unit calculates the delay time at measurement points within the hard macro and extracts the characteristic values by applying a slew to the signal waveform that is inputted to the hard macro and making a static path search. A dynamic verification unit verifies whether the characteristic values are adequate or not by carrying out a dynamic verification of the hard macro utilizing the characteristic values extracted by the characteristic value extraction unit. The characterization device can therefore shorten the time required to make a dynamic verification, and further is capable of extracting the characteristic values of high-reliability hard macros at high-speed. | 11-01-2012 |
20120278780 | TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING - A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level. | 11-01-2012 |
20120284679 | INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS - A computer-executed method for designing dummy metal object locations in an integrated circuit design. The method comprises the steps of: a) receiving an integrated circuit design as input; b) finding areas of the integrated circuit design that do not meet a minimum metal density requirement; c) finding areas of the integrated circuit design having a critical timing path; d) blocking empty routing tracks that are adjacent to critical nets of the critical timing paths located in step (c), for prospective dummy metal object placement for the areas commonly located in both of steps (b) and (c); and e) placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas that were found in step (b), but were not blocked in step (d). | 11-08-2012 |
20120284680 | METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT - A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-variation (OCV) margin from clock paths, removable OCV margin from data paths, removable IR drop margin from clock paths, and removable interconnects margin. At the timing analysis stage of a design flow, the method and apparatus determines the value of pessimism in the timing critical paths based on timing correlation between adjacent timing critical paths. In response to the determination, the value of pessimism may be reduced in the static timing analysis of the adjacent timing critical paths to optimize the timing performance of the integrated circuit at its desired clock frequency range. | 11-08-2012 |
20120284681 | CIRCUIT DESIGNING METHOD AND CIRCUIT DESIGNING SYSTEM - A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease. | 11-08-2012 |
20120317529 | Rapid Estimation of Temperature Rise in Wires Due to Joule Heating - A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations. | 12-13-2012 |
20120324410 | AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANALYSIS - Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode. | 12-20-2012 |
20120324411 | INTEGRATED CIRCUIT OPTIMIZATION MODELING TECHNOLOGY - A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results. | 12-20-2012 |
20130031523 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 01-31-2013 |
20130036395 | EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS - Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset. | 02-07-2013 |
20130047130 | EARLY NOISE DETECTION AND NOISE AWARE ROUTING IN CIRCUIT DESIGN - A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level. | 02-21-2013 |
20130047131 | DELAY TIME CALCULATING APPARATUS AND METHOD - An apparatus calculates a delay time of nets within a circuit included in design data by a processing unit. The processing unit performs a process that includes selecting a first calculation to calculate the delay time of a net when the net satisfies a first condition, when the first calculation is not selected by the selecting, selecting the first or second calculation to calculate the delay time of the net, depending on whether the net satisfies a second condition, and calculating the delay time of the net by the first or second calculation selected by the selecting. | 02-21-2013 |
20130061191 | AUTOMATED FUNCTIONAL COVERAGE FOR AN INTEGRATED CIRCUIT DESIGN - A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations. | 03-07-2013 |
20130061192 | Re-Modeling a Memory Array for Accurate Timing Analysis - A system and method for analyzing the timing requirements of a memory array are disclosed. The memory cell circuitry used in the original memory array may utilize two bi-directional passgate transistors which are both used during read and write operations on the memory cell, e.g., where signals can flow across the passgate transistors in two directions. A model of the memory array may be created according to a memory cell model that uses uni-directional passgate transistors. Modeling the memory array with uni-directional circuitry may enable a static timing analysis tool to determine the critical path through the memory array. Once the critical path has been determined from the model of the memory array, a dynamic simulation of the critical path in the original memory array may be performed to accurately determine the timing requirements of the original memory array. | 03-07-2013 |
20130074025 | POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE - A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path. | 03-21-2013 |
20130080986 | TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLTAGE DROP INTO ACCOUNT - A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply. | 03-28-2013 |
20130080987 | METHOD AND APPARATUS FOR SIMULTANEOUS SWITCHING NOISE OPTIMIZATION - Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. | 03-28-2013 |
20130080988 | IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME - A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits. | 03-28-2013 |
20130086542 | METHOD AND APPARATUS FOR PATTERN ADJUSTED TIMING VIA PATTERN MATCHING - An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic. | 04-04-2013 |
20130091480 | PARASITIC EXTRACTION FOR SEMICONDUCTORS - Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points. | 04-11-2013 |
20130097568 | GLOBAL CLOCK HANDLER OBJECT FOR HDL ENVIRONMENT - A global clock handler module for use in a hardware description language (HDL) environment is disclosed. An HDL module may include one or more clock statements. When a computer system executes the clock statements, a clock handler object may be called. The clock handler object may generate simulated clock signals for one or more simulated functional blocks of an integrated circuit design. Each simulated clock may be assigned to a separate and unique thread. The clock handler object may be a singleton object configured to manage each simulated clock signal for an integrated circuit design. Generation and control of each simulated clock signal may be performed by the clock handler object in a dynamic array. The dynamic array may include elements specifying parameters for each of the simulated clock signals. | 04-18-2013 |
20130104092 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE - In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree. | 04-25-2013 |
20130125076 | DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING - A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test. | 05-16-2013 |
20130139121 | RC Extraction Methodology for Floating Silicon Substrate with TSV - The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows. | 05-30-2013 |
20130145333 | STATISTICAL CLOCK CYCLE COMPUTATION - Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA. | 06-06-2013 |
20130152034 | SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING - A system for, and method of, reducing IC timing derating for a path in an integrated circuit design. In one embodiment, the system includes an electronic design automation tool configured to (1) extract circuit data regarding cells in the path and (2) calculate a timing derating for the path based at least in part on a determination as to whether the cells are simple cells. | 06-13-2013 |
20130159950 | METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT - A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump | 06-20-2013 |
20130159951 | SIGNAL SIMULATION DEVICE, SIGNAL RECORDING AND SIMULATION TESTING METHOD - A signal simulation device, a signal recording and simulation testing method for capturing a testing signal sent out by a test host and sending out a corresponding testing signal to a to-be-tested device. The signal simulation device comprises an input interface, a timer, a processing unit and a signal capturing unit. The signal capturing unit is electrically connected to the input interface, the timer and the processing unit. The testing signal is recorded by the signal capturing unit through the input interface. When the signal simulation device is switched to a recording status, the signal simulation device is electrically connected to the test host through the input interface to receive the testing signal. The clock cycle of the timer is adjusted according to the testing signal. The processing unit is used for setting the clock cycle of the timer. | 06-20-2013 |
20130159952 | COMBINING MULTIPLE TIMING MODES OF INTEGRATED CIRCUIT - A method and system for combining multiple timing modes of an integrated circuit. The method includes the steps of: creating logic groups for at least one logic device in the circuit according to at least one clock driving the at least one logic device, performing static timing analysis to the circuit in multiple given timing modes, obtaining at least one relationship between the logic groups in each of the multiple given timing modes according to a result of the static timing analysis, and combining the obtained at least one relationship between the logic groups in each of the multiple given timing modes | 06-20-2013 |
20130159953 | PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS - In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner. | 06-20-2013 |
20130179852 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 07-11-2013 |
20130227510 | DATABASE BASED TIMING VARIATION ANALYSIS - A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design. | 08-29-2013 |
20130239078 | OPTIMIZING TIMING CRITICAL PATHS BY MODULATING SYSTEMIC PROCESS VARIATION - Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element. | 09-12-2013 |
20130239079 | SYSTEM AND METHOD FOR TAKING INTER-CLOCK CORRELATION INTO ACCOUNT IN ON-CHIP TIMING DERATING - One aspect provides a system for taking inter-clock correlation into account in on-chip timing derating. The system comprises a storage medium and an electronic design automation tool. The storage medium is configured to store data and clock path setup and hold early and late derate data. The electronic design automation tool is configured to employ at least some of said data and clock path setup and hold early and late derate data to calculate setup and hold slacks and total derate that take into account a correlation in delay variation between first and second clock paths as a function of depths thereof. | 09-12-2013 |
20130239080 | HIERARCHICAL BOTTOM-UP CLOCK DOMAIN CROSSING VERIFICATION - Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules. | 09-12-2013 |
20130239081 | Circuit Design and Retiming - A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of latencies, the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a node between a first input of the portion of the circuit and an input of a register of the portion of the circuit. The method continues to retime the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor. | 09-12-2013 |
20130246991 | Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis - A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete. | 09-19-2013 |
20130254731 | ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS - A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical. | 09-26-2013 |
20130263075 | UTILIZING GATE PHASES FOR CIRCUIT TUNING - Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase, each device is given a phase designation based upon expected performance of the device in the circuit. If the device is expected to be in a critical path or has a minimum timing slack, the device is placed on the fast phase. If the device is not in a critical path or has excess timing slack the device is placed on the slow phase. | 10-03-2013 |
20130275935 | PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS - An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase. | 10-17-2013 |
20130275936 | INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD - A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value. | 10-17-2013 |
20130283222 | NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL AND/OR A TECHNOLOGY LIBRARY CELL TYPE - Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches. | 10-24-2013 |
20130283223 | ENABLING STATISTICAL TESTING USING DETERMINISTIC MULTI-CORNER TIMING ANALYSIS - In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data. | 10-24-2013 |
20130283224 | METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT - A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump. | 10-24-2013 |
20130298097 | METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER - A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment. | 11-07-2013 |
20130298098 | METHOD AND SYSTEM FOR HIGH SPEED AND LOW MEMORY FOOTPRINT STATIC TIMING ANALYSIS - The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware. | 11-07-2013 |
20140007034 | ROUTING OF LOCAL CLOCK INTERCONNECTS | 01-02-2014 |
20140013292 | STATIC TIMING ANALYSIS METHOD AND SYSTEM CONSIDERING CAPACITIVE COUPLING AND DOUBLE PATTERNING MASK MISALIGNMENT - A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths. | 01-09-2014 |
20140040844 | Method for Achieving An Efficient Statistical Optimization of Integrated Circuits - Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected. | 02-06-2014 |
20140047404 | TIMING-AWARE TEST GENERATION AND FAULT SIMULATION - Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs. | 02-13-2014 |
20140059508 | Determining A Design Attribute By Estimation And By Calibration Of Estimated Value - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 02-27-2014 |
20140068536 | NON-TRANSITORY COMPUTER READABLE MEDIUM STORING TIMING ANALYSIS PROGRAM, TIMING ANALYSIS DEVICE, AND TIMING ANALYSIS METHOD - A timing analysis device includes a storage unit and a processing unit. The processing unit performs storage processing and analysis processing. The storage processing stores circuit information of a circuit to be analyzed, timing constraint information defining timing constraints on the circuit, delay information defining a plurality of delay values associated with a plurality of cells constituting the circuit, and delay upper limit information including at least one delay upper limit for setting an upper limit to the plurality of delay values associated with the plurality of cells into a storage unit. The analysis processing generates a timing analysis result of a circuit to be analyzed, with delay value change processing that changes at least one of the plurality of delay values to the delay upper limit, using the changed delay upper limit in addition to the circuit information, the timing constraint information and the delay information. | 03-06-2014 |
20140068537 | STATIC TIMING ANALYSIS METHOD AND SYSTEM CONSIDERING CAPACITIVE COUPLING AND DOUBLE PATTERNING MASK MISALIGNMENT - A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths. | 03-06-2014 |
20140075403 | REDUNDANCY FOR ON-CHIP INTERCONNECT - One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields. | 03-13-2014 |
20140082576 | GRADIENT AOCV METHODOLOGY ENABLING GRAPH-BASED TIMING CLOSURE WITH AOCV TIMING MODELS - A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells. | 03-20-2014 |
20140089879 | CHARACTERIZATION BASED BUFFERING AND SIZING FOR SYSTEM PERFORMANCE OPTIMIZATION - A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration. | 03-27-2014 |
20140089880 | METHOD AND SYSTEM TO FIX EARLY MODE SLACKS IN A CIRCUIT DESIGN - An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value. | 03-27-2014 |
20140089881 | Circuit Timing Analysis Incorporating the Effects of Temperature Inversion - Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner. | 03-27-2014 |
20140096099 | GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS - A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform. | 04-03-2014 |
20140096100 | METHOD OF SHARING AND RE-USING TIMING MODELS IN A CHIP ACROSS MULTIPLE VOLTAGE DOMAINS - A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts. | 04-03-2014 |
20140115552 | SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS - Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor. | 04-24-2014 |
20140137062 | PATTERN MATCHING BASED PARASITIC EXTRACTION WITH PATTERN REUSE - The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously. | 05-15-2014 |
20140149956 | CORNER SPECIFIC NORMALIZATION OF STATIC TIMING ANALYSIS - A method and a system for expressing results of a timing analysis of an integrated circuit (IC) chip design as relative values to drive efficient chip design closure include: using a computer, performing the timing analysis to compute timing results of the chip design across at least two design corners; applying corner specific normalization equations to the timing analysis results from each of the at least two corners to obtain normalized timing results; and using the timing results ordered and filtered by the normalized timing results of the IC chip design for the design closure prior to chip manufacture. The slacks are normalized to provide insight into the degree of difficulty of the required fixes for that slack across corners. Given multiple analyses, the slacks are fixed in a correct order across corners and paths, avoiding inefficient circuit solutions or cost greater design effort. | 05-29-2014 |
20140165018 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay. | 06-12-2014 |
20140181771 | METHOD AND APPARATUS FOR ENHANCED STATIC IR DROP ANALYSIS - Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources. | 06-26-2014 |
20140195995 | SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS - Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters. | 07-10-2014 |
20140215423 | SEMICONDUCTOR DEVICE DESIGN METHOD AND DESIGN APPARATUS - A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section. | 07-31-2014 |
20140223400 | NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL TYPE - Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches. | 08-07-2014 |
20140258954 | RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS - Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution. | 09-11-2014 |
20140258955 | Metal Interconnect Modeling - A method for modeling metal routing includes extracting physical parameters of a metal interconnect for a circuit design, determining a resistance value from a database of metal interconnects with the extracted physical parameters, the resistance value being at a maximum frequency of a frequency range to be simulated, modeling the interconnect with a symmetric lumped transmission line model, and defining a resistance value of the lumped transmission line model to be about 1.05-1.3 times the resistance value taken from the database. | 09-11-2014 |
20140258956 | APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS - A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD. | 09-11-2014 |
20140282335 | PHASE DETERMINATION FOR EXTRACTION FROM SCATTERING PARAMETERS - Scattering (S) parameters can be evaluated for a plurality of conductors on a semiconductor device to determine phase based on traversal around a Smith chart type representation. A propagation function for the plurality of conductors can be derived from S parameters, which in turn, can be used to derive resistance, inductance, capacitance, and/or conductance parameters. A Smith chart representation is used to obtain zero crossing information for determination of accurate phase information. | 09-18-2014 |
20140289689 | WIRING INSPECTION APPARATUS AND WIRING INSPECTION METHOD - A wiring inspection apparatus includes a first calculating unit, a second calculating unit, and an output unit. The first calculating unit calculates the number of components arranged along two sides, one of which extends in a first direction and the other one of which extends in a second direction, of a minimum rectangle including a transmission component and a reception component. The second calculating unit calculates the number of the components arranged along the two sides at a predetermined arrangement density of relay components. When the number of the relay components is greater than the number of the components calculated by the second calculating unit, the output unit outputs information indicating the presence of a wiring extending in a direction opposite to a direction from the transmission component to the reception component among wirings connecting the transmission component, the reception component, and the relay components. | 09-25-2014 |
20140289690 | ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYNTHESIS (CTS) - On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact of OCV on clock skew. Next, the embodiments can construct a second set of clock tree topologies for timing sequential circuit elements that are not in the set of critical paths, wherein said constructing can comprise optimizing the second set of clock tree topologies to reduce latency, power consumption, and/or area. | 09-25-2014 |
20140298280 | REDUCING RUNTIME AND MEMORY REQUIREMENTS OF STATIC TIMING ANALYSIS - Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis. | 10-02-2014 |
20140298281 | METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTREAM IMPLEMENTATION FLOW - System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files. Using the results of this top-down global design-closure method the designers can use the generated floor-plan to guide downstream tools to achieve predictable and correlatable design implementation. | 10-02-2014 |
20140331196 | ANALYZING SPARSE WIRING AREAS OF AN INTEGRATED CIRCUIT DESIGN - A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization metric of each net in the set of sparse nets. One or more target nets are selected from the set of sparse nets, based on the timing margin of the target nets. The target nets may be modified. | 11-06-2014 |
20140337813 | METHOD AND APPARATUS FOR EXTRACTING DELAY PARAMETER - A delay parameter extracting apparatus includes a schematic composing unit, a layout composing unit, a verification unit, and a parameter extracting unit. The schematic composing unit is configured to: facilitate design of a schematic circuit; and generate a first net list based on the design of the schematic circuit. The layout composing unit is configured to: facilitate design of a layout based on the schematic circuit; and generate a second net list based on the design of the layout. The verification unit is configured to verify the layout by comparing the first net list to the second net list. The parameter extracting unit is configured to: extract capacitance (C) values from the layout; and extract delay parameters based on the C values with respect to respective nets according to types of delay parameters associated with the respective nets. | 11-13-2014 |
20140351778 | LSI DESIGN APPARATUS AND METHOD OF DESIGNING LSI - According to one embodiment, a LSI design apparatus includes a first logic synthesis portion executing a design of a LSI in a logic gate level, a extraction portion extracting paths from the LSI, a determination portion determining a character of each of the paths, a parameter setting portion setting an upper limit of a transition time of a signal on each of the paths independently based on the character of each of the paths, and a second logic synthesis portion revising the design of the LSI generated in the first logic synthesis portion by optimizing each of the paths so that each of the paths satisfies the upper limit of the transition time of the signal. | 11-27-2014 |
20140372961 | System and Method for Using Fabric-Graph Flow to Determine Resource Costs - A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use. | 12-18-2014 |
20150033197 | CLUSTERING FOR PROCESSING OF CIRCUIT DESIGN DATA - Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data. | 01-29-2015 |
20150033198 | INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING - A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements. | 01-29-2015 |
20150033199 | SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS - Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters. | 01-29-2015 |
20150040089 | NUMERICAL AREA RECOVERY - Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design. | 02-05-2015 |
20150040090 | DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS - Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized. | 02-05-2015 |
20150046890 | Method for Displaying Timing Information of an Integrated Circuit Floorplan - A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information. | 02-12-2015 |
20150052492 | ROUTING METHOD - A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit. | 02-19-2015 |
20150095866 | VLSI CIRCUIT SIGNAL COMPRESSION - An embedded agent ( | 04-02-2015 |
20150121327 | MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) CROSS-TIER CLOCK SKEW MANAGEMENT SYSTEMS, METHODS AND RELATED COMPONENTS - Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously. | 04-30-2015 |
20150121328 | PATH-BASED FLOORPLAN ANALYSIS - Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout. | 04-30-2015 |
20150135152 | Clock Tree Design - A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of detecting selection of the soft control, generates a plurality of clock tree solutions. The tool further causes a graphical form of a highlighted one of the clock tree solutions to be displayed in a second window of the GUI. An algorithm for generating the various clock tree solutions is also disclosed. | 05-14-2015 |
20150135153 | METHOD OF VALIDATING TIMING ISSUES IN GATE-LEVEL SIMULATION - A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated. | 05-14-2015 |
20150135154 | Apparatus and Methods for Optimization of Integrated Circuits - A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC). | 05-14-2015 |
20150143316 | APPARATUS AND METHODS FOR PARTITIONING AN INTEGRATED CIRCUIT DESIGN INTO MULTIPLE PROGRAMMABLE DEVICES - Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments include a bridge in each programmable logic device for providing synchronization and deterministic latency of packets sent between the programmable devices. | 05-21-2015 |
20150310152 | METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INTEGRATED CIRCUIT DESIGN - A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensated delay values. The method further includes identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage. | 10-29-2015 |
20150324508 | System and Method for Using Fabric-Graph Flow to Determine Resource Costs - A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use. | 11-12-2015 |
20150324513 | IDENTIFYING THE CAUSE OF TIMING FAILURE OF AN IC DESIGN USING SEQUENTIAL TIMING - A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure. | 11-12-2015 |
20150347653 | METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INTEGRATED CIRCUIT DESIGN - A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element. | 12-03-2015 |
20150356227 | PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF INSTANCE-BASED SYSTEMATIC VARIATIONS - A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data. | 12-10-2015 |
20150363530 | LSI DESIGN METHOD - Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs. | 12-17-2015 |
20150370955 | METHOD FOR ADJUSTING A TIMING DERATE FOR STATIC TIMING ANALYSIS - A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis. | 12-24-2015 |
20160012172 | PATH-BASED CONGESTION REDUCTION IN INTEGRATED CIRCUIT ROUTING | 01-14-2016 |
20160012173 | System and Method for Maintaining Slack Continuity in Incremental Statistical Timing Analysis | 01-14-2016 |
20160026745 | CLOCK TO OUT PATH OPTIMIZATION - A place and route technique is provided for a programmable logic device to optimize a delay difference between a clock to out path and a clock out path. | 01-28-2016 |
20160026746 | BUS-BASED CLOCK TO OUT PATH OPTIMIZATION - A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path. | 01-28-2016 |
20160034631 | METHOD OF GENERATING TECHFILE HAVING REDUCED CORNER VARIATION VALUE - A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value. | 02-04-2016 |
20160042112 | GENERATING ASSERTED SENSITIVITIES FOR STATISTICAL TIMING - One or more processors group a plurality of timing arcs into a plurality of equivalence classes. Each timing arc includes one or more delay tables. One or more processors generate, for at least one equivalence class of the plurality of equivalence classes, an average sensitivity to a condition by performing a weighted average on respective sensitivities of timing arcs to the condition. One or more processors determine a sensitivity of an electronic circuit to the condition based, at least in part, a match between one or more attributes of the electronic circuit and one or more attributes present in the at least one equivalence class. | 02-11-2016 |
20160070834 | AUGMENTED SIMULATION METHOD FOR WAVEFORM PROPAGATION IN DELAY CALCULATION - A system and a method are disclosed for performing static timing analysis. Information describing a distorted input waveform is received by a static timing analyzer. A transition time of the distorted input waveform is determined. Based on the determined input transition time a nominal input waveform and a corresponding nominal output waveform are received. An input waveform distortion is computed based on the nominal input waveform and the distorted input waveform. An output waveform distortion is computed based on an augmented circuit and the input waveform distortion. A distorted output waveform is computed based on the nominal output waveform and the output waveform distortion. The waveforms are represented using the distortion values which are smaller than the actual waveform values, thereby allowing for compact representation. A time-shifted version of an uncoupled input waveform is used to perform conservative timing analysis of circuits that accounts for crosstalk in the circuit. | 03-10-2016 |
20160070844 | SELECTIVELY REDUCING GRAPH BASED ANALYSIS PESSIMISM - A method, system or computer usable program product for improving a circuit design having a set of endpoint circuits including identifying a subset of the set of endpoint circuits for further timing analysis based on graph based analysis (GBA) of the circuit design; performing path based analysis (PBA) of a set of endpoint circuit paths in the subset of endpoint circuits; and providing a timing margin between graph based analysis and path based analysis for each of the set of endpoint circuit paths for reducing pessimism in subsequent graph based analysis of the set of endpoint circuit paths. | 03-10-2016 |
20160103947 | METHOD AND APPARATUS FOR EMULATION AND PROTOTYPING WITH VARIABLE CYCLE SPEED - A hardware verification system includes, in part, a multitude of programmable devices and a system clock. The hardware verification system receives a circuit design and generates a variable period clock from the system clock by analyzing propagation delays in different signal paths of the circuit design. The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, in which M>N. The variable period clock is applied to at least one of the programmable devices to verify the circuit design. | 04-14-2016 |
20160110483 | METHOD OF OPERATING SIMULATOR COMPENSATING FOR DELAY AND DEVICE FOR PEROFMRING THE SAME - A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description. | 04-21-2016 |
20160110492 | Error Resilient Digital Signal Processing Device - The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data. | 04-21-2016 |
20160117433 | INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION - As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein. | 04-28-2016 |
20160117436 | SYSTEM AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT - A system and method are provided for compiling an integrated circuit design are described. A web-based client accessible from a personal computer provides access for a user to a network-based server where the user is able to provide an integrated circuit design for compilation. The system propagates values into pertinent parameters for compilation of the circuit design, and further, provides strategies and suggestions based on analysis of past results for propagating values for a plurality of compilation sequences. Compilation of the integrated circuit design is carried out on server-based computing resources by way of parallel compilation of the plurality of compilation sequences, allowing for concurrent time-saving operation. | 04-28-2016 |
20160154918 | METHOD FOR ESTIMATION OF DELAYS AND SLEWS DURING CIRCUIT OPTIMIZATION | 06-02-2016 |
20160203249 | METHOD OF ANALYSING BEHAVIOUR OF AN INTEGRATED CIRCUIT IMPLEMENTED BY COMPUTER AND COMPRISING THE SELECTING OF PATHS ON THE BASIS OF SEVERAL CRITERIA BELONGING TO DIFFERENT TYPES | 07-14-2016 |
20160203251 | MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS | 07-14-2016 |
20160378901 | APPLYING RANDOM NETS CREDIT IN AN EFFICIENT STATIC TIMING ANALYSIS - A method may include: specifying a random noise credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; performing an initial noise-free timing analysis of the IC design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; marking all nets, including fan-in and fan-out cones, connected to each net that exceeds the upper bound; and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all marked nets, to adjust the initial IC design, to close timing and generate a final IC design. | 12-29-2016 |
20160378903 | DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE - Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table. | 12-29-2016 |